LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller Note

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LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller Note

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LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller Notebook CPUs
LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller Notebook CPUs
LM2633 feature-rich that combines three regulator controllers current mode synchronous buck regulator controllers linear regulator controller. switching regulator controllers operate 180° phase. This feature reduces input ripple current, resulting smaller input filter. first switching controller (Channel features Intel mobile compatible precision 5-bit digital-to-analog converter which programs output voltage from 0.925V 2.00V. also compatible with dynamic requirements. second switching controller (Channel adjustable between 1.25V 6.0V. synchronous rectification pulse-skip operation light load achieves high efficiency over wide load range. Fixed-frequency operation obtained disabling pulse-skip mode. Current-mode feedback control assures excellent line load regulation wide loop bandwidth good response fast load transient events. Current mode control achieved through sensing thus external sense resistor necessary. power good signal available indicate general health output voltages. unique feature analog soft-start switching controllers independent slew rate input voltage. This will make soft start behavior more predictable controllable. internal rail available externally boot-strap circuitry (only) when available from other sources. Current limit either switching channels achieved through sensing value adjustable. switching controllers have under-voltage over-voltage latch protections, linear regulator under-voltage latch protection. Under-voltage latch disabled delayed programmable amount time. input voltage switching channels ranges from 30V, which makes possible choice different battery chemistries options.
Features
GENERAL Three regulated output voltages 4.5V input range Power good function Input under-voltage lockout Thermal shutdown Tiny TSSOP package SWITCHING SECTION channels operating 180° phase Separate on/off control each channel Current mode control without sense resistor Skip-mode operation available Adjustable cycle-by-cycle current limit Negative current limit Analog soft start independent input voltage slew rate Power ground pins separate Output Programmable output delay 250kHz switching frequency (for 17V) Channel output from 0.925V 2.00V 1.5% accuracy from 125°C 1.7% initial tolerance Channel Dynamic change ready Power good flags changes Channel output from 1.3V 6.0V LINEAR SECTION Output voltage adjustable 50mA maximum driving current Output initial tolerance
Applications
Power supply CPUs notebook that require SpeedSteptechnique Power supply information appliances General voltage DC/DC buck regulators
SpeedStepis trademark Intel Corporation.
2001 National Semiconductor Corporation
DS200008
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LM2633
Connection Diagram
VIEW
PGOOD (Pin 13): constant monitor output voltages. indicates general health regulators. more information, Power Good Truth Table (Table Power Good Function Operation Descriptions. (Pin 16-17): Low-noise analog ground. (Pin 18): Connect base gate linear regulator pass transistor. OUT3 (Pin 19): Connect output linear regulator. (Pin 21): feedback input linear regulator, connected center external resistor divider. COMP2 (Pin 22): Channel compensation network connection (it's output voltage error amplifier). (Pin 23): feedback input Channel Connect center output resistor divider. SENSE2 (Pin 24): Remote sense Channel This used skip-mode operation. ILIM2 (Pin 25): Current limit threshold setting Channel sinks constant current. resistor connected between this MOSFET drain. voltage across this resistor compared with MOSFET determine over-current condition occurred Channel (Pin 27): Kelvin sense drain MOSFET Channel (Pin 29): Switch-node connection Channel which connected source MOSFET. HDRV2 (Pin 30): gate-drive output Channel HDRV2 floating drive output that rides voltage. CBOOT2 (Pin 31): Bootstrap capacitor connection Channel gate drive. positive supply rail Channel gate drive. VDD2 (Pin 32): supply rail Channel bottom gate drive. LDRV2 (Pin 33): Bottom gate-drive output Channel PGND2 (Pin 34): Power ground Channel (Pin 35): regulator input voltage supply. VLIN5 (Pin 36): output internal linear regulator. Bypass ground with ceramic capacitor. When regulator input voltage this tied improve light-load efficiency. PGND1 (Pin 38-39): Power ground Channel LDRV1 (Pin 40-41): Bottom gate-drive output Channel VDD1 (Pin 42): supply rail Channel bottom gate drive. CBOOT1 (Pin 43): Bootstrap capacitor connection Channel gate drive. positive supply rail Channel gate drive. HDRV1 (Pin 44): gate-drive output Channel HDRV1 floating drive output that rides voltage. (Pin 45): Switch-node connection Channel which connected source MOSFET. (Pin 46): Kelvin sense drain MOSFET Channel ILIM1 (Pin 48): Current limit threshold setting Channel sinks constant current. resistor connected between this MOSFET drain. voltage across this resistor compared with MOSFET determine over-current condition occurred Channel
20000801
48-Lead TSSOP (MTD) Order Number LM2633MTD Package Number MTD48
Descriptions
(Pin 1):The feedback input Channel Connect load directly. COMP1 (Pin Channel compensation network connection (connected output voltage error amplifier). (Pins 47): internal connection. ON/SS1 (Pin Adding capacitor this provides soft-start function which minimizes inrush current output voltage overshoot; lower than 0.8V input (open-collector type) this turns Channel also both ON/SS1 ON/SS2 pins below 0.8V, whole goes into shut down mode. soft-start capacitor voltage will eventually charged whichever lower. ON/SS2 (Pin Adding capacitor this provides soft-start function which minimizes inrush current output voltage overshoot; lower than 0.8V input (open-collector type) this turns Channel also both ON/SS1 ON/SS2 pins below 0.8V, whole goes into shut down mode. soft-start capacitor voltage will eventually charged whichever lower. VID4-0 (Pins 6-10): Voltage identification code. Each internal pull-up. They accept open collector compatible 5-bit binary code from CPU. code table shown Table DELAY (Pin 11): capacitor from this ground adjusts delay output under-voltage lockout. FPWM (Pin 12): When FPWM low, pulse-skip mode operation light load disabled. regulator forced operate constant frequency mode.
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Block Diagrams
LM2633
20000802
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LM2633
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20000886
Block Diagrams
(Continued)
Block Diagrams
(Continued)
LM2633
20000803
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LM2633
TABLE Shut Down Latch Truth Table Input ovp1 other combinations
Note '=1' means least variable high. Note 'Fault' logic UVLO thermal shutdown. Note 'Cap' means capacitor appropriate value between ground. Note Positive logic used. Note meanings variables, refer block diagrams. Note blank value means 'don't care'.
Output fault ssto1 ssto2 uv_delay latch
ovp2
uvp1
uvp2
uvplr
TABLE Power Good Truth Table Input ovp1 other combinations
Note means least variable low. Note Positive logic used. Note blank value means 'don't care'. Note meanings variables, refer block diagrams.
Output fault latch PGOOD
ovp2
uvpg1
uvpg2
uvpglr
TABLE Code Output VID4 VID3 VID2 VID1 VID0 Voltage CPU*
0.925
0.950 0.975 1.000 1.025 1.050 1.075
1.100
1.125 1.150 1.175 1.200 1.225
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LM2633
TABLE Code Output (Continued) VID4 VID3 VID2 VID1 VID0 Voltage 1.250 1.275
1.30 1.35 1.40
1.45
1.50 1.55 1.60
1.65 1.70 1.75 1.80 1.85 1.90 1.95
2.00
*This code 0.900V convenience.
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LM2633
Absolute Maximum Ratings
(Note
Rating (Note Ambient Storage Temperature Range
-65°C +150°C
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Voltages from indicated pins GND/PGND: VIN, KS1, KS2, SW1, ILIM1, ILIM2 VID0-VID4 VLIN, VDD1, VDD2, PGOOD FB1, FB2, SENSE2, FB3, OUT3 CBOOT1 CBOOT2 ON/SS1, ON/SS2 FPWM Power Dissipation 25°C), (Note Junction Temperature -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V SW1+ -0.3V SW2+ -0.3V -0.3V 1.56W +150°C
Soldering Dwell Time, Temperature (Note Wave sec, 260°C Infrared 10sec, 240°C Vapor Phase 75sec, 219°C
Operating Ratings(Note
(VIN VLIN5 tied together) (VIN VLIN5 separate) Junction Temperature Junction Temperature VDD1, VDD2 4.5V 5.5V 5.0V +125°C -40°C +125°C 4.5V 5.5V
Electrical Characteristics
+15V unless otherwise indicated under Conditions column. Typicals limits appearing plain type apply +25°C. Limits appearing boldface type apply over +125°C. Symbol SYSTEM Vout1_load Vout2_load Ivin Channel Load Regulation (Note Channel Load Regulation (Note Line Regulation (for switching regulators) Input Supply Current with Switching Channels Input Supply Current with Shut Down VLIN5 Output Voltage ILIM1 ILIM2 Pins Sink Current Negative Current Limit (SWx PGNDx voltage) Soft Start Charge Current Soft Start Sink Current Soft Start Threshold Soft Start Timeout Threshold UV_DELAY Threshold UV_DELAY Source Current VID4:0 Internal Pull Current (Note VLIN5 (Note UVLO thermal shutdown VCOMP1 moves from 0.5V 1.5V, VID4:0=01101 VCOMP2 moves from 0.5V 1.5V 5.0V 30V, VID4:0=01101 0.9V, VLIN5 Current (Note VON/SS1 VON/SS2 (Note IVLIN5 25mA, 5.5V Parameter Conditions Units
Ivin_sd Vvlin5 Iilim_pos Vilim_neg
Iss_sc Iss_sk Vss_on Vssto Vuvd Idelay Ivid
2.25
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LM2633
Electrical Characteristics
Symbol SYSTEM Vuvlo_thr Under-voltage Lockout (UVLO) Threshold UVLO Hysteresis Channel VOUT Under-voltage Shutdown Latch Threshold (Measured FB1) Channels VOUT Undervoltage Shutdown Latch Threshold (Measured FB3) VOUT Overvoltage Shutdown Latch Threshold Channel (Measured FB1) VOUT Overvoltage Shutdown Latch Threshold Channel (Measured FB2) VOUT Regulation Comparator Enable Threshold Channels Hysteresis Regulation Comparator Regulator Window Detector Thresholds (PGOOD from High Low) Regulator Window Detector Thresholds (PGOOD from High) CBOOT Leakage Current HDRV1 Source Current HDRV1 Sink Current LDRV1 Source Current LDRV1 Sink Current HDRV1 High-Side On-Resistance LDRV1 High-Side On-Resistance LDRV1 Low-Side On-Resistance Parameter
(Continued) +15V unless otherwise indicated under Conditions column. Typicals limits appearing plain type apply +25°C. Limits appearing boldface type apply over +125°C. Conditions Rising Edge VID4:0 01100 %VOUT Units
Vuvlo_hys Vuvp1
Vuvp2,
VID4:0 01100 %VOUT
Vovp1
%VOUT
Vovp2
%VOUT
Vlreg_thr
91.5
%VOUT
Vlreg_hys Vpwrbad
(Note
%VOUT
%VOUT
Vpwrgd
%VOUT
Gate Drive (For Channel Switching Regulator Controller) Iboot1 VCBOOT1 VHDRV1 VSW1 =0V, VCBOOT1 VHDRV1 VLDRV1 VLDRV1 1.84
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LM2633
Electrical Characteristics
Symbol Iboot2 Parameter CBOOT Leakage Current HDRV2 Source Current HDRV2 Sink Current LDRV2 Source Current LDRV2 Sink Current HDRV2 On-Resistance LDRV2 On-Resistance Oscillator Fosc Toff_min Ton_min Ifb1 Ifb2 Ifb3 Icomp1, Icomp2 Vcomp_max Vdac Oscillator Frequency Minimum Off-Time Minimum On-Time Feedback Input Bias Current, Channel Feedback Input Bias Current, Channel Feedback Input Bias Current, Channel COMP Output Sink Current COMP Maximum Voltage Transconductance Channel Output Voltage Accuracy
(Continued) +15V unless otherwise indicated under Conditions column. Typicals limits appearing plain type apply +25°C. Limits appearing boldface type apply over +125°C. Conditions VCBOOT2 VHDRV2 VSW2 =0V, VCBOOT2 VHDRV2 VLDRV2 VLDRV2 Units
Gate Drive (For Channel Switching Regulator Controller)
Error Amplifier VFB1 2.4V VFB2 1.36V VFB3 1.36V VFB1 150% measured 1.4V DAC, VFB2 150% measured bandgap, VCOMP1 VCOMP2
1.96
µmho
Output VFB2 VCOMP1 codes from 1.3V 1.6V VCOMP1 codes from 0.925V 1.25V from 1.65V 2.00V Vfb2 Channel Output Voltage Accuracy Channel Output Voltage Accuracy Sink Current Minimum Source Current Maximum Voltage COMP2 from 0.5V 1.8V -1.5 -1.7
1.217
1.238
1.259
Linear Regulator Controller Vfb3 Vg3_sk Ig3_sc Vg3_max 1.215 1.24 1.265
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LM2633
Electrical Characteristics
Symbol Parameter Minimum High Level Input Voltage (FPWM, VID0-VID4) Maximum Level Input Voltage (FPWM, ON/SS1, ON/SS2, VID0-VID4) PGOOD Output High Current PGOOD Output Voltage
(Continued) +15V unless otherwise indicated under Conditions column. Typicals limits appearing plain type apply +25°C. Limits appearing boldface type apply over +125°C. Conditions Units
Logic Inputs Outputs
Ioh_pg Vol_pg
PGOOD 5.7V (Note PGOOD Sinking
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LM2633
Electrical Characteristics
+15V unless otherwise indicated under Conditions column. Typicals limits appearing plain type apply +25°C. Limits appearing boldface type apply over -40°C +125°C. Symbol SYSTEM Vout1_load Vout2_load Ivin Channel Load Regulation (Note Channel Load Regulation (Note Line Regulation (for switching regulators) Input Supply Current with Switching Channels Input Supply Current with Shut Down VLIN5 Output Voltage ILIM1 ILIM2 Pins Sink Current Negative Current Limit (SWx PGNDx voltage) Soft Start Charge Current Soft Start Sink Current Soft Start Threshold Soft Start Timeout Threshold UV_DELAY Threshold UV_DELAY Source Current VID4:0 Internal Pull Current Under-voltage Lockout (UVLO) Threshold UVLO Hysteresis Channel VOUT Under-voltage Shutdown Latch Threshold (Measured FB1) Channels VOUT Undervoltage Shutdown Latch Threshold (Measured FB3) VOUT Overvoltage Shutdown Latch Threshold Channel (Measured FB1) VID4:0 01100 %VOUT Rising Edge (Note VLIN5 (Note UVLO thermal shutdown VCOMP1 moves from 0.5V 1.5V, VID4:0=01101 VCOMP2 moves from 0.5V 1.5V 5.0V 30V, VID4:0=01101 0.9V, VLIN5 Current (Note VON/SS1 VON/SS2 (Note IVLIN5 25mA, 5.5V Parameter Conditions Units
Ivin_sd Vvlin5 Iilim_pos Vilim_neg
Iss_sc Iss_sk Vss_on Vssto Vuvd Idelay Ivid Vuvlo_thr
2.25
Vuvlo_hys Vuvp1
Vuvp2,
VID4:0 01100 %VOUT
Vovp1
%VOUT
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LM2633
Electrical Characteristics
Symbol SYSTEM Vovp2 VOUT Overvoltage Shutdown Latch Threshold Channel (Measured FB2) VOUT Regulation Comparator Enable Threshold Channels Hysteresis Regulation Comparator Regulator Window Detector Thresholds (PGOOD from High Low) Regulator Window Detector Thresholds (PGOOD from High) CBOOT Leakage Current HDRV1 Source Current HDRV1 Sink Current LDRV1 Source Current LDRV1 Sink Current HDRV1 High-Side On-Resistance LDRV1 High-Side On-Resistance LDRV1 Low-Side On-Resistance Parameter
(Continued) +15V unless otherwise indicated under Conditions column. Typicals limits appearing plain type apply +25°C. Limits appearing boldface type apply over -40°C +125°C. Conditions Units
%VOUT
Vlreg_thr
91.5
%VOUT
Vlreg_hys Vpwrbad
(Note
%VOUT
%VOUT
Vpwrgd
%VOUT
Gate Drive (For Channel Switching Regulator Controller) Iboot1 VCBOOT1 VHDRV1 VSW1 =0V, VCBOOT1 VHDRV1 VLDRV1 VLDRV1 1.84
Gate Drive (For Channel Switching Regulator Controller) Iboot2 CBOOT Leakage Current HDRV2 Source Current HDRV2 Sink Current LDRV2 Source Current LDRV2 Sink Current HDRV2 On-Resistance LDRV2 On-Resistance Oscillator Fosc Toff_min Ton_min Ifb1 Oscillator Frequency Minimum Off-Time Minimum On-Time Feedback Input Bias Current, Channel VFB1 2.4V VCBOOT2 VHDRV2 VSW2 =0V, VCBOOT2 VHDRV2 VLDRV2 VLDRV2
Error Amplifier
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LM2633
Electrical Characteristics
Symbol Error Amplifier Ifb2 Ifb3 Icomp1, Icomp2 Vcomp_max Vdac Feedback Input Bias Current, Channel Feedback Input Bias Current, Channel COMP Output Sink Current COMP Maximum Voltage Transconductance Channel Output Voltage Accuracy Parameter
(Continued) +15V unless otherwise indicated under Conditions column. Typicals limits appearing plain type apply +25°C. Limits appearing boldface type apply over -40°C +125°C. Conditions VFB2 1.36V VFB3 1.36V VFB1 150% measured 1.4V DAC, VFB2 150% measured bandgap, VCOMP1 VCOMP2 Units
1.96
µmho
Output VFB2 VCOMP1 codes from 1.3V 1.6V VCOMP1 codes from 0.925V 1.25V from 1.65V 2.00V Vfb2 Channel Output Voltage Accuracy Channel Output Voltage Accuracy Sink Current Minimum Source Current Maximum Voltage Minimum High Level Input Voltage (FPWM, VID0-VID4) Maximum Level Input Voltage (FPWM, ON/SS1, ON/SS2, VID0-VID4) PGOOD Output High Current PGOOD Output Voltage PGOOD 5.7V (Note PGOOD Sinking COMP2 from 0.5V 1.8V -2.0 -2.2
1.212
1.238
1.264
Linear Regulator Controller Vfb3 Vg3_sk Ig3_sc Vg3_max 1.209 1.24 1.271
Logic Inputs Outputs
Ioh_pg Vol_pg
Note Absolute maximum ratings indicate limits beyond which damage device occur. Operating Ratings conditions under which operation device guaranteed. guaranteed performance limits associated test conditions, Electrical Characteristics table. Note Maximum allowable power dissipation calculated using PDMAX (TJMAX TA)/JA, where TJMAX maximum junction temperature, ambient temperature junction-to-ambient thermal resistance specified package. 1.56W rating results from using 150°C, 25°C, 80°C/W TJMAX, respectively. 90°C/W represents worst-case condition heat sinking 48-pin TSSOP. Heat sinking allows safe dissipation more power. Absolute Maximum power dissipation should derated 12.5mW above 25°C ambient. LM2633 actively limits junction temperature about 150°C. Note detailed information soldering plastic small-outline packages, refer Packaging Databook available from National Semiconductor Corporation. Note Except ILIM1 ILIM2 pins, which 1.5kV. testing purposes, applied using human-body model, 100pF capacitor discharged through 1.5k resistor. Note typical center characterization data taken with 25°C. Typical data guaranteed. Note limits guaranteed. electrical characteristics having room-temperature limits tested during production with 25°C. cold limits guaranteed correlating electrical characteristics process temperature variations applying statistical process control. Note This test simulates heavy load condition changing COMP voltage. Note This parameter indicates much current LM2633 drawing from input supply when functioning driving external MOSFETs bipoloar transistor.
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LM2633
Electrical Characteristics
(Continued)
Note This parameter indicates much current LM2633 drawing from input supply when completely shut off. Note When ON/SS1,2 pins charged above this voltage, under voltage protection feature enabled. Note Above this voltage, under-voltage protection enabled. Note This same over-voltage protection threshold. Note This amount current PGOOD sinks when PGOOD high forced voltage indicated
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LM2633
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20000804
Typical Application
LM2633
Typical Application
CEPH149-1R6MC CDRH127-100MC IRF7805 IRF7805 IRF7807 IRF7807 MMBT2222ALT1 CRCW0805 100J CRCW0805 104J CRCW0805 1002F CRCW0805 4752F CRCW0805 2612F CRCW0805 2872F CRCW0805 243J CRCW0805 512J CRCW0805 683J CRCW0805 562J CRCW0805 1002F CRCW0805 1002F CRCW0805 100J CRCW0805 104J LM2633M Number 25SP56M T510E108M004AS T510E108M004AS VJ1206S105MXJAC VJ1206S105MXJAC VJ0805Y104MXAAB VJ0805Y153MXJAB VJ0805Y103MXAAB VJ0805Y103MXAAB VJ0805Y222MXJAB VJ0805Y681MXJAB VJ0805Y472MXJAB VJ0805Y472MXJAB VJ0805Y821MXJAB VJ0805A221MXAAB VJ0805Y474MXJAB VJ1206S105MXJAC VJ0805Y104MXJAC VJ0805Y104MXJAC BAT54 BAT54
(Continued) TABLE Bill Materials Typical Application Circuit Type Capacitor, OSCON Capacitor, Tantalum Capacitor, Tantalum Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Capacitor, Ceramic Diode, Schottky Diode, Schottky Diode, Schottky Diode, Schottky Inductor, Power Inductor, Power MOSFET, N-CHAN MOSFET, N-CHAN MOSFET, N-CHAN MOSFET, N-CHAN BJT, Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor 14.6 14.6 SO-8 SO-8 SO-8 SO-8 SOT-23 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 TSSOP-48
Size Radial, 10.5 10.5 1206 1206 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 0805 1206 0805 0805 SOT-23 SOT-23
Parameters 25V, 3.2A 16V, 16V, 50V, 16V, 0.015 50V, 0.01 50V, 0.01 16V, 2200 16V, 16V, 4700 16V, 4700 16V, 50V, 16V, 0.47 16V, 16V, 16V, 30V, 30V,
Vendor Sanyo Kemet Kemet Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay (optional) (optional) Sumida Sumida Motorola Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay National
15.5A, 5.4A, 21.6 30V, 4.5V 30V, 4.5V 30V, 4.5V 30V, 4.5V 40V, 10.0 47.5 26.1 28.7, 10.0 10.0 3-in-1 control
(For performance, Typical Performance Curves)
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LM2633
Typical Performance Characteristics
Efficiency Load Current (Ch1, Typical Application) Efficiency Load Current (Ch2, Typical Application, FPWM
200008A1
20000898
Efficiency Load Current (Ch2, Typical Application, FPWM
Switching Frequency Load Current
20000899
20000890
Frequency Temperature
Error Amplifier Transconductance Temperature
200008A3
200008A4
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LM2633
Typical Performance Characteristics
VLIN5 Voltage Temperature
(Continued) Reference Voltage Temperature
20000894 200008B5
Current Sourcing Capability Voltage
Voltage Temperature
200008A6
20000897
Bias Current ILMx Temperature
Force-PWM Operation (Typical Application, Load
200008A2 200008A5
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LM2633
Typical Performance Characteristics
Skip-Mode Operation (Typical Application, Load
(Continued)
Soft Start with Constant Load Current
200008B3
20000892
Soft Start Under Load Typical Application)
Load Transient Response Typical Application, VOUT1 1.6V)
200008B4
200008A9
Current Limit
Control-Output Bode Plot (Ch1, Typical Application, VIN= Load)
20000891 20000893
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LM2633
Typical Performance Characteristics
Loop Bode Plot (Ch1, Typical Application, VOUT1 1.6V, Load, Compensation: 390pF, 100k, 150pF, 8.2k)
(Continued)
Control-Output Bode Plot (Ch2, Typical Application, Load)
200008B1
20000896
Loop Bode Plot (Ch2, Typical Application, Load, Compensation: 30k, 560pF, 5.1k)
200008B2
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LM2633
Operation Descriptions
General LM2633 combination three voltage regulator controllers. Among them, switching regulator controllers linear regulator controller. switching controllers, Channel Channel operate 180° phase. They independently enabled disabled. linear controller, Channel disabled only when both switching channels disabled. Channel output voltage internal DAC, which accepts 5-bit code from pins through Channels output voltages adjusted with voltage divider. Both switching channels synchronous employ peak current mode control scheme. Protection features include over-voltage protection (Ch1 under-voltage protection (all channels), positive negative peak current limit (Ch1 function delayed arbitrary amount time. Input voltage switching regulators range from 4.5V 30V. linear controller generate maximum 3.8V gate/base drive voltage. With external transistor, output voltage 3.0V. power good function always monitors three output voltages. Soft Start ON/SSx connected ground instead capacitor, corresponding channel turned will start Assume ON/SSx connected capacitor rest circuit correctly. When input voltage rises above 4.2V threshold, internal circuitry powered ON/SSx should already held 1.1V, current starts charge capacitor connected between ON/SSx ground. When ON/SSx voltage exceeds 1.2V, corresponding channel turned MIN_ON_TIME comparator generates soft start pulses. ON/SSx voltage ramps duty cycle grows, causing output voltage ramp During this time, error amplifier output voltage clamped 0.8V, duty cycle generated comparator ignored. When corresponding output voltage exceeds target voltage, mode channel transitions from soft start operating. result, high clamp output error amplifier switched Beyond this point, once pulses generated comparator wider than that generated MIN_ON_TIME comparator, comparator takes over starts regulate output voltage. That peak current mode control takes place. speed which duty cycle grows depends capacitance soft start capacitor. higher capacitance, slower speed. However, that speed independent fast input voltage rises. That because ramp signal used generate soft start duty cycle slope proportional input voltage, making product duty cycle input voltage value that independent input voltage. This feature makes soft start process more predictable reliable because whether input power supply goes through soft start process applied abruptly does affect LM2633 soft start. During soft start, under-voltage protection disabled. over-voltage protection current limit place.
When ON/SSx voltage exceeds 3.5V, soft start time signal (sstox) will issued. This signal enables under-voltage protection. Under-Voltage Protection section. Shutdown Mode both ON/SSx pins pulled low, will shut down mode. Both gate-drives switching channels turned while both bottom gate-drives remain linear channel also disabled. same thing happens gate drives when input voltage brought below UVLO threshold. Turning Switching Channel switching channel turned pulling ON/SSx below about 1.1V. Upon detecting level ON/SSx pin, corresponding gate-drive will turned bottom gate-drive will turned high current application, necessary take special measures make sure that output voltage does negative during shutdown. those measures Schottky diode parallel with output capacitors. Another measure fine tune power stage parameters such inductance capacitance values. Fault State Whenever input voltage becomes (less than about 3.9V), enters thermal shut down mode, 'fault' signal will generated internally. This signal will discharge capacitor connected between ON/SSx ground with current until reaches 1.1V. switching channels will turned upon seeing this signal. fault state, disabled shut down latch released. Force-PWM Mode This mode applies both switching channels simultaneously. force-PWM mode activated pulling FPWM logic low. this mode, bottom gate signals always complementary each other. 0-CROSSING NEGATIVE CURRENT LIMIT comparator will detect negative current limit. force-PWM mode, regulator always operates Continuous Conduction Mode (CCM) steady-state duty cycle (approximately VOUT VIN) almost independent load. force-PWM mode good applications where fixed switching frequency required. also offers fastest load transient response. force-PWM mode, turned minimum 220ns each cycle. However, when required duty cycle less than minimum value, skip comparator will activated pulses will skipped maintain regulation. Skip Comparator Whenever COMPx voltage goes below 0.5V threshold, cycles will 'skipped' until that voltage again exceeds threshold. Pulse-Skip Mode This mode activated pulling FPWM TTL-compatible logic high applies both switching channels simultaneously. this mode, 0-CROSSING NEGATIVE CURRENT LIMIT comparator detects bottom
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LM2633
Operation Descriptions
(Continued)
current. Once bottom current flows from drain source, bottom will turned off. This prevents negative inductor current. force-PWM operation, inductor current allowed negative, regulator always Continuous Conduction Mode (CCM), matter what load CCM, steady-state duty cycle almost independent load, roughly VOUT divided VIN. pulse-skip mode, regulator enters Discontinuous Conduction Mode (DCM) under light load. Once regulator enters DCM, steady-state duty cycle droops load current decreases. regulator operates mode until duty cycle falls below duty cycle, when MIN_ON_TIME comparator takes over. forces duty cycle which causes output voltage continuously rise COMPx voltage (error amplifier output voltage) continuously droop. When COMPx voltage dips below 0.5V, CYCLE_SKIP comparator toggles, causing present switching cycle 'skipped', i.e., both FETs remain during whole cycle. long COMPx voltage below 0.5V, switching FETs will happen. result, output voltage will droop, COMPx voltage will rise. When COMPx goes above 0.5V, CYCLE_SKIP comparator flips allows duty cycle pulse happen. load current small that this single pulse enough bring output voltage such level that COMPx drops below 0.5V again, pulse skipping will happen again. Otherwise take number consecutive pulses bring COMPx voltage down 0.5V again. load current increases, takes more more consecutive pulses discharge COMPx voltage 0.5V. When load current high that duty cycle exceeds duty cycle, then pulse-skipping disappears. pulse-skip mode, frequency switching pulses decreases load current decreases. LM2633 needs sense output voltages directly pulse-skip mode operation. Channel this realized through pin. Channel realized connecting SENSE2 output. LM2633 pulse-skip mode helps light load efficiency reasons. First, does turn bottom FET, this eliminates circulating energy reduces gate drive power loss. Second, only turned when necessary, rather than every cycle, which also reduces gate drive power loss. Current Sensing Current Limiting Sensing inductor current feedback control accomplished through sensing drain-source voltage when turned There leading edge blanking circuitry that forces least 160ns. Beyond this minimum time, output comparator used turn FET. blanking circuitry being used blank noise associated with turning FET. Current limit implemented using same information. Figure
20000805
FIGURE Current Limit Method There current sink ILIMx pin. When external resistor connected between ILIMx drain, voltage established between nodes. When turned voltage across proportional inductor current. inductor current high, voltage will lower than ILIMx voltage, causing comparator toggle thus will turned immediately. comparator disabled when turned during leading edge blanking time. Negative Current Limit negative current limit place ensure that inductor will saturate during negative current flow cause excessive current flow through bottom FET. negative current limit realized through sensing bottom Vds. internal reference voltage used compare with bottom when Upon seeing high Vds, bottom will turned off. negative current limit activated force mode, case Channel also whenever there dynamic change. Active Frequency Control input output voltage differential increases, time regulated feed-back control circuitry approach minimum value, i.e. blanking time. That will cause unstable operations such pulse skipping uneven duty cycles. avoid such issue, LM2633 designed such that when input voltage rises above about 17V, frequency starts droop. frequency droops fairly linearly with input voltage. typical curves. theoretical equation frequency 17V/VIN) kHz. main impact this shift frequency inductor ripple current output ripple voltage. Regulator design should take this into account. Shutdown Latch State This state typically caused output under voltage over voltage event. this state, both switching channels have their FETs turned off, their bottom FETs turned linear channel affected. There methods release system from latch state. create fault state (see corresponding section) either bringing down input voltage below 3.9V UVLO threshold then bringing back above 4.2V, somehow causing system enter thermal shut down. Another method pull both ON/SSx pins below 0.8V then release them. After latch released, switching channels will through normal soft start process. linear channel
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LM2633
Operation Descriptions
(Continued)
Power good upper limit same that function. cases above, corresponding output voltage(s) recovers, PGOOD will asserted again. there built-in hysteresis. Vpwrgd Electrical Characteristics Table. above information also available Power Good Truth Table. When internal power good MOSFET turned PGOOD will pulled ground. When turned off, PGOOD floats (open-drain). resistance power good MOSFET about 15k. Dynamic Change During normal operation, Channel sees change pattern, signal will issued. Upon seeing signal, power good signal will deasserted, Channel will disabled temporarily, Channel goes through special step quickly ramp output voltage value. output voltage higher than voltage, Channel will rely control loop change output voltage. value lower than one, going remain while bottom going remain This will cause output capacitor discharge through inductor. 0-CROSSING NEGATIVE CURRENT LIMIT comparator will detect negative over current, even LM2633 pulse-skip mode. When negative current limit reached, bottom will turned off, forcing inductor current flow through body diode input supply. When next clock cycle comes, bottom will turned again, will turned until negative current limit reached again. During this process, output voltage goes below voltage, signal will deasserted. this time, power good function will released, will enabled bottom will turned off. normal control loop takes over after output voltage droops below voltage. Internal Supply internal supply generated from voltage through internal linear regulator. This supply mainly internal circuitry use, also used externally (through VLIN5 pin) convenience. typical this supplying bootstrap circuitry drivers supplying voltage needed bottom drivers (through VDDx pins). since this generated linear regulator, hurt light load efficiency, especially when voltage high. there separate available that generated switching power supply, good idea that power bootstrap circuitry VDDx pins better efficiency less thermal stress LM2633. shut down mode, VLIN5 will 5.5V. recommended this voltage purposes other than bootstrap circuitry VDDx pins. When power stage input voltage guaranteed within 4.5V 5.5V, VLIN5 tied directly. this mode, currents directly coming from power stage input rail power loss internal linear regulation longer issue.
output voltage will affected unless UVLO method used release latch. linear channel causes event, then enters Shut Down Latch State. later fault linear channel removed, linear channel will recover, will still latch state. Over-voltage Protection This protection feature implemented switching channels linear channel. Refer Table long there least switching channel enabled, LM2633 fault state, over voltage event either switching channels' output will cause system enter Shut Down Latch State. However, over voltage event happens only Channel after dynamic change signal issued before change completes, system will enter Shut Down Latch State. Dynamic Change section. Under-voltage Protection feature implemented three channels. UV_DELAY pulled ground, then undervoltage protection feature disabled. Otherwise, capacitor connected between UV_DELAY ground, enabled. Assume enabled system fault state. switching channel enabled, soft start time signal (sstox, soft start section) asserted, then under voltage event output that channel will cause system enter Shut Down Latch State. However, under voltage event happens only Channel after dynamic change signal issued before change completes, system will enter Shut Down Latch State. Dynamic Change section. linear channel, there least switching channel least soft start time signal been issued, system Fault State, then under voltage event linear regulator output will cause system enter Shut Down Latch State. When LM2633 reacts under voltage event, current will charging capacitor connected UV_DELAY when voltage exceeds 2.1V, system immediately enters Shut Down Latch State. details, block diagram Shut Down Latch Truth Table. Power Good Function power good function general indication health regulators. There internal MOSFET tied from PGOOD ground. Power good signal asserted turning that MOSFET. internal power good MOSFET will turned unless least following occurs: There output over voltage event least switching channels. output voltage three channels below power good lower limit, regardless ON/SSx voltage level. Whenever Channel going through dynamic change. System shut down mode. System fault state. System shut down latch state.
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Design Procedures
Core Power Supply Nomenclature
LM2633
Design Procedures
(Continued)
Equivalent Series Resistance. Loading transient load transient when load current goes from minimum load full load. Unloading transient load transient when load current goes from full load minimum load. regulator output capacitance. duty cycle. switching frequency. Inlim negative current limit level. Iilim ILIMx current. Iirrm maximum input current ripple value. Iload load current. Irip output inductor peak-to-peak ripple current.
design procedures that follow generally appropriate both core power supplies, although emphasis placed former. When there difference between two, will pointed out.
Output Capacitor Selection
Type output capacitors Different type capacitors often have different combinations capacitance ESR. High-capacitance multi-layer ceramic capacitors (MLCs) have very ESR, typically 12m, also relatively capacitance 100µF. Tantalum capacitors have fairly ESR, such 18m, pretty high capacitance 1mF. Aluminum capacitors have very high capacitance fairly ESR. OSCON capacitors achieve values that even lower than those MLCs' while having higher capacitance. Tutorial load transient response Skip next subsection when quick design desired. control loop LM2633 made fast enough that when worst-case load transient happens, duty cycle will saturate (meaning jumps either Dmax). control loop fast enough, worst situation load transient will that transient happens when following three also happening. One, present pulse just finished. Two, input voltage highest. Three, load current goes from maximum down minimum (referred unloading transient). Figure shows inductor current changes during worst-case load transient. reasons follows. mobile application, input/output voltage differential, which applied across inductor during loading transient, higher than output voltage, which applied across inductor during unloading transient.
core voltage regulation window. LM2633 initial tolerance.
Vc_s maximum allowed core voltage excursion during load transient, derived from specifications. Ic_s maximum load current change during load transient, specified manufacturer. inductance output inductor. total combined output capacitors. Re_s maximum allowed total combined output capacitors, derived from load transient specifications. Rilim current limit adjustment resistance. Current Sensing Current Limiting. tmax maximum allowed dynamic transition time. tpeak time core voltage reach peak value during unloading transient. input voltage switching regulators. nominal output voltage. Vold nominal core voltage before dynamic change. Vnew nominal core voltage after dynamic change. Vrip peak-to-peak output ripple voltage.
General
Designing power supply involves many tradeoffs. good design usually design that makes good tradeoffs. Today's synchronous buck regulators typically 200kHz 300kHz switching frequency. Beyond this range, switching loss becomes excessive, below this range, inductor size becomes unnecessarily large. LM2633 fixed operating frequency 250kHz when voltage below about 17V, decreased frequency when voltage exceeds 17V. Active Frequency Control section. mobile application, both core exhibit large fast load current swings. load current slew rate during such transient usually well beyond response speed regulator. meet regulation specification, special considerations should given component selection. example, total combined output capacitors must lower than certain value. Also because tight regulation specification, only small budget assigned ripple voltage, typically less than 20mV. found that starting from given output voltage ripple will often result fewer design iterations.
20000806
FIGURE Worst-case Load Transient That means inductor current changes slower during unloading transient than during loading transient. slower inductor current changes during load transient, higher output capacitance needed. That unloading transient worst case. load transient happens when present pulse just finished, inductor current will highest, which means highest initial charging current output capacitors. Finally, higher input voltage, higher inductor ripple current higher initial charging current output capacitors.
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LM2633
Output Capacitor Selection
(Continued)
total change output voltage during such load transient From Figure told that will reach peak value some point time then going decrease. larger output capacitance earlier peak will happen. capacitance large enough, peak will occur beginning transient, i.e., will decrease monotonically after transient happens. find peak position, derivative zero, result
20000807
FIGURE Load Transient Spec. Violation Because response speed regulator slow compared typical load transient, regulator rely heavily output capacitors handle load transient. initial overshoot undershoot caused output capacitors. output voltage recovers after that initial excursion depends fast output inductor current ramps large output capacitance Figure total combined output capacitors enough, initial output voltage excursion will violate specification, Vc1. enough, there enough output capacitance, output voltage will have much extra excursion travel outside specification window, before returns nominal value, Vc2.
target find capacitance value that will yield, tpeak, that equals Vc_s. plugging tpeak expression into expression equating latter Vc_s, following formula obtained:
Notice already assumed total greater than Re_s otherwise term under square root will negative value.
20000813
FIGURE Re_s Re_s There scenarios when calculating Cmin. Figure that equal Re_s there absolutely room which means tpeak other that smaller than Re_s there some room which means tpeak greater than zero. However, necessary differentiate between scenarios when figuring Cmin above formula. Allowed transient voltage excursion allowed output voltage excursion during load transient
20000808
FIGURE Delta Output Voltage Components During load transient, delta output voltage changing components. delta voltage across (Vr), other delta voltage caused gained charge (Vq). Both delta voltages change with time. equation
equation
Example: 1.35V, 7.5%, 1.4%, Vrip 20mV
Since ripple voltage included calculation Vc_s, inductor ripple current should included worst-case load current excursion. That worst-case load current excursion should simply Ic_s.
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LM2633
Output Capacitor Selection
(Continued) Maximum calculation matter much capacitance there total combined less than certain value, load transient requirement will met. maximum allowed total combined Generally speaking, Cmax decreases with decreasing tmax, Inlim Iload, with increasing voltage step. Power loss output capacitors typical buck regulator, ripple current inductor (and thus output capacitors) small that causes very little power loss. equation calculating that loss
Example: Vc_s 72mV, Ic_s 10A. Then Re_s 7.2m. Maximum criterion used when capacitance high enough, otherwise more capacitors than number determined this criterion should used. Minimum capacitance calculation core power supply, minimum output capacitance typically dictated load transient requirement. there enough capacitance, output voltage excursion will exceed maximum allowed value even maximum requirement met. worst-case load transient unloading transient that happens when input voltage highest when just been turned off. corresponding minimum capacitance calculated follows:
(10) Example: Irip 4.3A,
(11)
Output Inductor Selection
size output inductor determined from assigned output ripple voltage budget impedance output capacitors switching frequency. equation determine minimum inductance value follows:
Notice already assumed total greater than Re_s, otherwise term under square root will negative value. Example: 1.35V, Vc_s 72mV, Ic_s 10A,
(12) where min(Vin_max, 17V) means smaller Vin_max 17V. reason this term simply Vin_max that switching frequency droops with increasing when higher than 17V. Active Frequency Control. above equation, used place impedance output capacitors. This because most cases, impedance output capacitors switching frequency very close case ceramic capacitors, replace with true impedance. Example Vin_max 21V, 1.6V, Vrip 26mV, 250kHz.
Generally speaking, Cmin decreases with decreasing Ic_s, with increasing Vc_s. Maximum capacitance calculation This subsection applies Channel core power supply only. there need change core voltage dynamically (see Dynamic Change), there will maximum output capacitance restriction. output capacitance large, will take much time core voltage ramp value, violating maximum transition time specification. worst-case dynamic change that takes largest step down load. maximum capacitance determined LM2633 implements change calculated follows:
Example Vin_max 18V, 1.35V, Vrip 20mV, 250kHz.
Example: tmax 100µs, Inlim 20A, Vold 1.6V, Vnew 1.35V, Iload
actual selection process usually involves several iterations above steps, from ripple voltage selection, capacitor selection, inductance calculations. Both highest lowest core voltages their load transient requirements should considered. inductance value larger than Lmin selected, make sure Cmin requirement violated. Priority should given parameters that flexible more costly. example, there very types capacitors choose from,
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LM2633
Output Inductor Selection
(Continued)
good idea adjust inductance value that requirement capacitors reduced capacitors. Inductor ripple current often criterion selecting output inductor. However, core application, usually lower priority. That partly because stringent output ripple voltage requirement automatically limits inductor ripple current level. nevertheless good idea double check ripple current. equation
current. case FETs parallel, multiply calculated resistance obtain resistance each FET. case three FETs, that number Since efficiency very important mobile having lowest resistance usually more important than fully utilizing thermal capacity package. probably better find lowest-Rds first, then determine many needed. Example: Tj_max 100°C, Ta_max 60°C, 60°C/W, Vin_max 21V, 1.6V, Iload_max 10A.
(13) where min(Vin_max, 17V) means smaller Vin_max 17V. What more important ripple content, which defined Irip_max Iload_max. Generally speaking, ripple content less than high ripple content will cause much loss inductor. Example: Vin_max 21V, 1.6V, 250kHz, 1.7µH.
lowest-on-resistance Rds_max 10m, then used parallel. temperature rise each will Tj_max because each dissipating only half total power. Alternatively, FETs used parallel, with each reaching Tj_max. This lower cost, will double bottom switch power loss. Selection types power losses switching loss conduction loss. switching loss mainly consists cross-over loss bottom diode reverse recovery loss. rather difficult estimate switching loss. general starting point allot thermal capacity switching loss. best find still test bench. equation calculating resistance thus:
maximum load current 14A, then ripple content 4.3A 30%. When choosing inductor, saturation current should higher than maximum peak inductor current. current rating should higher than maximum load current.
MOSFET Selection
Bottom Selection During normal operations, bottom turned almost zero voltage. only conduction loss present bottom FET. bottom power loss peaks maximum input voltage load current. most important parameter when choosing bottom resistance. less resistance, less power loss. equation maximum allowed resistance room temperature given package,
(15) where Tj_max maximum allowed junction temperature FET, Ta_max maximum ambient temperature, junction-to-ambient thermal resistance FET, temperature coefficient resistance which typically 4000ppm/°C. Example: Tj_max 100°C, Ta_max 60°, 60°C/W, Vin_min 14V, 1.6V, Iload_max 10A.
(14) where Tj_max maximum allowed junction temperature FET, Ta_max maximum ambient temperature, junction-to-ambient thermal resistance FET, temperature coefficient resistance which typically 4000ppm/°C. calculated resistance smaller than lowest value available, multiple FETs used parallel. design criterion highest-Rds FET, then Rds_max each increased reduced
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Since switching loss usually increases with bigger FETs, choosing with much smaller resistance sometimes yield noticeable lower temperature rise better efficiency. recommended that peak value does exceed when conducts, otherwise COMPx voltage reach high clamp value (2V) cause loss regulation.
LM2633
Current Limit Setting
What actually monitored limited peak drainsource voltage when conducting. equation current limit resistor follows:
tween channels' input current pulses. equation calculating maximum total input ripple current therefore:
(17) where maximum load current Channel maximum load current Channel duty cycle Channel duty cycle Channel (16) where Iload_lim desired load current limit level Iilim_min minimum sink current ILIM1 pin. This calculated Rilim value guarantees that minimum current limit will less than Iload_lim. Example: Iload_lim 16A, Irip_max 4.3A, Rds_max 18m, Tj_max 100°C, Iilim_min 8µA. Example: Iload_max_1 6.8A, Iload_max_2 0.09, 0.1.
recommended that tolerant resistor used resistance should lower than calculated value.
Input Capacitor Selection
typical buck regulator power loss input capacitors much larger than that output capacitors. That because current flowing through input capacitors square-wave shape peak-to-peak magnitude equal load current. result large ripple current input capacitors. fact that switching channels LM2633 180° phase helps reduce value ripple current seen input capacitors. That will help extend input capacitor life span result more efficient system. mobile application, both core voltages rather compared input voltage. corresponding duty cycles therefore less than 50%, which means there will over-lapping
Choose input capacitors that handle 1.97A ripple current highest ambient temperature. input capacitors should also meet voltage rating requirement. this case, SANYO OSCON capacitor 25SP33M, Taiyo Yuden ceramic capacitor TMK325BJ475, will meet both requirements. Comparison: channels operating phase, ripple value would 2.52A. equation calculating ripple current takes same form above meanings variables change. maximum load currents, smaller duty cycle two, difference between duty cycles, maximum load current channel that larger duty cycle.
Figure shows reduction input ripple current brought 2-phase operation varies with load current ratio duty cycles. From plots, seen that benefit 2-phase operation tends maximize when load currents tend equal. Another conclusion that ratio increases rapidly when channel's duty cycle catching with other channel's then becomes almost flat when former exceeds latter. absolute optimal operating point terms input ripple Iload_max_1 Iload_max_2, when input ripple current zero 2-phase operation.
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LM2633
Input Capacitor Selection
(Continued)
20000884
FIGURE Input Ripple Current Ratio: 2-phase In-phase
Control Loop Design
Samll Signal Model buck regulator small signal model shown Figure model obtained applying current-controlled switch derived Vorperian omitting portions that irrelevant buck topology.
20000838
FIGURE Small Signal Model Buck Regulators model, output conductance switch
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LM2633
Control Loop Design
(Continued)
go(CRRe
(30) (31)
(18) Where (19)
reasonable design, output filter large attenuation large complex frequencies (i.e. large values). values where 1/sC smaller than power stage reduced shown Figure
(20)
200008D5
(21) FIGURE Simplified Power Stage High Frequencies transfer function re-written (22)
(23) correction ramp slope, on-time slope current sense waveform, peak-peak value correction ramp, frequency, input voltage, transfer resistance from inductor current ramp voltage, on-resistance gain current sense amplifier. coefficient first current source
(32) Where
(33)
(24) coefficient second current source
(25) output capacitance switch
(34) terms omitted denominator because their values negligible compared other terms. Since denominator control-output transfer function third-order polynomial, coefficients positive real numbers, transfer function either real pole complex poles that complex conjugates three real poles. Thus approximately written following format:
(26) resistance switches inductor included here because value usually much smaller than load resistance. Where Control-Output Transfer Function control (COMPx pin) voltage peak-current mode scheme such that LM2633 current command. instant that voltage determines level inductor current (from average-model point view). control-output transfer function description small-signal behavior power stage obtained letting small signal component input voltage zero. expression control-output transfer function
(35)
(36)
(37) where (27) Where LCsC(R goLC(R Cs(CRRe (28) (29)
(38)
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LM2633
Control Loop Design
(Continued)
(39) value determined comparing denominators Equation (35) Equation (27). result
(40) From above expressions, seen that control-output transfer function three poles zero. three poles, real pole (fp) that located frequency, other either complex conjugates that located half switching frequency (fn), separated real poles, depending value. When value less than 0.5, high frequency poles will become real poles. From Equation (34) told that will become negative when 1/(2D'). negative value means unstable system because control-output transfer function will have right-half-plane pole. Example: 10V, Vout 1.6V, 0.4. LM2633, kHz, 0.25V,
20000863
FIGURE Example Control-Output Transfer Function Bode Plot should noted that load resistance only changes frequency gain. This causes location frequency pole change with load. Frequency Compensation Design general purpose compensate loop meet static dynamic performance requirements while maintaining stability. Loop gain what usually checked small-signal performance. Loop gain equal product control-output transfer function so-called 'plant') output-control transfer function (i.e. compensation network transfer function). Different compensation schemes result different trade-offs among static accuracy, transient response speed degree stability, etc. Generally speaking good idea have loop gain slope that -20dB/decade from very frequency well beyond cross-over frequency. cross-over frequency should exceed one-fifth switching frequency, i.e. 50kHz case LM2633. higher bandwidth, potentially faster load transient response speed. However, duty cycle saturates during load transient, then further increasing small signal bandwidth will help. context core power supply, small-signal bandwidth 20kHz 30kHz should sufficient output capacitors just MLCs. Since control-output transfer function usually very limited frequency gain (see Figure good idea place pole compensation zero frequency, that frequency gain especially gain will very large. large gain means high regulation accuracy (i.e. voltage changes little with load line variations). rest compensation scheme depends highly plant shape. typical shape such shown Figure assumed, then following done create -20dB/decade roll-off loop gain. Place first zero second pole second zero then resulting loop gain plot will -20dB/dec slope from zero frequency (half switching frequency).
0.25V 250kHz 62.5mV/µs
250kHz 125kHz
resulting gain plot shown Figure asymptotic plot. plots actual gain phase computed Equation (27) also shown.
Figure shows gain plot such two-pole two-zero (more accurately, lag-lag) compensation network, where fz1, first zero, second zero second pole frequencies. first pole located zero frequency.
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LM2633
Control Loop Design
VID4:0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VDAC 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.050 1.025 1.000 0.975 0.95 0.925 0.900 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k 12.5k
(Continued)
TABLE Values 17.1k 18.4k 17.4k 21.4k 19.3k 22.0k 22.1k 30.0k 24.5k 27.3k 26.0k 34.6k 29.3k 36.0k 36.4k 64.3k 23.2k 25.7k 24.5k 32.1k 27.5k 33.3k 33.6k 56.2k 39.6k 47.4k 43.4k 75.0k 53.7k 81.8k 83.7k R2/(R1+R2) 0.41 0.42 0.41 0.46
20000864
0.43 0.47 0.47 0.55 0.49 0.52 0.51 0.58 0.54 0.59 0.59 0.72 0.65 0.67 0.66 0.72 0.69 0.73 0.73 0.82 0.76 0.79 0.78 0.86 0.81 0.87 0.87 FIGURE Compensation Network gain compensation network calculated following. zero frequency higher than frequency pole then there should -20dB/decade section from (310 (8.8 kHz) plant gain plot, such shown Figure Find frequency where this section extension this section) crosses using following equation: fc_o (41) desired loop transfer function cross-over frequency fc_c, then gain compensation network should
20000865
FIGURE 2-Pole 2-Zero (lag-lag) Network Asymptotic Gain Plot achieve gain shape Figure Figure should take form branches parallel, shown Figure scheme, form first zero fz1, form second pole fp2, form second zero fz2.
signal path from output voltage control voltage feedback path. typically contains voltage divider, error amplifier compensation network. Those shown Figure amplifier, Channel LM2633, since R-2R ladder network used, values change with setting. information regarding their values ratios, refer Table Channel simply external voltage divider resistors.
(42) determine component values Figure following equations used:
(43) where desired gain fz1, transconductance error amplifier.
(44)
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LM2633
Control Loop Design
(Continued)
(45)
(46) Back previous example. then: fc_o 310Hz 1581Hz
20000877
FIGURE Example Loop Transfer Function shorter recovery time desired during load transient, increased that gain loop transfer function becomes higher. However, higher than desired cross-over frequency, otherwise phase margin low. Figure shows situation where placed higher frequency than which results dB/dec section before cross-over frequency. Notice phase margin lower.
corresponding Bode plots compensation network loop transfer function shown Figure Figure respectively.
200008D6
FIGURE Higher Frequency Gain Sometimes slow transient response caused current source sink capability error amplifier. Reducing value compensation capacitor helps, make sure small-signal loop stable. power stage component selection significantly different from example values. Figure shows high frequency poles current-mode-control buck regulator change with value.
20000876
FIGURE Example Compensation Transfer Function seen from Figure that crossover frequency 20kHz, phase margin about degrees. thing that should pointed this Bode plot only load. That when load current load current lower than portion gain plot from corresponding 310Hz will -40dB/dec. load current higher than then portion gain plot from 310Hz will flat. However, this usually does have much effect cross-over frequency phase margin because happens frequencies.
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LM2633
Control Loop Design
(Continued) (48) where H(s) compensation transfer function defined
(49) seen from Equation (47) that equal 1/(2D')+0.5, then open-loop audio susceptibility zero. Unfortunately, transfer function rather sensitive value around critical value thus this phenomenon little value.
20000878
FIGURE Control-Output Transfer Function Changes with Values When higher than 0.5, there will double-pole half switching frequency When lower than 0.5, double-pole damped becomes separate poles. lower value farther apart poles are. When (such 0.05 lower), high frequency poles move well into frequency region. When high (such higher), there will significant peaking half switching frequency phase will rapidly -180° near This typically results lower cross-over frequency that peaking loop gain well below line. function duty cycle deepness ramp compensation (mc). Equation (34). larger duty cycle, higher value. deeper ramp compensation, lower value. When inductor current ramp much smaller than compensation ramp, high frequency poles will move into frequency region form double-pole with existing frequency pole That makes voltage-mode control. ramp compensation becomes deeper when inductance increased, input voltage decreased, sense resistance decreased. case Channel LM2633, 3µH, 24V, 0.925 20m, value will between 0.65 0.2. Audio Susceptibility Audio susceptibility transfer function from input output. typical power supply design, desirable have much attenuation that transfer function possible that noise appearing input little effect output. open-loop audio susceptibility given model Figure
20000882
FIGURE Example Audio Susceptibility Gain open-loop closed-loop audio susceptibility previous example shown Figure told, both from model from Equation (47), that open-loop gain audio susceptibility just level shift loop gain. Closed-loop audio susceptibility starts depart from open-loop counterpart when frequency drops below cross-over frequency. Adjusting Output Voltages Switching Channels Channel output voltage normally adjusted through pins. Channel output voltage adjusted through external voltage divider, shown Figure
200008B7
FIGURE Setting Output Voltage equation find value when been selected (47) closed-loop audio susceptibility simply: (50) where Vfb2 equal internal reference voltage connected non-inverting input Channel error
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LM2633
Control Loop Design
(Continued)
amplifier, Ifb2 current drawn pin. Vfb2 Ifb2 have typical value 1.24V respectively. Example: Vout2 1.5V,
Since op-amp active device, close attention start shut down behavior. Make sure that does create problem during those times. Designing Power Supply without Load Transient Specification Many times load transient response buck regulator critical issue. that case, selection power stage components start from inductor ripple current. Choosing peak-to-peak ripple current maximum load current often good starting point. Then inductance value determined ripple, switching frequency input output voltages. rearranging Equation (13), inductance value calculated follows:
(51) calculate total system tolerance, following equation:
(52) where tolerance Channel reference voltage, tolerance resistors. Example: Vout2 3.3V, feedback resistors have tolerance.
(54) Example: Vin_max 21V, 1.6V, Iload_max 10A.
(53) That means 3.3V output voltage will have 2.96% tolerance over (LM2633 die) temperature range 125°C. Channel output voltage should above pulse-skip mode. That because SENSE2 cannot take voltage higher than However, force-PWM operation chosen operating mode, then SENSE2 grounded there will limitation Channel output voltage. desired Channel voltage higher than op-amp voltage divider used expand voltage range, shown Figure
output capacitors chosen based output voltage ripple requirement. there specific requirement, then ripple level good starting point. equation determining impedance output capacitors
(55) zero frequency capacitor lower than switching frequency, such case aluminum, tantalum OSCON capacitors, then output capacitors chosen value. Otherwise, such case ceramic capacitors, output capacitors chosen capacitance. equation
(56) Basically make sure that product impedance capacitors ripple current does exceed ripple voltage requirement. Example: 1.6V, Irip
200008B6
FIGURE Make VOUT1 Higher Than recommended that VIDx pins tied ground that 2.00V. That will reduce total tolerance. equations used calculate Channel feedback resistors total tolerance still hold, except that reference voltage Vfb1 2.00V instead 1.24V. Channel operate only force-PWM mode when configured Figure
(57) ceramic capacitors preferred, then minimum capacitance
(58)
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LM2633
Control Loop Design
(Continued)
aluminum, tantalum OSCON capacitors going used, make sure combined greater than 10.6 Depending application, different priority assigned selection components. example, achieve 10.6 combined ESR, would require low-ESR tantalum capacitors, which quite expensive. inductor size allowed expand, then higher inductance value used that ripple current reduced impedance capacitor switching frequency higher. often necessary through several iterations before reasonable combination inductor capacitors achieved. Notice above procedure given without consideration load transient, whether expected unexpected. power supply designer tempted ceramic capacitor only output capacitor above example. That fine design that very static load. However, should there large fault load current (which enough trigger UVP) later that condition suddenly lifted, output severe over voltage. Although LM2633 will shut down immediately upon seeing over-voltage event, load could have been damaged already. Another concern with pure ceramic output capacitors soft start. necessary increase soft start time that there will minimum overshoot soft start. when large inductance small capacitance chosen, care should given above situations. load current goes from level another during normal operations, design with less capacitance tends have more output voltage excursion recover more slowly than with more capacitance. From time-domain viewpoint, that because less capacitance less effective energy buffer when load current temporarily different from inductor current. From frequency-domain viewpoint, that because output impedance regulator higher. power supplies that don't have stringent load transient requirement, polymer aluminum capacitors used well low-ESR tantalum capacitors. These polymer aluminum capacitors surface mount, long-life, ignition free typically have very values. example, Cornell Dubilier's ESRE ESRD polymer aluminum chip capacitors have value capacitance Panasonic also offers specialty polymer aluminum capacitors. Panasonic's series offers capacitance voltage rating VDC. Typical Application circuit, there stringent load transient requirement Channel replaced single polymer aluminum capacitor, such ESRE271M02R from Cornell Dubilier. frequency compensation should necessary. Notice that voltage rating that capacitor only VDC. Designing Around Pulse-Skip Mode FPWM pulled logic high, LM2633 operates pulse-skip mode. this mode, when load light enough, LM2633 starts skip pulses. Pulse-Skip Mode Operation Descriptions.
pulse-skip mode, apparent switching frequency lower than frequency regulator would were force-PWM mode. actual frequency depends load, lighter load lower frequency. load which pulse-skipping starts happen determined from following formula:
(59) Example: Irip
Since critical load current completely depends inductor ripple current, inductance value cannot arbitrary accurate control value critical load desired. When FPWM pulled high, regulator enters discontinuous conduction mode (DCM) when load light enough that inductor current goes zero before each switching cycle. critical load current value regulator enter
(60) Notice mode FETs still switch every clock cycle duty cycle shrinks load current decreases. When load current goes below Iload_skip, regulator enters pulse-skip mode. region very narrow one. when peak-peak ripple current happens only when load current falls 1.1A 1.5A range. Above that range, regulator continuous conduction mode (CCM), below that range, regulator runs pulse-skip mode. Designing Linear Regulator with Channel Channel LM2633 used drive external transistor provide linear regulation. Figure
200008A7
FIGURE Channel Controlling output voltage adjusted through voltage divider, equation
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LM2633
Control Loop Design
(Continued)
error amplifier Channel gain unity-gain bandwidth kHz. plots Figure
(61) where Vfb3 equal reference voltage connected non-inverting input error amplifier typical value 1.24V, Ifb3 bias current drawn typical value Example: intended output voltage 2.5V. Find appropriate value chosen 10.0
(62) voltage cannot exceed current sourcing capability decreases with increasing voltage. typical curves. suggested that maximum output voltage does exceed when pass transistor used. N-channel used, make sure fully turned before goes There factors consider when selecting First current gain second power dissipation. certain load current, lower value, more base current necessary maintain regulation. Since base current comes from through internal linear regulation, large base current significantly increases power consumption LM2633 hurts light-load efficiency, particularly when relatively high. Therefore transistor with large value preferred. maximum power consumption Ploss Iload_max (Vin2_max Vout3_min) (63) Example: input voltage linear regulator 3.3V maximum load current output voltage 2.5V. Since Channel LM2633 tolerance over temperature, voltage divider contributes another total output voltage tolerance Equation (52) calculation total tolerance when voltage divider used. Ploss (3.3V 1.05 2.5V 0.97) ambient temperature 65°C less, SOT-23 package should able handle this much power. Since Channel affects UVP, used, proper termination pins should made. good VLIN5, OUT3 together leave them floating. Figure
20000895
FIGURE VFB3-to-VG3 Transfer Function (theoretical) easy model loop frequency response linear regulator. best still measure loop gain under different load conditions bench. reference point, 2.5V that uses MMBT2222 pass transistor, ceramic output capacitor load, bandwidth about kHz, with phase margin gain margin about higher bandwidth, less output capacitance needed handle load transient. However, most applications, stability only concern.
Layout Guidelines
extremely important follow guidelines below ensure clean stable operation. four-layer PCB. Keep FETs close possible. Keep power components right side (pins through low-power components left side. Analog ground power ground should separate planes should connected single point, preferably PGNDx pins directly underneath VDDx decoupling capacitor should connected power ground plane. Input ceramic capacitors should placed very close FETs their connections drain source bottom should short possible should through power plane ground plane. HDRVx, traces should close each other possible minimize noise emission. these traces longer than centimeters, they should fairly wide, such 50mil. Keep trace short possible. Otherwise, trace 50mil wider. ILIMx trace should kept away from noisy nodes such switch node. preferable have shorter wider trace than longer narrower one.
200008A8
FIGURE When Ch.3
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LM2633
Layout Guidelines
(Continued)
VLIN5 decoupling capacitor should connected local analog ground. Compensation components should placed close within centimeters.
Channel should analog ground, power ground, avoid potential noise coupling from switching channels. example power stage layout shown Figure
20000883
FIGURE Layout Example
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LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller Notebook CPUs
Physical Dimensions
unless otherwise noted
inches (millimeters)
48-Lead TSSOP Package Order Number LM2633MTD Package Number MTD48
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LM2633 Advanced Two-Phase Synchronous Triple Regulator Controller Note

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