DataPath Systems, Inc. 01/20/2000 further information, pleas

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ADSL Analog Front DPS8000 (for ATU-C) DPS8001 (for ATU-R) Data Sheet V1.1.1
DataPath Systems, Inc.
01/20/2000
further information, please contact: Cormac Conroy 408-365-6073 cconroy@DataPathSystems.Com Phil Welsh 408-365-6058 pwelsh@DataPathSystems.Com FAX: 408-365-0530 Mailing address: 5883 Ferrari, Suite Jose, 95138
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Features
ADSL analog front with full analog signal path ATU-R ATU-C (excluding pots reject filter high-voltage line drivers/receivers). Fully monolithic: minimal external components required precision resistors, non-critical resistors, decoupling capacitors) Support both echo-cancelled frequency-division based systems; full analog echo path support hardware. Compatible with G.992.1 (G.dmt) G.992.2 (G.lite) standards Upstream channel: support both (for ADSL over ISDN) Downstream channel: support both (G.lite) 1.104 (G.dmt) 14-bit linear 4.416 MS/s Dual 14-bit linear 4.416 DAC's 4th-order lowpass filters receive transmit paths, with cutoff frequency accuracy Programmable gain stages attenuators paths ATU-R receive path noise PSD: -160 dBm/Hz above (100 system) ATU-C receive path noise PSD: -153 dBm/Hz above (100 system) Integrated wakeup detector ATU-C 12-bit support VCXO 4-wire serial port register control attenuation/gain settings, filter bandwidths, modes, power down individual functional blocks etc. power supply; 3.3V supply digital Power: 0.825 (full-rate ADSL, with full echo channel turned on)) 0.675 (full-rate ADSL, echo channel used i.e., typical system)
128-pin MQFP plastic package Operating temperature range: -40°C +85°C
more information operation this block, please contact DataPath Systems.
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Functional Block Diagram
Filter
Filter
Echo
Filter
Fine Support Blocks: Wakeup detect VCXO
Low-Noise Coarse
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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General Description
Asymmetric digital subscriber line (ADSL) technology provides viable solution meet emerging need high-bandwidth communications home while utilizing existing twistedpair copper infrastructure. simplify design reduce deployment costs, DataPath Systems developed analog front-end designed perform analog functions receive (RX) transmit (TX) paths ADSL, excluding POTS reject filtering highvoltage line drivers/receivers. chip requires external circuitry beyond pair precision resistors bypass/coupling capacitors. Note that full compliance with G.992.1 G.992.2 transmit masks, additional off-chip filtering path needed; systems, additional off-chip bandsplit filtering required system optimization. versions chip exist: customer remote modem central office modem
(ATU-R, part number DPS8001) (ATU-C, part number DPS8000).
chip will allow maximum data throughput greater than Mb/s downstream kb/s upstream short lines. other extreme, linearity noise performance analog signal paths enable chip successfully transmit receive data Mb/s longest lines above kfeet AWG24 wire. chip utilized systems employing either echo cancellation (EC) frequency division multiplexing (FDM), also fully compatible with emerging G.lite standard. Support simultaneous operation ADSL over ISDN also present. Thus, ADSL modem equipped with this chip will operate vast majority phone lines worldwide, enabling maximum data rate with maximum reach between central office (CO) remote site. portion chip comprises low-noise front programmable gain amplifier (PGA), anti-aliasing filter, 14-bit converter (ADC). portion consists independent signal paths, primary transmit signal support echo. feature excellent matching between echo path primary path, minimizing difficulties echo cancellation arising from mismatch between two. Each path consists 14-bit converter (DAC), transmit lowpass filter, programmable attenuation amplifier (PAA). simplify overall system design, droop compensation handled internally, removing this burden from back-end signal processing. Apart from primary signal paths, chip also contains support circuitry other functions required ADSL modem. assist timing recovery, 12-bit present drive offchip voltage controlled crystal oscillator. all-analog "wakeup" detector present minimize power consumption When ADSL line unused, back-end digital analog circuitry modem thus powered down, facilitating significant power savings. chip's digital input/output interfaces designed simple possible, emphasizing ease design-in evaluation. primary digital ADC/DAC interfaces separate 16-bit wide busses. Although chip itself utilizes supply voltage, digital interfaces fully compliant with either 3.3V CMOS signal swings. chip modes programmable single serial port interface.
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Electrical Specifications
indicates tested production guaranteed design characterization
dBFS: below full scale signal level
Notes:
Parameter
Units
Notes/Conditions
General
temperature
Chip power supplies VDD_ADIO power supply Power supply current 4.75 5.25 5.25
this supply only Echo path Echo path
Path
ATU-R input-referred noise floor ATU-C input-referred noise floor range gain accuracy step size ATU-R low-pass filter cutoff frequency ATU-C low-pass filter cutoff frequency Filter bandedge tolerance Entire channel (PGA, filter, ADC) linearity: Multitone Power Ratio (MTPR) -0.2 -156 -160 dBm/Hz (100 -150 -153 dBm/Hz (100 0.25 1.104
test pattern 248-tone multitone over 1.104 band with missing tones aggregate level dBFS. pins RX_INP, RX_INM pins RX_INP, RX_INM frequencies >300 kHz. Assumes maximum-sensitivity condition: PGA's maximum gain. frequencies kHz. Assumes maximum sensitivity condition: PGA's maximum gain.
+0.2
Full-rate mode Halfband (G.lite) mode Non-ISDN mode ISDN mode
resistance capacitance
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Parameter
Units
Notes/Conditions
Path
range gain accuracy step size ATU-C low-pass filter cutoff frequency ATU-R low-pass filter cutoff frequency Filter bandedge tolerance Entire channel (DAC, filter, PAA) linearity: Multitone Power Ratio (MTPR) Output load -0.2 1.104
test pattern 248-tone multitone over 1.104 band with missing tones aggregate level dBFS. Resistance ground coupled), pins TX_OUTP, TX_OUTM, EC_OUTP, EC_OUCapacitance ground pins TX_OUTP, TX_OUTM, EC_OUTP, EC_OU
+0.2
Full-rate mode Halfband (G.lite) mode Non-ISDN mode ISDN mode
Effective number bits Linearity Full scale input range Full scale range accuracy 13.0 14.0 ±2.5 Bits Bits
Resolution 13.5 14.0 ±2.5 Bits Bits
Effective number bits Linearity Full scale output range Full scale range accuracy
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Parameter
Units
Notes/Conditions
VCXO
Resolution Maximum output voltage Minimum output voltage Bits
Guaranteed monotonic Input word FFFH Input word 000H
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Pinout
VDDD_DAC VDDD_DAC GNDD_DAC GNDD_DAC GNDS_DAC GNDSA_DAC DA10 DA11 DA12 DA13 DA14 DA15 TX_SHLD VDD_DAC VDD_DAC DAC_REFM DAC_REFP GND_DAC GND_DAC
AUXCLK REFCLK GND_CLK VDD_CLK GND_ADIO GND_ADIO VDD_ADIO VDD_ADIO GND_ADIO GND_ADIO AD10 VDD_ADIO VDD_ADIO AD11 AD12 AD13 GND_ADIO GND_ADIO AD14 AD15 RESVD GNDS_ADC GNDSA_ADC
VIEW (Not scale)
MQFP 2.71 thick
RESVD VDD_TX VDD_TX GND_TX GND_TX TX_OU95 TX_OUTP GND_TX EC_OUTP EC_OU91 GND_TX VCX_OUT VDD_TX VDD_TX GND_TX REXT_TX TXBGCAP TX_RESRTN RX_RESRTN RXBGCAP REXT_RX GND_RX VDD_RX VDD_RX GND_RX GND_RX RX_INP RX_INM GND_RX GND_RX RXCMIN VDD_RX VDD_RX
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
VDDD_ADC VDDD_ADC GNDD_ADC GNDD_ADC VDD_ADC VDD_ADC GND_ADC GND_ADC ADC_REFP ADC_REFM GND_ADC GND_ADC VDD_ADC VDD_ADC RX_SHLD S_CLK S_EN S_DOUT S_DIN GND_SPIO VDD_SPIO WAKEUP BUSY RESETB
DataPath Systems, Inc.
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Function Description
Number
111,112,113,114, 115,116,117,118, 119,120,121,122, 1,2,3,4
Name
DA15,.,DA0
Function Description
inputs: DA15;
AUXCLK
echo mode, auxiliary clock (=REFCLK/2). Serves data identifying data either transmit echo. non-echo mode, connect ground. Output enable digital outputs (active low) Master reference clock input either 8.832 4.416 Ground +5.0V digital outputs: AD15;
10,11,12,15,16,17, 19,20,21,24,25,26, 29,30,31,34,35 13,14,22,23,32,33 17,18,27,28 39,40 41,42 43,44,51,52 45,46,49,50 47,48
REFCLK GND_CLK VDD_CLK AD0,.,AD15
GND_ADIO VDD_ADIO RESVD GNDS_ADC GNDSA_ADC VDDD_ADC GNDD_ADC VDD_ADC GND_ADC ADC_REFP, ADC_REFM RX_SHLD S_CLK S_EN S_DOUT S_DIN
Ground Power supply outputs (+3.3V +5V) Reserved connect Ground Ground +5.0V Ground +5.0V Ground reference voltage outputs Ground Serial port clock input Serial port enable input Serial port data output from Serial port data input
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Number
63,64 65,66,67 68,69,77,78 71,72,75,76,79 73,74 86,90,93,96,97 87,88,98,99 91,92 94,95
Name
GND_SPIO VDD_SPIO RESVD BUSY RESETB CS1,CS0 GP0, GP1, VDD_RX RXCMIN GND_RX RX_INP, RX_INM REXT_RX RXBGCAP RX_RESRTN TX_RESRTN TXBGCAP TEXT_RX GND_TX VDD_TX VCX_OUT EC_OUTP, EC_OUTX_OUTP, TX_OU
Function Description
Ground +5.0V Reserved connect Active high output indicating chip self-calibration reset mode Resets internal state chip (active low) Chip select address inputs General purpose (default: connect) +5.0V Common-mode reference voltage output Ground Analog inputs External resistor connection side External capacitor connection side Resistor return side Resistor return side External capacitor connection side External resistor connection side Ground +5.0V VCXO output voltage Analog outputs echo path Analog outputs path
101,102,103 104,105 106,107 108,109
RESVD GP3, GP4, GND_DAC DAC_REFP, DAC_REFM VDD_DAC TX_SHLD
Reserved connect General purpose (default: connect) Ground reference voltage outputs +5.0V Ground
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Number
125,126 127,128
Name
GNDSA_DAC GNDS_DAC GNDD_DAC VDDD_DAC
Function Description
Ground Ground Ground +5.0V
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Operation Functionality
Overview
following sections describe greater detail individual blocks functions chip with particular focus register bits associated with various modes. First, Section 7.2, some global modes described. Then, Sections 7.3-7.6, path, path, ADC, respectively discussed. Section describes serial port interface Sections cover some ADSL modem support functions included chip some miscellaneous interface issues, respectively. portion chip, incoming analog differential signal (maximum level peakto-peak differential, i.e., relative enters chip RX_INP, RX_INM pins. analog signal path partitioned into continuous-time (CT) section ADC. section consists number stages programmable gain followed order lowpass filter. gain user programming RXGAIN register. output filter directly ADC, which samples either 4.416 MS/s 2.208 MS/s outputs 16-bit wide parallel word. portion chip, when echo path used, incoming 16-bit digital word 4.416 update rate. output re-sampled (de-glitched) passed continuous-time section comprising order lowpass filter followed programmable attenuation amplifier (PAA). amount attenuation user programming TXGAIN register. output appears TX_OUTP, TX_OUpins drive ac-coupled load parallel with maximum level ±2.5 When echo path used, chip accepts digital data 8.832 rate alternate digital words passed ping-pong fashion main path echo path, which each operate 4.416 MHz. identify which sample goes path which goes echo path, "label" "tag" input, AUXCLK, used, which described more detail later. chip requires single low-jitter clock applied REFCLK pin. clock generation performed internally converter clocks both paths directly derived from REFCLK. REFCLK must always either 4.416 8.832 MHz; frequency tolerance ±100ppm. When echo path used, REFCLK should 4.416 MHz. When echo path used, REFCLK should 8.832 AUXCLK should used identify echo data. Since AUXCLK alternates between each period REFCLK, could viewed 4.416 clock signal. MODE register sets appropriate sample rates enables disables echo path, discussed Section 7.2.2. versions chip exist customized ATU-R customized ATU-C. ATU-R version contains high-bandwidth path lowpass filter low-bandwidth TX/echo path lowpass filters. ATU-C version contains high-bandwidth TX/echo path lowpass filters low-bandwidth path lowpass filter. remaining blocks behave identically versions.
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Global Modes Power Control
7.2.0 Introduction
chip configured number ways depending particular system requirements. These configurations include various sample rates individual functional block power control modes enabling power saved when block used. chip registers 16-bit wide; detailed read/write protocol discussed Section 7.8. following sections registers tabulated 8-bit bytes, byte high byte, that form 16-bit word. Each register address associated name. register shaded, this indicates that reserved internal test only should value indicated. later versions this document, DataPath supply alternative settings these registers. Unless otherwise stated, register descriptions hold both ATU-R ATU-C versions chip. power-up, chip expects active reset pulse applied RESETB pin. This resets gain mode registers particular values, which detailed below. useful debugging check read back state these registers after reset check that values expected.]
7.2.1 Global Power Control Register (PWR)
global power on/off control individual blocks chip register, (01H), tabulated below.
Register (PWR)
Name Reset Value (ATU-C) (ATU-R Name Reset Value (ATU-C) (ATU-R) (ATU-C) (ATU-R)
convention power on/off follows. block power block power
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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assignment individual bits register follows.: Chip initialization support circuits Chip initialization support circuits Chip initialization support circuits Chip initialization support circuits VCXO blocks echo path blocks primary path blocks path block i.e., filter/PGA/PAA etc.
Note that whenever analog block powered appropriate time must allowed settling internal bias circuits.
7.2.2 Global Mode Control Register (MODE)
chip configurable support various converter rates filter modes signal paths. These global modes primarily using MODE register, tabulated below.
Register (MODE)
Name Reset Value Name Reset Value RXFLTLOW TXFLTLOW CLK1 (ATU-C) (ATU-R) CLK0 AUXCLKINV
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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ISDN Mode Halfband Mode Control fast-channel (downstream) filters (ATU-R ATU-C default 1.104 reset. (Note, however, that halfband mode exists ATU-R receive filter, detailed below.) register bits RXFLTLOW TXFLTLOW control bandwidth settings upstream filters halfband mode, follows. TXFLTLOW: low-bandwidth mode transmit-path filters. case ATU-R: enable ISDN mode (all transmit/echo filters kHz). non-ISDN mode (all transmit/echo filters kHz).
case ATU-C: normal mode (all transmit/echo filters 1.104 MHz). reserved
RXFLTLOW: low-bandwidth mode receive-path filters. case ATU-R: normal mode (receive filter 1.104 MHz). halfband mode (receive filter kHz).
case ATU-C: enable ISDN mode (receive filter kHz). non-ISDN mode (receive filter kHz).
Clock Mode Control CLK[1:0] bits control clocking modes depending whether echo path used not. Their functionality follows. CLK[0]: clock rate. samples 4.416 samples 2.208 CLK[1]: Echo path clocks enable. echo clocks disabled chip expects single 4.416 reference clock REFCLK pin. echo path associated functions enabled chip expects 8.832 clock REFCLK 4.416 clock AUXCLK select ECHO data. AUXCLK identifies transmit data AUXCLK identifies echo data
ADSL Analog Front Data Sheet V1.1.1 01/20/2000 DataPath Systems, Inc.
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summary four possible clocking configurations based CLK[1:0] given below. CLK[1:0] Echo Path REFCLK 4.416 4.416 8.832 8.832 AUXCLK 4.416 4.416 4.416 2.208 4.416 2.208
WARNING
voltages REFCLK AUXCLK pins CLK[1:0] register bits must correspond according above table. example, setting CLK[1:0]=10 with AUXCLK grounded will result unpredictable behavior. MODE register does control analog power on/off. Therefore, echo path used, relevant bits both MODE registers need accordingly. Note that only possible either 4.416 MS/s 2.208 MS/s; always samples incoming digital data 4.416 MHz.
TX/Echo Timing Protocol AUXCLKINV: Inverts interpretation TX/Echo data with respect AUXCLK when echo path used; Section 7.6.1.
7.2.3 Chip Startup/Initialization Sequence
information below given reference guideline only. DataPath will supply this entire initialization sequence described below list register writes, e-mail floppy disk. user simply download appropriate register values, wait initialization complete.
WARNING
This initialization sequence, including register download supplied DataPath required operate chip. Without this, chip will work. power-up, chip expects RESETB (pin held least power supply voltages applied chip must stable during this time. This reset causes registers chip (excluding certain registers associated with DAC) reset known states. Those reset values documented register definitions each register. ATU-R ATU-C have different reset values some registers.
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Note that analog blocks chip require significant time power come their quiescent states. Allowance needed also thermal time constants associated with package/board. Following this hard reset RESETB pin, before entering chip initialization phase, user should program registers that required different from their default values especially MODE registers. Next, following writes must occur: must written bits P10, P11, register, must written MODE register 0080H must written register (CALC)
user must then download DataPath-supplied values registers chip. These values, along with register writes already described this section, will supplied DataPath floppy disk e-mail. Next, chip initialized triggering internal initialization functions. user must write BIT4 register (CALC) start internal initialization sequence. Since must maintained set, this means that user should write 0090H register 03H. Once chip enters initialization, asserts active high signal BUSY (pin 61). When initialization complete, BUSY de-asserted chip ready normal operation. During initialization, (BUSY asserted), user should write registers chip. maximum duration this initialization phase Note that BUSY cannot tristated: always driven either high low. Upon completion internal initialization operations, initialization control (BIT4) register CALC reset. debugging check, user further check that initialization completed correctly reading back contents CALC register: should 0080H. After initialization, following writes should occur: should written bits P10, P11, register, must written MODE register. write register optional powers down some initialization support circuits. write MODE register mandatory.
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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7.2.4 Initialization Control Register (CALC)
mentioned above, chip initialization performed writing appropriate bits CALC register, tabulated below.
Register (CALC)
Name Reset Value Name Reset Value BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
TWOS
BIT[7:0] trigger internal initialization operations. When particular SET, operation started. When operation completed, RESET. BIT7: Enable complete initialization BIT4: Start complete initialization TWOS: Two's complement control outputs (described later Section 7.3.5). mentioned Section 7.2.3 above, trigger initialization, user should write BIT7 BIT4 register CALC.
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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Continuous-Time Blocks Path
7.3.0 Introduction
continuous-time (CT) blocks comprise major portion receive analog signal paths, providing programmable gain filtering. high-level block diagram signal path shown below Fig.
Filter Fine
Low-Noise Coarse
Fig. Diagram showing major portions receive signal path
primary receive inputs differential, should capacitively coupled into chip. avoid clipping, signal swing inputs should exceed peak-to-peak differential peak-to-peak single ended). chip provides common-mode voltage marked RXCMIN), input common mode established pair resistors board, shown Fig. Output drive capability RXCMIN maximum ground).
RX_RESRTN (82) CHIP RX_INP (74)
RXCMIN (70)
High Voltage Line Receiver From hybrid/line
RX_INM (73)
Fig. Recommended receive-side chip interface. Note that other connections RX_RESRTN illustrated Fig.
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.
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From block diagram, there programmable gain amplifiers (PGA), providing coarse-resolution gain control steps) providing fine-resolution gain control (0.25 steps). coarse (register bits RXGAIN[4:0]) lower noise, whereas fine (register bits RXGAIN[11:5]) higher linearity. Thus, general guideline, maximize noise performance receive path, gain should preferentially placed coarse opposed fine i.e., long lines where input signal level minimum. moderate large input signals where only gain needed linearity more important, recommended employ fine first. Furthermore, achieve maximum overall system noise performance, high-voltage line receiver driving these inputs needs low-noise possible, while maintaining required distortion performance. internal analog signal level full-scale reference level peak-to-peak differential (2.5 peak-to-peak single ended). Thus, chip input level exceeds peakto-peak differential, must programmed provide attenuation. fourth order receive filter implemented simple cascade second-order lowpass structures. aggregate filter cutoff frequency function ATU-R (1.1 MHz) ATU-C (138 kHz, depending ISDN mode); these values held within ±5%. halfband mode (552 kHz) exists ATU-R case support lower-bandwidth ADSL variants (such emerging G.lite standard). response type filter also varies from ATU-R ATU-C. ATU-R case, each second-order stages true Butterworth lowpass response. ATU-C case, fifth offchip pole desirable increase rejection out-of-band signals, thus on-chip filter some peaking compensate in-band loss. Specifically, off-chip pole frequency should non-ISDN mode), ISDN mode). resultant fifth-order structure (the off-chip pole plus fourth-order on-chip filter) aggregate response that flat magnitude response, with frequency (non-ISDN mode) (ISDN mode). actual implementation fifth pole customer-dependent; embedded within hybrid, placed within high-voltage line receiver itself. s-domain equations nominal filter transfer functions follows. ATU-R cascade 2nd-order Butterw orth sections; regrate cascade bandwidth 1.104 MHz. half-band mode, this response scales kHz. 1.330 1.631 ATU-C cascade 2nd-order sections; yields magnitude response ving bandwidth when cascaded with off-chip pole section Q=1.1 compensate off-chip pole. 1.4140 9.2579 ISDN mode, this response scales frequency 320-kHz chip pole required. ISDN 7.0711 4.6290
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DataPath Systems, Inc.
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7.3.1 Receive Path Control Register (RXGAIN)
primary functionality controlled RXGAIN register, described below:
Register (RXGAIN)
Name
Reset Value
PAA2
PAA1
PAA0
PGA4
PGA3
PGA2
PGA1
PGA0
Name
Reset Value
PAA6
PAA5
PAA4
PAA3
WARNING NOTE ABOUT RXGAIN REGISTER:
After re-programming gain registers, minimum symbol time (250 needs allowed ensuing transient away. During this output invalid. PGA[4:0]: Coarse gain setting. gain. 00000 11111 (00111 default, dB). achieve precise steps, 5-bit control word thermometer encoded: PGA[4:0] 00000 00001 00011 00111 01111 11111 Gain (dB) Gain (Linear) 16.0
other control values interpolate gain between these values, linear steps 0.5. example, control word 00100 (equal 00011 yields gain (linear scale) 0.5, i.e., (+7.96 dB). This represented equation given below. Gain (dB) log10 (gain_word
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PAA[6:0]: (fine PGA) gain setting. gain 0.25 steps. 0000000= (default dB). achieve precision control 0.25 steps gain, very fine-grain control provided, exact specification gain values given below. should noted that table lists only PAA[5:0], instead PAA[6:0]. MSB, PAA[6], yields additional gain RXPAA this additional gain PAA[5:0]. mentioned earlier, maximize noise performance, more preferable place gain coarse opposed fine PGA. particular, final PAA[6]) should only utilized under longest line conditions. fine gain represented equation given below. Gain (dB) log10 0.0246825 gain_word
Programmable Gains bits PAA[5:0]. Note: PAA[6]=1 gives additional
PAA[5:0] 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 Gain 1.0246 1.0493 1.0740 1.0987 1.1234 1.1481 1.1728 1.1975 1.2222 1.2469 1.2716 1.2962 1.3209 1.3456 1.3703 1.3950 1.4197 1.4444 0.211 0.418 0.620 0.818 1.011 1.199 1.384 1.565 1.743 1.916 2.087 2.254 2.417 2.578 2.736 2.891 3.044 3.194
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
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010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000
1.4691 1.4938 1.5185 1.5432 1.5679 1.5925 1.6172 1.6419 1.6666 1.6913 1.7160 1.7407 1.7654 1.7901 1.8148 1.8395 1.8641 1.8888 1.9135 1.9382 1.9629 1.9876 2.0123 2.0370 2.0617 2.0864 2.1111 2.1358 2.1604 2.1851
3.341 3.486 3.628 3.768 3.906 4.042 4.175 4.307 4.436 4.564 4.690 4.814 4.937 5.057 5.176 5.294 5.409 5.524 5.636 5.748 5.858 5.966 6.074 6.179 6.284 6.388 6.490 6.591 6.691 6.789
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
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110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
2.2098 2.2345 2.2592 2.2839 2.3086 2.3333 2.3580 2.3827 2.4074 2.4320 2.4567 2.4814 2.5061 2.5308 2.5555
6.887 6.983 7.079 7.173 7.267 7.359 7.450 7.541 7.630 7.719 7.807 7.894 7.980 8.065 8.149
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gain versus code relationship shown graphically below.
25.0 20.0 15.0
[dB]
10.0
-5.0 -10.0
PGA[4:0]
Fig. Functional relationship between first (coarse) gain register code.
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DataPath Systems, Inc.
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gain versus code relationship shown graphically below.
16.0 14.0 12.0
[dB] 10.0
PAA[6:0]
Fig. Functional relationship between second (fine) gain register code.
7.3.2 Receive Path Coarse High-Pass Filter
well accurate low-pass filter described above Section 7.3.0, receive path available un-tuned high-pass filter consisting cascaded real high-pass poles, each approximately kHz. composite 2nd-order high-pass corner approximately kHz. This filter engaged setting register (Note that register normally 0012H after initialization.) tolerance this high-pass cutoff frequency approximately ±50%. Therefore, pole should relied accurate band-edge control best used purposes additional out-of-band energy suppression.
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DataPath Systems, Inc.
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Continuous-Time Blocks Path
7.4.0 Introduction
section continuous-time signal processing includes analog reconstruction filtering DAC, droop compensation, fine control system transmit power. section consists identical blocks, primary transmit output other provide echo functionality. typical ADSL system using non-overlapped upstream downstream bands, echo path used, powered down. existence echo path affords system designer several degrees freedom modeling echo cancellation signal done adaptively transmit side, digital domain. Other approaches, such fixed analog compromise hybrid, limited their adaptability, digital echo cancellation receive side incurs large dynamic range penalty ADC. course, system designer revert these more traditional methods echo cancellation, with concomitant reduction power consumption chip. high-level block diagram entire section shown below:
Filter
Echo Filter
Echo
Fig. Diagram showing major portions transmit echo paths.
Like receive filter, transmit filter's cutoff frequency function ATU-C (1.104 MHz) ATU-R (138 kHz, depending ISDN mode); these values held within ±5%. response simple fourth-order lowpass, implemented pair second-order Butterworth structures. s-domain equations nominal filter transfer functions follows.
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ATU-C cascade 2nd-order Butterw orth sections; regrate cascade bandwidth 1.104 MHz. 1.330 1.631 ATU-R cascade 2nd-order Butterw orth sections; regrate cascade bandwidth kHz. ISDN mode, this response scales kHz. 8.5104 1.3046 Note that full compliance with G.992.1 G.992.2 transmit masks, additional off-chip filtering path needed. outputs both transmit echo signal paths differential, with peak signal swing peak-to-peak differential (2.5 peak-to-peak single-ended). recommended that outputs capacitively coupled into subsequent high voltage line driver. load-driving capability maximum linearity, each output designed individually drive resistance smaller than capacitive load greater than Given tight gain-control specification ADSL standard, gain accuracy entire transmit path designed better than ±0.5 about nominal value. improve absolute gain accuracy, large load resistance excess should used. nominal gain settings described below.
7.4.1 Transmit Path Control Register (TXGAIN)
main functions path controlled TXGAIN register.
Register (TXGAIN)
Name Reset Value Name Reset Value ECPA7 ECPA6 ECPA5 ECPA4 ECPA3 ECPA2 ECPA1 ECPA0
TXPA7
TXPA6
TXPA5
TXPA4
TXPA3
TXPA2
TXPA1
TXPA0
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WARNING NOTE ABOUT TXGAIN REGISTER:
After re-programming gain/attenuation registers either ECHO paths, minimum symbol period (250 should allowed ensuing transient away. During this time, both path ECHO path outputs invalid, that fullpower transients cannot emitted onto twisted-pair line.
ECPA[7:0]: Echo path output attenuator gain setting. attenuation steps. (default dB). Note that 00000000 corresponds attenuation, 11111111 corresponds TXPA[7:0]: Transmit path output attenuator gain setting. attenuation steps. (default dB). Note that 00000000 corresponds attenuation, 11111111 corresponds encoding both TXPA[7:0] ECPA[7:0] follows: upper bits (TXPA[7:5] ECPA[7:5]) encode attenuation factor coarsely(0 steps), with lower bits (TXPA[4:0] ECPA[4:0]) encoding attenuation fine scale steps). upper bits, coarse attenuation control quasi-thermometer encoded, follows.
lower bits, fine attenuation control quasi-binary encoded, follows. 00000 00100 01000 01101 10011 11001 11111
NOTE: this last case overlaps coarse fine control bits, required achieve complete attenuation).
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EXAMPLES TXGAIN REGISTER: 00000 coarse, fine 00100 coarse, fine 01000 coarse, fine 01101 coarse, fine 10011 coarse, fine 11001 coarse, fine 11111 coarse, fine TXPAA gain function TXPA[7:0] register code 255) given equation below.
code Gain code%32 where: (code numerator integer division, (code denominator modulo.
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gain versus code relationship both shown graphically below.
-5.0
[dB] -10.0
-15.0
-20.0
-25.0
TXPA[7:0]
Fig. Functional relationship between attenuation register code.
7.4.2 Transmit Path Coarse High-Pass Filter
well accurate low-pass filter described above Section 7.4.0, transmit path available un-tuned high-pass filter consisting real high-pass pole approximately kHz. This filter engaged setting register (Note that register normally 0012H after initialization.) tolerance this high-pass cutoff frequency approximately ±50%. Therefore, pole should relied accurate band-edge control best used purposes additional out-of-band energy suppression.
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7.5.0 Introduction
output filter directly ADC. described earlier, chip requires single low-jitter clock applied REFCLK pin. clock generation performed internally clock directly derived from REFCLK. sampling rate CLK[1:0] bits MODE register either 4.416 MS/s 2.208 MS/s. Note that REFCLK must always either 4.416 8.832 MHz; required divided down clocks generated internally.
7.5.1 Digital Output Timing
chip implements simple interface: outputs appear AD15,.AD0 pins parallel word synchronous with sampling clock. AD15 MSB. timing diagram digital outputs shown Fig. figure shows case where sampling clock same frequency REFCLK.
REFCLK
Outputs
ADC[n]
ADC[n+1]
Fig. Timing diagram outputs.
data changes rising edge REFCLK latched falling edge. cases where sampling rate less than REFCLK, above timing relationships still hold, with data changing every second every fourth clock edge, appropriate. latency through from filter output digital outputs clock cycles clock. voltage levels AD15,.,AD0 lines CMOS levels: HIGH level determined power supply voltage VDD_ADIO pins, which independently other supply pins chip. Typically, VDD_ADIO should +3.3V: this ensures that outputs both TTL-compatible 3.3V-CMOS compatible.
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7.5.2 References
full scale range reference voltages generated chip. These reference voltages appear pins ADC_REFP ADC_REFM; nominally their difference ADC_REFP ADC_REFM pins should very carefully decoupled board using low-ESR capacitor short trace possible. Some optimization decoupling required, shown Fig.
required
CHIP
ADC_REFP (47)
10µF 0.1µF 0.1µF
ADC_REFM (48)
0.1µF
Fig. Recommended connection pins ADC_REFP ADC_REFM.
range adjustment: default value reference single-ended. However, some adjustment possible using register bits REFADC[1:0] located register (MISC1), bits MISC1[5:4] REFADC[1:0] differential-mode reference (nominal 100%, default value) differential-mode reference 2.1875 (87.5%) differential-mode reference (125%) differential-mode reference 2.8125 (112.5%) Note that full linearity guaranteed outside nominal reference setting, 125% setting especially should used with caution.
7.5.3 Other Functions
OUTPUT ENABLE: digital outputs enabled active output enable (OEB). digital outputs AD15,.,AD0 enabled digital outputs AD15,.,AD0 high-impedance (tristated). FORMAT: format digital data controlled TWOS (bit CALC register), which tabulated Section 7.2.3. AD15,.,AD0 uses unsigned format AD15,.,AD0 uses twos' complement format
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7.6.0 Introduction
accepts 16-bit word DA15,.,DA0 pins generates analog signal continuous time blocks path.
7.6.1 Digital Input Timing
timing diagram input digital data when echo path used given below Fig. this case, AUXCLK (pin used should tied GND.
REFCLK
(4.416 MHz)
Inputs
DAC[n]
DAC[n+1]
Fig. Timing diagram digital inputs.
expects incoming digital data change falling edge REFCLK data latched internally rising edge. Thus, data should stable rising edge.
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timing diagram input case when both echo paths used given below Fig.
AUXCLK
REFCLK
(8.832 MHz)
Inputs
TX[n-1]
Echo[n-1]
TX[n]
Echo[n]
Fig. Timing diagram digital inputs (DA15,.,DA0) with echo path path both used.
Note that AUXCLK must change rising edge REFCLK. value AUXCLK latched internally falling edge REFCLK. expects incoming digital data change falling edge REFCLK latched internally rising edge. Thus, data should stable rising edge. latency through from rising edge REFCLK which incoming digital data latched instant when analog sample transferred filter periods REFCLK clock. Detailed information setup/hold times given Section this document.
WARNING NOTE ABOUT TX/ECHO TIMING:
Note: MODE register must TX/Echo data timing work shown above. With (default condition), TX/Echo ordering with respect AUXCLK swapped.
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7.6.2 References
full scale range reference voltages generated internally chip. These reference voltages appear pins DAC_REFP DAC_REFM. case references, these pins should very carefully decoupled board using higher) low-ESR capacitor using traces short possible. Some optimization decoupling required, shown Fig.
required
CHIP
DAC_REFP (106)
10µF 0.1µF 0.1µF
DAC_REFM (107)
0.1µF
Fig. Recommended decoupling pins DAC_REFP DAC_REFM.
range adjustment: default value reference single-ended. However, some adjustment possible using register bits REFDAC[1:0] located register (MISC1), bits MISC1[7:6] REFDAC[1:0] differential-mode reference (nominal 100%, default value) differential-mode reference 2.1875 (87.5%) differential-mode reference (125%) differential-mode reference 2.8125 (112.5%)
Note that full linearity guaranteed outside nominal reference setting, 125% setting especially should used with caution.
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Serial Port Interface
7.7.0 Introduction
serial port interface controls read/write registers chip. interface consists active-low enable input (S_EN), serial clock input (S_CLK), data input (S_DIN) data output (S_DOUT). timing diagram operation serial port shown Fig. After S_EN asserted, chip-selects (CS1, CS0), serial port register address (A4-A0) read/write control (R/W) ially cloc ising edge S_CLK. write operation (R/W=1), addressed register updated upon receiving 16-bit write data (D15-D0). read operation (R/W=0), 16-bit contents addressed register sequentially shifted S_DOUT falling edge S_CLK. shown Fig. S_DOUT driven only when data being read. Otherwise, tristated.
7.7.1 Serial Port Timing
timing diagram serial port shown Fig.
S_EN S_CLK S_DIN S_DOUT
Fig. Timing diagram serial port
Detailed information setup/hold times given Section this document.
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Support Blocks
7.8.0 Introduction
support blocks chip consist voltage-mode drive external voltagecontrolled crystal oscillator (VCXO), some general purpose digital outputs.
7.8.1 VCXO Control Register (VCXO)
VCXO 12-bit voltage-mode designed monotonic intended operated update rate. source sink current. order update DAC, user must write VCXO register through serial port. individual definitions given below.
Register (VCXO)
Name Reset Value Name Reset Value VCX7 VCX6 VCX5 VCX4 VCX3 VCX2 VCX1 VCX0
VCX11
VCX10
VCX9
VCX8
VCX[11:0]: VCXO 12-bit word. nominal output voltages extreme mid-scale codes follows. VCXO[11:0] 000000000000 000H: above VCXO[11:0] 100000000000 800H: 2.25 above (mid-range) VCXO[11:0] 111111111111 FFFH: above general expression output voltage (CODE 4096) (3.5 where CODE decimal integer value 12-bit word formed VCXO[11:0].
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7.8.2 Miscellaneous Functions Register (MISC1)
MISC1 register contains general purpose definitions.
Register (MISC1)
Name Reset Value Name Reset Value REFDAC1 REFDAC0 REFADC1 REFADC0
Register bits GP[5:0]: values GP[5:0] appear directly pins GP5,.,GP0 (103-101, 67-65) CMOS digital levels available user. Bits REFDAC[1:0] REFADC[1:0] were described earlier sections.
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Miscellaneous Interface External Component Connections
EXTERNAL RESISTOR CONNECTIONS: connections groups pins {REXT_TX, TXBGCAP, TX_RESRTN} {REXT_RX, RXBGCAP, RX_RESRTN} critical should routed very carefully board. connections shown Fig. below. traces to/from these pins should short possible.
2.00 (1%)
REXT_TX (85) TXBGCAP (84)
(X7R, ESR)
TX_RESRTN (83) CHIP
RX_RESRTN (82)
(X7R, ESR)
RXBGCAP (81) REXT_RX (80)
2.00 (1%)
Fig. Recommended connection pins 80-85. Note that RX_RESRTN also used decoupling RXCMIN pin, shown previously Fig.
GENERAL GUIDELINE CONNECTION DIGITAL INPUTS: general, digital inputs chip should connected impedance (either +3.3 +5.0 GND). Leaving digital inputs floating result unreliable behavior digital inputs have internal pull-up pull-down resistors. Specifically, this applies following pins chip: DA15,.,DA0, AUXCLK, OEB, REFCLK, S_CLK, S_EN, S_DIN, RESETB, CS1, CS0.
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Timing Specifications
Overview
This section gives detailed timing specifications various digital interfaces chip.
REFCLK
AD[15:0] OVR_RNG
Parameter
REFCLK high Data Valid inactive active Data Valid
Symbol
Units
Conditions: load capacitance
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REFCLK
TSU1
Inputs DA[15:0]
DAC[n]
DAC[n+1]
Parameter
inputs setup time inputs hold time
Symbol
TSU1
Units
AUXCLK Timing Echo Mode
REFCLK
TSU1
AUXCLK
Parameter
AUXCLK input setup time AUXCLK input hold time
Symbol
TSU1
Units
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Serial Port
TCYC TSU1 TPWH
S_EN
TPWL
S_CLK
TSU2
S_DIN
S_DOUT
Parameter
S_CLK clock period S_CLK high time S_CLK time S_EN S_CLK high S_CLK high S_EN high S_EN inactive pulse width S_DIN setup time S_DIN hold time S_CLK S_DOUT delay S_EN inactive S_DOUT
Symbol
TCYC TPWH TPWL TSU1 TSU2
Units
Conditions: load capacitance
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Package Drawing
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Appendix Document Revision History
V1.1.1 (01/20/2000) Tolerances coarse high-pass filters available path path changed Sections 7.3.2 7.4.2, respectively. Contact addresses phone numbers title page updated.
V1.1.0 (09/15/99) Description coarse high-pass filters available path path added Sections 7.3.2 7.4.2, respectively. Description range programmability added Sections 7.5.2 7.6.2, respectively.
V1.0.1 (09/03/99) Minor typo fixes. Resistor values corrected Fig.
V1.0.0 (08/07/99) First version
ADSL Analog Front Data Sheet V1.1.1 01/20/2000
DataPath Systems, Inc.

DataPath Systems, Inc. 01/20/2000 further information, pleas

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