Mbit x16) 1.8V Asynchronous SRAM FEATURES SUMMARY SUPPLY VOLTAGE:
|
|
|
Top Searches for this datasheet
M68AR024D
Mbit x16) 1.8V Asynchronous SRAM
FEATURES SUMMARY SUPPLY VOLTAGE: 1.65 1.95V
Figure Packages
SUPPLY VOLTAGE: 1.95V WORDS bits POWER SRAM EQUAL CYCLE ACCESS TIME: 70ns DATA RETENTION: 1.0V STANDBY CURRENT TRI-STATE COMMON SINGLE BYTE READ/WRITE AUTOMATIC POWER DOWN
TFBGA48 (ZH) (for Engineering Samples only)
TFBGA48 (ZB)
October 2002
This preliminary information product development undergoing evaluation. Details subject change without notice.
1/19
M68AR024D
TABLE CONTENTS SUMMARY DESCRIPTION Figure Logic Diagram Table Signal Names Figure TFBGA Connections (Top view through package) Figure Block Diagram MAXIMUM RATING. Table Absolute Maximum Ratings PARAMETERS. Table Operating Measurement Conditions Figure Measurement Waveform Figure Measurement Load Circuit Table Capacitance. Table Characteristics. OPERATION Table Operating Modes Read Mode Figure Address Controlled, Read Mode Waveforms Figure Chip Enable Output Enable Controlled, Read Mode Waveforms Figure Chip Enable UB/LB Controlled, Standby Mode Waveforms Table Read Standby Mode Characteristics Write Mode Figure Write Enable Controlled, Write Waveforms Figure Chip Enable Controlled, Write Waveforms Figure UB/LB Controlled, Write Waveforms Table Write Mode Characteristics Figure Controlled, Data Retention Waveforms Figure Controlled, Data Retention Waveforms Table Data Retention Characteristics PACKAGE MECHANICAL Figure TFBGA48 6.5x10mm ball array, 0.75 pitch, Bottom View Package Outline. Table TFBGA48 8x10mm ball array, 0.75 pitch, Package Mechanical Data. PART NUMBERING Table Ordering Information Scheme REVISION HISTORY Table Document Revision History
2/19
M68AR024D
SUMMARY DESCRIPTION M68AR024D Mbit (16,777,216 bit) Power SRAM fabricated STMicroelectronics advanced CMOS technology, organized 1,048,576 words bits. device exhibits fully static operation requiring external clocks timing strobes. needs 1.65 1.95V supply voltage. using VCCQ outputs powered independently from core supply voltage allowing drive pins down 1.5V. tied feature required.
This device standard Asynchronous SRAM Interface. Read Write cycles performed single byte using UB/LB signals. device into standby mode using E1/E2 pins. same pins used cascade more devices order achieve deep memory expansion. Standby mode allows current consumption, 99%, reducing internal activities. M68AR024D available TFBGA48 (0.75 pitch) package with industrial standard footprint.
Figure Logic Diagram
VCCQ
Table Signal Names
A0-A19 DQ0-DQ15 Address Inputs Data Input/Output Chip Enables Output Enable Write Enable Upper Byte Enable Input Lower Byte Enable Input Supply Voltage Supply Voltage Ground Connected Internally Don't Internally Connected
A0-A19 M68AR024D
DQ0-DQ15
VCCQ
AI05400c
3/19
M68AR024D
Figure TFBGA Connections (Top view through package)
DQ10
DQ11
VCCQ
DQ12
DQ14
DQ13
DQ15
AI05918
4/19
M68AR024D
Figure Block Diagram
DECODER MEMORY ARRAY
DQ15
CIRCUITS COLUMN DECODER
AI05924
MAXIMUM RATING Stressing device above rating listed Absolute Maximum Ratings table cause permanent damage device. These stress ratings only operation device these other conditions above those indicated Operating sections this specification imTable Absolute Maximum Ratings
Symbol TSTG VCCQ Output Current Power Dissipation Ambient Operating Temperature Storage Temperature Supply Voltage Supply Voltage Input Output Voltage Parameter
plied. Exposure Absolute Maximum Rating conditions periods greater than affect device reliability. Refer also STMicroelectronics SURE Program other relevant quality documents.
Value -0.5 -0.5 -0.5 VCCQ +0.5
Unit
Note: output time exceed second duration. maximum operating VCCQ 1.95V only.
5/19
M68AR024D
PARAMETERS This section summarizes operating measurement conditions, well characteristics device. parameters following Characteristic tables derived from tests performed under Measure-
ment Conditions listed relevant tables. Designers should check that operating conditions their projects match measurement conditions when using quoted parameters.
Table Operating Measurement Conditions
Parameter Supply Voltage VCCQ Supply Voltage (VCCQ VCC) Range Ambient Operating Temperature Range Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages Output Transition Timing Ref. Voltages 85°C 30pF 15.3k 11.3k 1ns/V VCCQ VCCQ/2 0.3VCCQ; 0.7VCCQ M68AR024D 1.65 1.95V 1.95V 70°C
Figure Measurement Waveform
Figure Measurement Load Circuit
VCCQ
Timing Reference Voltage VCCQ VCCQ/2 DEVICE UNDER TEST 0.7VCCQ 0.3VCCQ
AI05987
Transition Timing Reference Voltage VCCQ
includes capacitance
AI05988
6/19
M68AR024D
Table Capacitance
Symbol COUT Parameter (1,2) Input Capacitance pins (except Output Capacitance Test Condition VOUT Unit
Note: Sampled only, 100% tested. 25°C, 1MHz, 1.8V. Outputs deselected.
Table Characteristics
Symbol ICC1 (1,2) Parameter Operating Supply Current Test Condition 1.95V, 1/tAVAV, IOUT 1.95V, 1MHz, IOUT VOUT 1.95V, VCCQ -0.2V 0.2V VCCQ -0.2V, VCCQ -0.3 -100µA 100µA VCCQ Unit
ICC2
Operating Supply Current Input Leakage Current Output Leakage Current
Standby Supply Current CMOS
Note:
Input High Voltage Input Voltage Output High Voltage Output Voltage
VCCQ
Average current, cycling tAVAV minimum. VIH, OR/AND VIL. 0.2V -0.2V, OR/AND 0.2V, 0.2V VCCQ -0.2V. Output disabled.
7/19
M68AR024D
OPERATION M68AR024D Chip Enable power down feature which invokes automatic standby mode whenever Chip Enable de-asserted High) Chip Select asserted Low), UB/LB de-asserted (UB/LB High). Output Enable signal provides high speed tri-state conTable Operating Modes
Operation Deselected/Standby Deselected/Standby Deselected/Standby Lower Byte Read Lower Byte Write Output Disabled Upper Byte Read Upper Byte Write Word Read Word Write
Note: VIL.
trol, allowing fast read/write cycles achieved with common data bus. Operational modes determined device control inputs summarized Operating Modes table (see Table
DQ0-DQ7 Hi-Z Hi-Z Hi-Z Data Output Data Input Hi-Z Hi-Z Hi-Z Data Output Data Input
DQ8-DQ15 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Data Output Data Input Data Output Data Input
Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Read Mode M68AR024D, when Chip Select (E2) High, read mode whenever Write Enable High with Output Enable Low, Chip Enable (E1) asserted. This provides access data from eight sixteen, depending status signal 16,777,216 locations static memory array, specified address inputs. Valid data will available
eight sixteen output pins within tAVQV after last stable address, providing Low. Chip Enable Output Enable access times met, data access will measured from limiting parameter (tELQV, tGLQV tBLQV) rather than address. Data indeterminate tELQX, tGLQX tBLQX, data lines will always valid tAVQV
Figure Address Controlled, Read Mode Waveforms
tAVAV A0-A19 tAVQV VALID tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
AI05403
Note: Low, High, Low, High, and/or Low.
8/19
M68AR024D
Figure Chip Enable Output Enable Controlled, Read Mode Waveforms
tAVAV A0-A19 tAVQV tELQV VALID tAXQX tEHQZ
tELQX tGLQV tGLQX DQ0-DQ15 tBLQV tBLQX
AI07730
tGHQZ
VALID tBHQZ
Note: Write Enable High
Figure Chip Enable UB/LB Controlled, Standby Mode Waveforms
AI05990
9/19
M68AR024D
Table Read Standby Mode Characteristics
M68AR024D Symbol tAVAV tAVQV tAXQX tBHQZ tBLQV tBLQX tEHQZ tELQV tELQX tGHQZ tGLQV tGLQX Read Cycle Time Address Valid Output Valid Data hold from address change Upper/Lower Byte Enable High Output Hi-Z Upper/Lower Byte Enable Output Valid Upper/Lower Byte Enable Output Transition Chip Enable High Output Hi-Z Chip Enable Output Valid Chip Enable Output Transition Output Enable High Output Hi-Z Output Enable Output Valid Output Enable Output Transition Chip Enable High Power Down Chip Enable Power Parameter Unit
Note: Test conditions assume transition timing reference level 0.3VCCQ 0.7VCCQ. given temperature voltage condition, tGHQZ less than tGLQX, tBHQZ less than tBLQX tEHQZ less than tELQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels. Tested initially after design process changes that affect these parameters.
10/19
M68AR024D
Write Mode M68AR024D, when Chip Select (E2) High, Write Mode whenever Low. Either Chip Enable Input (E1) Write Enable input must de-asserted during Address transitions subsequent write cycles. When Low, Low, write cycle begins falling edge. When Low, High, write cycle begins first falling edge Therefore, address setup time referenced Write Enable, Chip Enables UB/LB AVWL, tAVEL tAVBL respectively, determined latter occurring falling edge.
Write cycle terminated earlier rising edge Output enabled Low, High, Low, Low), then will return outputs high impedance within tWLQZ falling edge. Care must taken avoid contention this type operation. Data input must valid DVWH before rising edge Write Enable, tDVEH before rising edge DVBH before rising edge UB/LB, whichever occurs first, remain valid WHDX, tEHDX tBHDX respectively.
Figure Write Enable Controlled, Write Waveforms
tAVAV A0-A19 VALID tAVWH tAVEL tELWH tWHAX
tWLWH tAVWL tWLQZ tWHDX DQ0-DQ15 DATA INPUT tDVWH tBLBH
AI05991
tWHQX
11/19
M68AR024D
Figure Chip Enable Controlled, Write Waveforms
tAVAV A0-A19 VALID tAVEH tAVEL tELEH tEHAX
tAVWL tEHDX DQ0-DQ15 DATA INPUT tDVEH tBLBH
AI05992
tWLEH
Figure UB/LB Controlled, Write Waveforms
tAVAV A0-A19 VALID tAVBH tBHAX
tAVWL tWLQZ DQ0-DQ15 DATA tBHDX DATA INPUT tDVBH tAVBL
AI05993
tWLBH
tBLBH
Note: During this period DQ0-DQ15 output state input signals should applied.
12/19
M68AR024D
Table Write Mode Characteristics
M68AR024D Symbol tAVAV tAVBH tAVBL tAVEH tAVEL tAVWH tAVWL tBHAX tBHDX tBLBH tBLEH tBLWH tDVBH tDVEH tDVWH tEHAX tEHDX tELBH tELEH tELWH tWHAX tWHDX tWHQX tWLBH tWLEH tWLQZ tWLWH Write Cycle Time Address Valid High Addess Valid Address Valid Chip Enable High Address valid Chip Enable Address Valid Write Enable High Address Valid Write Enable High Address Transition High Input Transition High Chip Enable High Write Enable High Input Valid High Input Valid Chip Enable High Input Valid Write Enable High Chip Enable High Address Transition Chip enable High Input Transition Chip Enable High Chip Enable Chip Enable High Chip Enable Write Enable High Write Enable High Address Transition Write Enable High Input Transition Write Enable High Output Transition Write Enable High Write Enable Chip Enable High Write Enable Output Hi-Z Write Enable Write Enable High Parameter Unit
Note: given temperature voltage condition, tWHQZ less than WLQX given device. These parameters defined time which outputs achieve open circuit conditions referenced output voltage levels.
13/19
M68AR024D
Figure Controlled, Data Retention Waveforms
DATA RETENTION MODE 1.95V 1.65V 1.0V tCDR 0.2V
AI05855
Figure Controlled, Data Retention Waveforms
DATA RETENTION MODE 1.95V 1.65V 1.0V tCDR 0.2V
AI05875
Table Data Retention Characteristics
Symbol
Parameter
Test Condition 1.0V, VCCQ -0.2V 0.2V VCCQ -0.2V,
Unit
ICCDR
Supply Current (Data Retention)
tCDR
Chip deselected Data Retention Time Operation Recovery Time VCCQ -0.2V 0.2V VCCQ -0.2V,
tAVAV
Supply Voltage (Data Retention)
Note: other Inputs VCCQ -0.2V 0.2V. Tested initially after design process changes that affect these parameters. tAVAV Read cycle time. input exceed +0.2V.
14/19
M68AR024D
PACKAGE MECHANICAL Figure TFBGA48 6.5x10mm ball array, 0.75 pitch, Bottom View Package Outline
BALL "A1"
BGA-Z30
Note: Drawing scale.
Table TFBGA48 6.5x10mm ball array, 0.75 pitch, Package Mechanical Data
millimeters Symbol 10.000 5.250 0.750 0.875 3.125 0.375 0.375 9.900 6.500 3.750 0.790 0.350 6.400 0.450 6.600 0.100 10.100 0.3937 0.2067 0.0295 0.0344 0.1230 0.0148 0.0148 0.3898 0.2559 0.1476 0.300 1.200 0.400 0.0311 0.0138 0.2520 0.0177 0.2598 0.0039 0.3976 0.0118 0.0472 0.0157 inches
15/19
M68AR024D
Figure TFBGA48 8x10mm ball array, 0.75 pitch, Bottom View Package Outline
BALL "A1"
BGA-Z28
Note: Drawing scale.
Table TFBGA48 8x10mm ball array, 0.75 pitch, Package Mechanical Data
Symbol 10.000 5.250 0.750 2.125 2.375 0.375 0.375 9.900 8.000 3.750 0.350 7.900 0.260 0.900 0.450 8.100 0.100 10.100 0.3937 0.2067 0.0295 0.0837 0.0935 0.0148 0.0148 0.3898 0.3150 0.1476 0.0138 0.3110 millimeters 1.200 0.0102 0.0354 0.0177 0.3189 0.0039 0.3976 inches 0.0472
16/19
M68AR024D
PART NUMBERING Table Ordering Information Scheme
Example: Device Type Mode Asynchronous Operating Voltage 1.65 1.95V Array Organization Mbit x16) Option Chip Enable; Write Standby from Option N-Die Speed Class Package TFBGA48: 0.75 pitch (8x10mm) TFBGA48: 0.75 pitch (6.5x10mm) Operative Temperature 70°C Shipping Tape Reel Packing
Note: This package available Engineering Samples only.
M68AR016
17/19
M68AR024D
REVISION HISTORY Table Document Revision History
Date July 2001 24-Oct-2001 07-Nov-2001 19-Feb-2002 12-Mar-2002 20-Mar-2002 19-Apr-2002 Version First Issue Table Contents added Block Diagram added, Data Retention Waveforms clarified Package Mechanical Data Drawing added Voltage range extended 2.2V Document totally revised Features Summary clarified Tables clarified Figures clarified TFBGA 6.5x10 package added Chip Enable Controlled, Data Retention Waveforms clarified (Figures Revision numbering modified: minor revision will indicated incrementing digit after dot, major revision, incrementing digit before (revision version equals 7.0). Part number changed. Document status changed from Target Specification Preliminary Data. Part number modified. Revision Details
02-Oct-2002
04-Oct-2002 09-Oct-2002
18/19
M68AR024D
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners. 2002 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil Canada China Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www.st.com
19/19
Other recent searches
ZXMP7A17K - ZXMP7A17K ZXMP7A17K Datasheet
STW81100 - STW81100 STW81100 Datasheet
STP70NF03L - STP70NF03L STP70NF03L Datasheet
STB70NF03L-1 - STB70NF03L-1 STB70NF03L-1 Datasheet
Si5479DU - Si5479DU Si5479DU Datasheet
SE3A - SE3A SE3A Datasheet
SE3M - SE3M SE3M Datasheet
LXT16706 - LXT16706 LXT16706 Datasheet
16707 - 16707 16707 Datasheet
LXT16707 - LXT16707 LXT16707 Datasheet
LXT16706 - LXT16706 LXT16706 Datasheet
ADG1208 - ADG1208 ADG1208 Datasheet
ADG1209 - ADG1209 ADG1209 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
