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DS0026 Dual High-Speed MOS Driver

DS0026 Dual High-Speed MOS Driver

DS0026 Dual High-Speed MOS Driver
February 2002
DS0026 Dual High-Speed MOS Driver
General Description
DS0026 is a low cost monolithic high speed two phase MOS clock driver and interface circuit. Unique circuit design provides both very high speed operation and the ability to drive large capacitive loads. The device accepts standard TTL outputs and converts them to MOS logic levels. The device may be driven from standard 54 / 74 series and 54S / 74S series gates and flip-flops or from drivers such as the DS8830 or DM7440. The DS0026 is intended for applications in which the output pulse width is logically controlled i.e., the output pulse width is equal to the input pulse width. The DS0026 is designed to fulfill a wide variety of MOS interface requirements. Information on the correct usage of the DS0026 in these as well as other systems is included in the application note AN-76.
Features
Connection Diagram (Top View)
Dual-In-Line Package
DS005853
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DS0026
Absolute Maximum Ratings
(Note 1)
Operating Ratings
If Military / Aerospace specified devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. (V+) - (V-) Differential Voltage Input Current Input Voltage (VIN) - (V-) Peak Output Current Storage Temperature Range Lead Temperature (Soldering, 10 sec.) 22V 100 mA 5.5V 1.5A -65°C to +150°C 300°C
Ordering Information
Order Number DS0026CN DS0026CMA DS0026CMM Package Type M-DIP SOIC MSOP NS Package Number N08E M08A MUA08A
Electrical Characteristics (Notes 2, 3, 4)
Switching Characteristics
(Figure 1) (Figure 2) (Figure 1) (Figure 2) (Figure 1), (Note 5) (Figure 2), (Note 5)
Fall Time
(Figure 1), (Note 5) (Figure 2), (Note 5)
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DS0026
Switching Characteristics
(Continued)
Note 5: Rise and fall time are given for MOS logic levels i.e., rise time is transition from logic "0" to logic "1" which is voltage fall. Note 6: The high current transient (as high as 1.5A) through the resistance of the internal interconnecting V- lead during the output transition from the high state to the low state can appear as negative feedback to the input. If the external interconnecting lead from the driving circuit to V- is electrically long, or has significant dc resistance, it can subtract from the switching response. Note 7: Derate N08E package 9.3 mW / °C for TA above 25°C.
Typical VBB Connection
Typical Performance Characteristics
Input Current vs Input Voltage Supply Current vs Temperature Turn-On and Turn-Off Delay vs Temperature
Rise Time vs Load Capacitance
Fall Time vs Load Capacitance
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DS0026
Typical Performance Characteristics
Recommended Input Coding Capacitance
(Continued) DC Power (PDC) vs Duty Cycle
Schematic Diagram
1 / 2 DS0026
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DS0026
AC Test Circuits and Switching Time Waveforms
FIGURE 1.
FIGURE 2.
Typical Applications
AC Coupled MOS Clock Driver
DC Coupled RAM Memory Address or Precharge Driver (Positive Supply Only)
Application Hints
DRIVING THE MM5262 WITH THE DS0026 CLOCK DRIVER The clock signals for the MM5262 have three requirements which have the potential of generating problems for the user. These requirements, high speed, large voltage swing and large capacitive loads, combine to provide ample opportunity for inductive ringing on clock lines, coupling clock signals to other clocks and / or inputs and outputs and generating noise on the power supplies. All of these problems have the potential of causing the memory system to malfunction. Recognizing the source and potential of these problems early in the design of a memory system is the most critical step. The object here is to point out the source of these problems and give a quantitative feel for their magnitude.
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DS0026
Application Hints
(Continued)
Line ringing comes from the fact that at a high enough frequency any line must be considered as a transmission line with distributed inductance and capacitance. To see how much ringing can be tolerated we must examine the clock voltage specification. Figure 3 shows the clock specification, in diagram form, with idealized ringing sketched in. The ringing of the clock about the VSS level is particularly critical. If the VSS - 1 VOH is not maintained, at all times, the information stored in the memory could be altered. Referring to Figure 1, if the threshold voltage of a transistor were -1.3V, the clock going to VSS - 1 would mean that all the devices, whose gates are tied to that clock, would be only 300 mV from turning on. The internal circuitry needs this noise margin and from the functional description of the RAM it is easy to see that turning a clock on at the wrong time can have disastrous results.
are more expensive than two sided boards. The user must make the decision as to the necessity of multilayer boards. Suffice it to say here, that reliable memory boards can be designed using two sided printed circuit boards.
FIGURE 4. Clock Waveforms (Voltage and Current) Because of the amount of current that the clock driver must supply to its capacitive load, the distribution of power to the clock driver must be considered. Figure 4 gives the idealized voltage and current waveforms for a clock driver driving a 1000 pF capacitor with 20 ns rise and fall time. As can be seen the current is significant. This current flows in the VDD and VSS power lines. Any significant inductance in the lines will produce large voltage transients on the power supplies. A bypass capacitor, as close as possible to the clock driver, is helpful in minimizing this problem. This bypass is most effective when connected between the VSS and VDD supplies. The size of the bypass capacitor depends on the amount of capacitance being driven. Using a low inductance capacitor, such as a ceramic or silver mica, is most effective. Another helpful technique is to run the VDD and VSS lines, to the clock driver, adjacent to each other. This tends to reduce the lines inductance and therefore the magnitude of the voltage transients. While discussing the clock driver, it should be pointed out that the DS0026 is a relatively low input impedance device. It is possible to couple current noise into the input without seeing a significant voltage. Since the noise is difficult to detect with an oscilloscope it is often overlooked.
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DS0026
Application Hints
(Continued)
Lastly, the clock lines must be considered as noise generators. Figure 5 shows a clock coupled through a parasitic coupling capacitor, CC, to eight data input lines being driven by a 7404. A parasitic lumped line inductance, L, is also shown. Let us assume, for the sake of argument, that CC is 1 pF and that the rise time of the clock is high enough to completely isolate the clock transient from the 7404 because of the inductance, L.
This has been a hypothetical example to emphasize that with 20V low rise / fall time transitions, parasitic elements can not be neglected. In this example, 1 pF of parasitic capacitance could cause system malfunction, because a 7404 without a pull up resistor has typically only 0.3V of noise margin in the "1" state at 25°C. Of course it is stretching things to assume that the inductance, L, completely isolates the clock transient from the 7404. However, it does point out the need to minimize inductance in input / output as well as clock lines. The output is current, so it is more meaningful to examine the current that is coupled through a 1 pF parasitic capacitance. The current would be:
FIGURE 5. Clock Coupling With a clock transition of 20V the magnitude of the voltage generated across CL is:
This exceeds the total output current swing so it is obviously significant. Clock coupling to inputs and outputs can be minimized by using multilayer printed circuit boards, as mentioned previously, physically isolating clock lines and / or running clock lines at right angles to input / output lines. All of these techniques tend to minimize parasitic coupling capacitance from the clocks to the signals in question. In considering clock coupling it is also important to have a detailed knowledge of the functional characteristics of the device being used. As an example, for the MM5262, coupling noise from the 2 clock to the address lines is of no particular consequence. On the other hand the address inputs will be sensitive to noise coupled from 1 clock.
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DS0026
Physical Dimensions
inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N) Order Number DS0026CN NS Package Number N08E
8-Lead Small Outline Molded package (M) NS Package Number M08A
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DS0026 Dual High-Speed MOS Driver
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead Mini SOIC Package (MM) NS Package Number MU08A
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.