COP87L88EB/COP87L89EB 8-Bit Time Programmable (OTP) Microcontroller wi
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COP87L88EB/COP87L89EB 8-Bit Time Programmable (OTP) Microcontroller with Interface, UART
COP87L88EB/COP87L89EB 8-Bit Time Programmable (OTP) Microcontroller with Interface, UART
General Description
COP87L88EB/COP87L89EB members COP8microcontroller feature family, which uses 8-bit core architecture. They software compatible mask COP888EB product family. devices designed perform complex embedded control applications such those found Automotive Control Applications, while providing control/diagnostic communications interface. devices comply with basic specification 2.0B (Passive). They fully static devices fabricated using National's double metal silicon gate microCMOS technology. Efficient throughput achieved through regular efficient instruction operating maximum instruction rate. MICROWIRE/PLUS Multi-input Wake Software Trap interface interrupts) UART Inputs) Versatile easy instruction 8-bit stacker pointer (SP) (Stack RAM) 8-bit RegisterR Indirect Memory Pointers
Fully Static CMOS
current drain (typically power saving modes: HALT, IDLE Single supply operation: 4.5V 5.5V Temperature range: -40°C +85°C
Features
interface, with Software Power save mode 8-bit Converter with channels Fully buffered UART Multi-input wake (MIWU) both Port Compatible Master/Slave Interface 8096 bytes on-board EPROM with security feature bytes on-board
Development Support
Emulation device COP888EB Real time emulation full program debug offered MetaLink Development System
Basic Functional Description
serial interface block described specification part 2.0B (Passive) Interface rates 250k bit/s supported utilizing standard message identifiers Programmable double buffered UART 8-bit, channel, 1-LSB Resolution, with improved Source Impedance improved channel channel cross talk immunity Multi-Input-Wake-Up (MIWU) edge selectable wake-up interrupt capability input port interface (Port Port I/F); supports Wake-Up capability SPI, UART, Port 8-bit bi-directional port Port 8-bit Output port with high current drive capability Port 8-bit bidirectional Port 8-bit bidirectional Port 8-bit bidirectional port, including alternate functions for: MICROWIREInput Output Timer Input Output (Depending mode selected) External Interrupt input WATCHDOG Output Port 8-bit input port combining either digital input, eight input channels
Additional Peripheral Features
Idle timer (programmable) 16-bit timer, with 16-bit registers supporting Processor independent mode External Event counter mode Input capture mode WATCHDOGand Clock Monitor MICROWIRE/PLUSserial
Features
Memory mapped Software selectable options (TRI-STATE outputs, Push pull outputs, Weak pull input, High impedance input) Schmitt trigger inputs Port Packages: PLCC with pins; PLCC with pins
CPU/Instruction Features
instruction cycle time Fourteen multi-sourced vectored interrupts servicing External interrupt Idle Timer Timers Interrupts)
TRI-STATE registered trademark National Semiconductor Corporation. COP8TM, MICROWIRE/PLUSTM, WATCHDOGand MICROWIREare trademarks National Semiconductor Corporation. iceMASTERis trademark MetaLink Corporation.
2000 National Semiconductor Corporation
DS012871
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Basic Functional Description
(Continued) Port 8-bit bidirectional port, including alternate functions for: UART Transmit/Receive Multi-input-wake (MIWU pins) Port 8-bit port, with following alternate function Interface MIWU Interface Wake-up (MSB) Timer Input Output (Depending mode selected) Port 8-bit bidirectional Slave Select Expander 16-bit multi-function Timer counters plus supporting registers (I/P Capture, Event Counting) Idle timer Provides basic time-base counter, (with interrupt) automatic wake from IDLE mode programmable
MICROWIRE/PLUS MICROWIRE serial peripheral interface, supporting both Master Slave operation HALT IDLE Software programmable current modes HALT Processor stopped, Minimum current IDLE Processor semi-active more than power saving kbytes bytes board static Master/Slave interface includes bytes Transmit bytes Receive FIFO Buffers. Operates Bit/S board programmable WATCHDOG CLOCK Monitor
Applications
Automobile Body Control Comfort System Integrated Driver Informaiton Systems Steering Wheel Control Radio Control Panel Sensor/Actuator Applications Automotive Industrial Control
Block Diagram
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FIGURE Block Diagram
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Connection Diagrams
Plastic Chip Carrier
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View Order Number COP87L88EB-XE Plastic Chip Package Number V44A Plastic Leaded Chip Carrier
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Note: Crystal Oscillator Halt Enable
View Order Number COP87L89EB-XE Plastic Chip Package Number V68A FIGURE Connection Diagrams
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Connection Diagrams
Port ESS0 ESS1 ESS2 MIWU;MISO MIWU;MOSI MIWU;SCK MIWU;SS MIWU;T2A MIWU;T2B MIWU ADCH0 ADCH1 ADCH2 ADCH3 ADCH4 ADCH5 ADCH6 ADCH7 MIWU MIWU;CKX MIWU;TDX MIWU;RDX MIWU MIWU MIWU MIWU Type WDOUT Function
(Continued)
Port CANVREF RESET DVCC VREF
Type
Function ESS3 ESS4 ESS5 ESS6 ESS7
44-Pin PLCC
68-Pin PLCC
TABLE Pinouts 44-Pin 68-Pin Packages 44-Pin PLCC 68-Pin PLCC
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Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage -0.3V +0.3V
Total Current into Pins (Source) Total Current Pins (Sink) Storage Temperature Range
-65°C +150°C
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics
-40°C +85°C Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note HALT Current (Notes IDLE Current (Note Input Levels (VIH, VIL) Reset, Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pull-Up Current Port Input Hysteresis Output Current Levels Outputs Source Sink Transmitter Outputs Source (Tx1) Sink (Tx0) Others Source (Weak Pull-Up) Source (Push-Pull) Sink (Push-Pull) TRI-STATE Leakage Allowable Sink/Source Current Outputs (sink) (Sink) (Note (Source) (Note Other Maximum Input Current without Latchup (Notes Retention Voltage, (Note Input Capacitance Load Capacitance
Note Maxiumum rate voltage change must
Conditions Peak-to-Peak 5.5V, 5.5V, 5.5V,
Units
0.8VCC 0.2VCC 0.7VCC 0.2VCC 5.5V 5.5V, (Note 0.05VCC
-250
4.5V, 3.3V 4.5V, 1.0V 4.5V, -0.1V 4.5V, 0.6V 4.5V, 0.1V 4.5V, 0.6V 4.5V, 2.7V 4.5V, 3.3V 4.5V, 0.4V 5.5V
-0.4 -1.5 -0.4 -110 +5.0
Room Temp Rise Fall Time (Note
0.5V/ms
1000
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Electrical Characteristics
(Continued)
Note Supply current measured after running 2000 cycles with square wave input, open, inputs GND, outputs open. Note HALT mode will stop from oscillating Crystal configurations. Halt test conditions: inputs tied VCC; Port I/Os configured outputs programmed low; outputs programmed high. Parameter refers HALT mode entered setting Port data register. Part will pull during HALT crystal clock mode. Both main comparator Wakeup comparator need disabled. Note HALT IDLE current specifications assume block comparators disabled. Note Pins RESET designed with high voltage input network. These pins allow input voltages greater than pins will have sink current when biased voltages greater than (the pins have source current when biased voltage below VCC). effective resistance (typical). These pins will latch voltage pins must limited less than 14V. Note Condition parameter valid only part HALT mode. Note Parameter characterized tested.
Electrical Characteristics
-40°C +85°C Parameter Instruction Cycle Time (tc) Crystal/Resonator Inputs tSETUP tHOLD Output Propagation Delay (tPD1, tPD0) (Note others MICROWIRE Setup Time (tUWS) (Note Hold Time (tUWH) (Note Output Delay (tUPD) Input Pulse Width Interrupt High Time Interrupt Time Timer High Time Timer Time Reset Pulse Width (Note 4.5V 4.5V 4.5V 4.5V 4.5V Conditions Units
Instruction Cycle Time maximum speed achievable with interface function crystal frequency, message length software overhead. device support speed Mbit/S with oscillator byte messages. speed refers rate which protocol data bits transferred bus. Longer messages require slower speeds time required software intervention between data bytes. device will support maximum 125k bits/s with eight byte messages oscillator. device testing purpose parameters, will tested 0.5*VCC. Note output propagation delay referenced instruction cycle where output change occurs. Note Parameter tested.
On-Chip Voltage Reference
-40°C +85°C Parameter Reference Voltage VREF Reference Supply Current, Conditions IOUT IOUT Load) (Note 0.5VCC -0.12 0.5VCC +0.12 Units
Note Reference supply supplied information purposes only, tested.
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Comparator Characteristics
4.8V 5.2V, -40°C +85°C Parameter Differential Input Voltage Input Offset Voltage Input Common Mode Voltage Range Input Hysteresis 1.5V -1.5V Conditions Units
-1.5
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FIGURE MICROWIRE/PLUS Timing Diagram
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FIGURE Timing Diagram
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Converter Specifications
(4.5V 5.5V) (VSS 0.050V) Input (VCC 0.050V) Parameter Resolution Absolute Accuracy Non-Linearity Deviation from Best Straight Line Differential Non-Linearity Common Mode Input Range (Note Common Mode Error Channel Leakage Current Channel Leakage Current Clock Frequency (Note Conversion Time (Note Internal Reference Resistance Turn-On Time (Note
Note Conversion Time includes sample hold time. Note Prescaler description. Note VIN(-) VIN(+) digital output code will 0000 0000. on-chip doides ties each analog input. diodes will forward conduct analog input voltages below ground above supply. careful, during testing levels (4.5V), high level analog inputs (5V) cause this input diode conduct especially elevated temperatures, cause errors analog inputs near full-scale. spec allows forward bias either diode. This means that long analog does exceed supply voltage more than output code will correct. achieve absolute input voltage range will therefore require minimum supply voltage 4.950 over temperature variations, initial tolerance loading. Note Time internal reference resistance turn after coming Halt Idle Mode.
Conditions VREF
Units Bits Clock Cycles
1.67
Description
power supply pins. clock input. clock come from crystal oscillator conjunction with CKO). Oscillator Description section. RESET master reset input. Reset Description section. device contains seven bidirectional 8-bit ports where each individual independently configured input (Schmitt trigger inputs ports), output TRI-STATE under program control. Three data memory address locations allocated each these ports. Each port associated 8-bit memory mapped registers, CONFIGURATION register output DATA register. memory mapped address also reserved input pins each port. (See memory various addresses associated with ports.) Figure shows port configurations device. DATA CONFIGURATION registers allow each port individually configured under software control shown below: Configuration Register Data Register Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull Output Port Set-Up
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FIGURE Port Configurations Port following alternate features: MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU Port 8-bit port with pins (G0-G5), input (G6), dedicated output (G7). Pins G0-G6 have Schmitt Triggers their inputs. serves dedicated output clock output. There registers associated with Port, data register configuration register. Therefore, each bits (G0-G5) individually configured under software control.
Port 8-bit ports, they support Multi-Input Wake-up (MIWU) eight pins. L-pins M-pins have Schmitt triggers inputs. Port only have interrupt vector.
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Description
(Continued)
Since input only dedicated clock output associated bits data configuration registers used special purpose functions outlined below. Reading data bits will return zeroes. Note that chip will placed HALT mode wirting ''1" Port Data Register. Similarly chip will placed IDLE mode writing Port Data Register. Writing Port Configuration Register enables MICROWIRE/PLUS operate with alternate phase clock Config. Reg. CLKDLY Alternate Data Reg. HALT IDLE
Port following alternate functions: Multi-input Wakeup MISO Multi-input Wakeup MOSI Multi-input Wakeup Multi-input Wakeup Multi-input Wakeup
Port following alternate features: INTR (External Interrupt Input) Dedicated WATCHDOG output (Timer Capture Input) (Timer I/O) (MICROWIRE Serial Data Output) (MICROWIRE Serial Clock) (MICROWIRE Serial Data Input) Port following dedicated function: Oscillator dedicated output Port bidirectional I/O, configured software Hi-Z input, weak pull-up, push-pull output. These pins used general purpose input/output pins selected altlernate functions. Port pins have optional alternate functions. Each (M0-M5) been assigned alternate data, configuration, wakeup source. respective alternate function selected content associated bits configuration and/or data register ignored. alternate wakeup source selected input level respective will ignored purpose triggering wakeup event, however will still possible read that accessing input register. (Serial Peripheral Interface) block, example, uses four Port pins automatically reconfigure MISO (Master Input, Slave Output), MOSI (Master Output, Slave Input), (Serial Clock) SlaveSelect pins inputs outputs, depending whether interface been configured Master Slave. When interface disabled those pins available general purpose pins configurable user software writing associated data configuration bits. interface device makes Port alternate wake-ups, trigger wakeup such condition been detected CAN's dedicated receive pins.
Multi-input Wakeup Multi-input Wakeup Multi-input Wakeup Ports general-purpose, bidirectional ports. device package that Port fewer than eight pins, contains unbonded, floating pads internally chip. these types devices, software should write configuration register bits corresponding non-existent port pins. This configures port bits outputs, thereby reducing leakage current device. Port 8-bit wide port with alternate function capability used extending slave select lines interface. expander block provides mutually exclusive slave select extension signals (ESS0 ESS7 according state line specific contents shift register. These slave select extension lines routed Port pins enabling alternate function port PORTNX register. enabled, internal signal ESSx line causes ports state change exactly like change PORTND register. user's responsibility switch port output when enabling alternate function.
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Description
ESS0 ESS1 ESS2 ESS3 ESS4 ESS5 ESS6 ESS7
(Continued)
Port following alternate functions:
ALTERNATE PORT FUNCTIONS Many general-purpose pins have alternate functions. software program each used either general-purpose specific function. chip hardware determines which pins have alternate functions, what those functions are. This section lists alternate functions available each pins. Port 8-bit output port that preset high when RESET goes low. user more port outputs (except together order higher drive.
Note: Care must exercised with operation. RESET, external loads this must ensure that output voltages stay above prevent chip from entering special modes. Also keep external loading 1000
pins: on-chip interface this device five dedicated pins with following features: VREF On-chip reference voltage with value VCC/2 receive data input pin. receive data input pin. transmit data output pin. This TRI-STATE mode with TXEN0 control register. transmit data output pin. This TRI-STATE mode with TXEN1 control register.
Port 8-bit Hi-Z input port, also provides analog inputs converter. unterminated, Port pins will draw power only when addressed.
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Functional Description
architecture device utilizes modified Harvard architecture. With Harvard architecture, control store program memory (ROM) separated from data store memory (RAM). Both have their separate addressing space with separate address buses. architecture, though based Harvard architecture, permits transfer data from RAM. REGISTERS 8-bit addition, subtraction, logical shift operation instruction (tc) cycle time. There five registers: 8-bit Accumulator Register 15-bit Program Counter Register upper bits program counter (PC) lower bits program counter (PC) 8-bit address pointer, which optionally post auto incremented decremented. 8-bit alternate address pointer, which optionally post auto incremented decremented. 8-bit stack pointer, which points subroutine/ interrupt stack RAM). initialized address with reset. registers memory mapped with exception Accumulator Program Counter (PC). PROGRAM MEMORY Program memory device consists kbytes EPROM. These bytes hold program instructions constant data (data tables LAID instruction, jump vectors instruction interrupt vectors instruction). program memory addressed 15-bit program counter (PC). interrupts device vector program memory location Hex. device configured inhibit external reads program memory. This done programming Security Byte. SECURITY FEATURE program memory array associate Security Byte that located outside program address range. This byte addressed only from programming mode programmer tool. Security optional feature only asserted after memory array been programmed verified. secured part will read 00(hex) programmer. part will fail Blank Check will fail Verify operations. Read operation will fill programmer's memory with 00(hex). Security byte itself always readable with value 00(hex) unsecure FF(hex) secure. DATA MEMORY data memory address space includes on-chip data registers, registers (Configuration, Data Pin), control registers, MICROWIRE/PLUS shift register, various registers, counters associated with timers (with exception IDLE timer). Data memory addressed directly instruction indirectly pointers. device bytes RAM. Sixteen bytes mapped "registers" addresses Hex. These registers loaded immediately, also decremented
tested with DRSZ (decrement register skip zero) instruction. memory pointer registers memory mapped into this space address locations respectively, with other registers (other than reserved register 0FF) being available general usage. instruction permits memory set, reset tested. registers (except memory mapped; therefore bits register bits directly individually set, reset tested. accumulator bits also directly individually tested.
Note: contents undefined upon power-up.
RESET RESET input when pulled initializes microcontroller. Initialization will occur whenever RESET input pulled low. Upon initialization, data configuration registers Ports cleared, resulting these Ports being initialized TRI-STATE mode. Port initialized high with RESET. CNTRL, INCTRL control registers cleared. Multi-Input Wakeup registers WKEN, WKEDG, WKPND cleared. Stack Pointer, initialized Hex. following initializations occur with RESET: SPI: SPICNTRL: Cleared SPISTAT: Cleared STBE Bit: T1CNTRL T2CNTRL: Cleared ITMR: Cleared IDLE timer period reset Instr. ENAD: Cleared ADDSLT: Random SIOR: Unaffected after RESET with power already applied. Random after RESET power Port TRI-STATE Port TRI-STATE Port HIGH CLEARED PSW, CNTRL ICNTRL registers: CLEARED Accumulator Timer RANDOM after RESET with power already applied RANDOM after RESET power-on (Stack Pointer): Loaded with Pointers: UNAFFECTED after RESET with power already applied RANDOM after RESET power-up RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET power-up CAN: Interface comes external reset "error-active" state waits until user's software sets either both TXEN0, TXEN1 bits "1". After that, device will start transmission reception frame util eleven consecutive "recessive" (undriven) bits have been received. This done ensure that output drivers enamble during active message bus. CSCAL, CTIM, TCNTL, TEC, REC: CLEARED
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Functional Description
RID, RIDL, TID, TDLC: RANDOM
(Continued)
Oscillator Circuits
chip driven clock input input which between MHz. output clock input frequency divided produce instruction cycle clock (1/tc).
RTSTAT: CLEARED with exception which device comes reset with both WATCHDOG logic Clock Monitor detector armed, with WATCHDOG service window bits Clock Monitor set. WATCHDOG Clock Monitor circuits inhibited during reset. WATCHDOG service window bits being initialized high default maximum WATCHDOG service window clock cycles. Clock Monitor being initialized high will cause Clock Monitor being initialized high will cause Clock Monitor error following reset clock reached minimum specified frequency termination reset. Clock Monitor error will cause active error output This error output will continue until tc-32 clock cycles following clock frequency reaching minimum specified value, which time output will enter TRI-STATE mode. RESET signal goes directly HALT latch restart halted chip. When using external reset, external network shown Figure should used ensure that RESET held until power supply chip stabilizes. Under circumstances should RESET allowed float. WATCHDOG:
Figure shows Crystal diagram.
CRYSTAL OSCILLATOR connected make closed loop crystal resonator) controlled oscillator.
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FIGURE Crystal Oscillator Diagram
Table shows component values required various standard crystal values.
TABLE Crystal Oscillator Configuration, 25°C (pF) (pF) 30-36 30-36 100-150 Freq. (MHz) 0.455 Conditions
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Power Supply Rise Time
FIGURE Recommended Reset Circuit
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Control Registers
CNTRL Register (Address X'00EE) Timer1 MICROWIRE/PLUS control register contains following bits: Select MICROWIRE/PLUS clock divide IEDG MSEL T1C0 T1C1 T1C2 T1C3 External interrupt edge polarity select Rising edge, Falling edge) Selects MICROWIRE/PLUS signals respectively Timer Start/Stop control timer Timer Underflow Interrupt Pending Flag timer mode Timer mode control Timer mode control Timer mode control T1C3 T1C2 T1C1 T1C0 MSEL IEDG
Register (Address X'00EF) register contains following select bits: Global interrupt enable (enables interrupts) EXEN Enable external interrupt BUSY MICROWIRE/PLUS busy shifting flag EXPND External interrupt pending T1ENA Timer Interrupt Enable Timer Underflow Input capture edge T1PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow Mode capture edge mode Carry Flag Half Carry Flag T1PNDA T1ENA EXPND BUSY EXEN
Half-Carry also affected instructions that affect Carry flag. (Set Carry) (Reset Carry) instructions will respectively clear both carry flags. addition instructions, ADC, SUBC, instructions affect carry Half Carry flags. ICNTRL Register (Address X'00E8) ICNTRL register contains following bits: T1ENB Timer Interrupt Enable Input capture edge T1PNDB Timer Interrupt Pending Flag capture edge Enable MICROWIRE/PLUS interrupt WPND MICROWIRE/PLUS interrupt pending T0EN Timer Interrupt Enable (Bit toggle) T0PND Timer Interrupt pending LPEN Port Interrupt Enable (Multi-Input Wakeup/Interrupt) could used flag Unused LPEN T0PND T0EN WPND T1PNDB T1ENB
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Control Registers
(Continued)
T2CNTRL Register (Address X'00C6) T2CNTRL register contains following bits: T2ENB T2ENA T2PNDA T2C0 T2C1 T2C2 T2C3 Timer Interrupt Enable Input capture edge Timer Interrupt Enable Timer Underflow Input capture edge Interrupt Pending Flag (Autoreload mode Underflow mode capture edge mode Start/Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode mode control mode control mode control T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB T2PNDB Timer Interrupt Pending Flag capture edge Timer Timer Timer Timer Timer
Timers
device contains very versatile timers (T0, T2). timers associated autoreload/capture registers power containing random data. TIMER (IDLE TIMER) device supports applications that require maintaining real time power with IDLE mode. This IDLE mode support furnished IDLE timer which 16-bit timer. Timer runs continuously fixed rate instruction cycle clock, user cannot read write IDLE Timer which count down timer. Timer supports following functions:
Exit Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description)
Start delay HALT mode
Figure functional block diagram showing structure IDLE Timer associated interrupt logic. Bits through ITMR register selected triggering IDLE Timer interrupt. Each time selected underflows (every 16k, instruction cycles), IDLE Timer interrupt pending T0PND set, thus generating interrupt enabled), Port data register reset, thus causing exit from IDLE mode device that mode. order interrupt generated, IDLE Timer interrupt enable T0EN must set, (Global Interrupt Enable) must also set. T0PND flag T0EN bits ICNTRL register, respectively. interrupt used purpose. Typically, used perform task upon exit from IDLE mode. more information IDLE mode, refer Power Save Modes section.
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FIGURE Functional Block Diagram Idle Timer
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Timers
(Continued)
Idle Timer period selected bits ITMR register Bits ITMR Register reserved should used software flags. TABLE Idle Timer Window Length ITSEL2 ITSEL1 ITSEL0 Idle Timer Period (Instruction Cycles) 4,096 8,192 16,384 32,768 65,536
ITMR register cleared Reset Idle Timer period reset 4,096 instruction cycles. ITMR Register (Address X'0xCF) Reserved ITSEL2 ITSEL1 ITSEL0
time IDLE Timer period changed there possibility generating spurious IDLE Timer interrupt setting T0PND bit. user advised disable IDLE Timer interrupts prior changing value ITSEL bits ITMR Register then clear T0PND before attempting synchronize operation IDLE Timer. TIMER TIMER device three powerful timer/counter blocks, associated features functioning timer block described referring timer block Since three timer blocks, identical, comments equally applicable either three timer blocks. Each timer block consists 16-bit timer, supporting 16-bit autoreload/capture registers, RxB. Each timer block pins associated with TxB. supports required timer block, while input timer block. powerful flexible timer block allows device easily perform timer functions with minimal software overhead. timer block three operating modes: Processor Independent mode, External Event Counter mode, Input Capture mode. control bits TxC3, TxC2, TxC1 allow selection different modes operation. Mode Processor Independent Mode name suggests, this mode allows device generate signal with very minimal user intervention. user only define parameters signal time time). Once begun, timer block will continuously generate signal completely independent microcontroller. user software services timer block only when parameters require updating. this mode timer counts down fixed rate Upon every underflow timer alternately reloaded with contents supporting registers, RxB. very first underflow timer causes timer reload from register RxA. Subsequent underflows cause timer reloaded from registers alternately beginning with register RxB. Timer control bits, TxC3, TxC2 TxC1 timer mode operation.
Figure shows block diagram timer mode.
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FIGURE Timer Mode
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Timers
(Continued)
underflows programmed toggle output pin. underflows also programmed generate interrupts. Underflows from timer alternately latched into pending flags, TxPNDA TxPNDB. user must reset these pending flags under software control. control enable flags, TxENA TxENB, allow interrupts from timer underflow enabled disabled. Setting timer enable flag TxENA will cause interrupt when timer underflow causes register reloaded into timer. Setting timer enable flag TxENB will cause interrupt when timer underflow causes register reloaded into timer. Resetting timer enable flags will disable associated interrupts. Either both timer underflow interrupts enabled. This gives user flexibility interrupting once period either rising falling edge output. Alternatively, user choose interrupt both edges output. Mode External Event Counter Mode This mode quite similar processor independent mode described above. main difference that timer, clocked input signal from pin. timer control bits, TxC3, TxC2 TxC1 allow timer clocked either positive negative edge from pin. Underflows from timer latched into TxPNDA pending flag. Setting TxENA control flag will cause interrupt when timer underflows. this mode input used independent positive edge sensitive interrupt input TxENB control flag set. occurrence positive edge input latched TxPNDB flag.
Figure shows block diagram timer External Event Counter mode.
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FIGURE Timer External Event Counter Mode
Note: output available this mode since being used counter input clock.
Mode Input Capture Mode device precisely measure external frequencies time external events placing timer block, input capture mode. this mode, timer constantly running fixed rate. registers, RxB, capture registers. Each register acts conjunction with pin. register acts conjunction with register acts conjunction with pin. timer value gets copied over into register when trigger event occurs corresponding pin. Control bits, TxC3, TxC2 TxC1, allow trigger events specified either positive negative edge. trigger condition each input specified independently. trigger conditions also programmed generate interrupts. occurrence specified trigger condition pins will respectively latched into pending flags, TxPNDA TxPNDB. control flag TxENA allows interrupt either enabled disabled. Setting TxENA flag enables interrupts generated when selected trigger condition occurs pin. Similarly, flag TxENB controls interrupts from pin. Underflows from timer also programmed generate interrupts. Underflows latched into timer TxC0 pending flag (the TxC0 control serves timer underflow interrupt pending flag Input Capture mode). Consequently, TxC0 control should reset when entering Input Capture mode. timer underflow interrupt enabled with TxENA control flag. When interrupt occurs Input Capture mode, user must check both whether input capture timer underflow both) caused interrupt.
Figure shows block diagram timer Input Capture mode.
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Timers
(Continued)
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FIGURE Timer Input Capture Mode TIMER CONTROL FLAGS timers have identical control structures. control bits their functions summarized below. TxC0 Timer Start/Stop control Modes (Processor Independent Extenral Event Counter), where State, Stop Timer Underflow Interrupt Pending Flag Mode (Input Capture) TxPNDA Timer Interrupt Pending Flag TxPNDB Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag TxENB Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control timer mode control bits (TxC3, TxC2 TxC1) detailed below: TxC3 TxC2 TxC1 Timer Mode MODE (External Event Counter) MODE (External Event Counter) MODE (PWM) Toggle MODE (PWM) Toggle MODE (Capture) Captures: Pos. Edge Pos. Edge MODE (Capture) Captures: Pos. Edge Neg. Edge MODE (Capture) Captures: Neg. Edge Pos. Edge MODE (Capture) Captures: Neg. Edge Neg. Edge Neg. Edge Timer Underflow Neg. Edge Neg. Edge Timer Underflow Pos. Edge Pos. Edge Timer Underflow Neg. Edge Interrupt Source Time Underflow Timer Underflow Autoreload Autoreload Pos. Edge Timer Underflow Interrupt Source Pos. Edge Pos. Edge Autoreload Autoreload Pos. Edge Timer Counts Pos. Edge Neg. Edge
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Power Save Modes
device offer user power save modes operation: HALT IDLE. HALT mode, microcontroller activities stopped. IDLE mode, on-board oscillator circuitry timer active other microcontroller activities stopped. either mode, on-board RAM, registers, states, timers (with exception unaltered. HALT MODE device placed HALT mode writing ''1" HALT flag data bit). microcontroller activities, including clock, timers, stopped. HALT mode, power requirements device minimal applied voltage (VCC) decreased 2.0V) without altering state machine. HALT/IDLE mode: order reduce device overall current consumption HALT/IDLE mode step power save mechanism implemented device: Step Disable main receive comparator. This done resetting both TxEN0 TxEN1 bits CBUS register. Note: These bits should always reset before entering HALT/IDLE mode allow proper resynchronization after exiting HALT/IDLE mode. Step Disable wake-up comparators, this done resetting port-m wakeup enable register (MWKEN) transition will then wake device
Note: both main receive comparator wake-up comparator disabled chip voltage reference also disabled. CANVREF output then High-Z
Schmitt trigger following inverter chip ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications. This Schmitt trigger part oscillator closed loop. start-up time-out from IDLE timer enables clock signals routed rest chip. device mask options associated with HALT mode. first mask option enables HALT mode feature, while second mask option disables HALT mode. With HALT mode enable mask option, device will enter exit HALT mode described above. With HALT disable mask option, device cannot placed HALT mode (writing HALT flag will have effect). following table shows power save modes active transceiver blocks. IDLE MODE device placed IDLE mode writing IDLE flag data bit). this mode, activity, except associated on-board oscillator circuitry, IDLE Timer stopped. power supply requirements microcontroller this mode operation typically around normal power requirement microcontroller. with HALT mode, device returned normal operation with reset, with Multi-Input Wakeup from Port Interface. Alternately, microcontroller resumes normal operation from IDLE mode when thirteenth (representing 4.096 internal clock frequency MHz, IDLE Timer toggles. This toggle condition thirteenth IDLE Timer latched into T0PND pending flag. user option being interrupted with transition thirteenth IDLE Timer interrupt enabled disabled T0EN control bit. Setting T0EN flag enables interrupt vice versa. user enter IDLE mode with Timer interrupt enabled. this case, when T0PND gets set, device will first execute Timer interrupt service routine then return instruciton following "Enter Idle Mode" instruction. Alternatively, user enter IDLE mode with IDLE Timer interrupt disabled. this case, device will resume normal operation with instruction immediately following "Enter IDLE Mode" instruction.
Note: necessary program instructions following both HALT mode IDLE mode instructions. These instructions necessary allow clock resynchronization following HALT IDLE modes.
device supports different ways exiting HALT mode. first method exiting HALT mode with Multi-Input Wakeup feature port. second method exiting HALT mode pulling RESET low. Since crystal ceramic resonator selected oscillator, Wakeup signal allowed start chip running immediately since crystal oscillators ceramic resonators have delayed start time reach full amplitude frequency stability. IDLE timer used generate fixed delay ensure that oscillator indeed stabilized before allowing instruction execution. this case, upon detecting valid Wakeup signal, only oscillator circuitry enabled. IDLE timer loaded with value clocked with instruction cycle clock. clock derived dividing oscillator clock down facStep Step Main-Comp
Wake-Up-Comp
CAN-VREF
VREF VCC/2 VCC/2 VCC/2 High-Z
Multi-Input Wakeup
Multi-Input Wakeup feature used return (wakeup) device from either HALT IDLE modes. Alternately, Multi-Input Wakeup/Interrupt feature also used generate edge selectable external interrupts.
Note: following description both Port port. When document refers registers WKEGD, WKEN WKPND, user will have either (for port) (for port) front register, i.e., LWKEN (Port WKEN), MWKEN (Port WKEN).
Figure Figure show Multi-Input Wakeup logic microcontroller. Multi-Input Wakeup feature utilizes Port. user selects which particular Port combination Port bits) will cause device exit
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Multi-Input Wakeup
(Continued)
HALT IDLE modes. selection done through Reg: WKEN. Reg: WKEN 8-bit read/write register, which contains control every Port bit. Setting particular WKEN enables Wakeup from associated Port pin. user select whether trigger condition selected Port going either positive edge (low high transition) negative edge (high transition). This selection made Reg: WKEDG, which 8-bit control register with assigned each Port pin. Setting control will select trigger condition negative edge that particular Port pin. Resetting selects trigger condition positive edge. Changing edge select entails several steps order avoid
pseudo Wakeup condition result edge change. First, associated WKEN should reset, followed edge select change WKEDG. Next, associated WKPND should cleared, followed associated WKEN being re-enabled. example serve clarify this procedure. Suppose wish change edge select from positive (low going high) negative (high going low) Port where previously been enabled input interrupt. program would follows: RBIT 5,WKEN ;Disable Port wake-up SBIT 5,WKEDG ;Select neg-rising edge RBIT 5,WKPND ;Clear pending SBIT 5,WKEN ;Re-enable
DS012871-13
FIGURE Port Multi-Input Wake-up Logic
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Multi-Input Wakeup
(Continued)
DS012871-14
FIGURE Port Multi-Input Wake-Up Logic Port bits have been used outputs then changed inputs with Multi-Input Wakeup/Interrupt, safety procedure should also followed avoid inherited pseudo wakeup conditions. After selected Port bits have been changed from output input before associated WKEN bits enabled, associated edge select bits WKEDG should reset desired edge selects, followed assoicated WKPND bits being cleared. This same procedure should used following reset, since Port inputs left floating result reset. occurrence selected trigger condition Multi-Input Wakeup latched pending register called WKPND. respective bits WKPND register will occurrence selected trigger edge corresponding Port Port pin. user responsibility clearing these pending flags. Since WKPND pending register occurrence selected wakeup conditions, device will enter HALT mode wakeup both enabled pending. Consequently, user responsibility clearing pending flags before attempting enter HALT mode. WKEN, WKPND WKEDG read/write registers, cleared reset. PORT INTERRUPTS Port provides user with additional eight fully selectable, edge sensitive interrupts which vectored into same service subroutine. interrupt from Port shares logic with wake circuitry. register WKEN allows interrupts from Port individually enabled disabled. register WKEDG specifies trigger condition either positive negative edge. Finally, register WKPND latches pending trigger conditions. (global interrupt enable) enables interrupt function. control flag, LPEN, functions global interrupt enable Port interrupts. Setting LPEN flag will enable interrupts vice versa. separate global pending flag needed since register WKPND adequate. Since Port also used waking device HALT IDLE modes, user elect exit HALT IDLE modes either with without interrupt enabled. elects disable interrupt, then device will restart execution from instruction immediately following instruction that placed microcontroller HALT IDLE modes. other case, device will first execute interrupt service routine then revert normal operation. Wakeup signal will start chip running immediately since crystal oscillators ceramic resonators have finite start time. IDLE Timer (T0) generates fixed delay ensure that oscillator indeed stabilized before allowing device execute instructions. this case, upon detecting valid Wakeup signal, only oscillator circuitry IDLE Timer enabled. IDLE Timer loaded with value clocked from instruction cycle clock. clock derived dividing down oscillator clock factor Schmitt trigger following on-chip inverter ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications. This Schmitt trigger part oscillator closed loop. start-up time-out from IDLE timer enables clock signals routed rest chip. PORT INTERRUPTS Port provides user with seven fully selectable, edge sensitive interrupts which vectored into same service subroutine. interrupt from Port shares logic with wake circuitry. MWKEN register allows interrupts from Port individually enabled disabled. MWKEDG register specifies trigger condition either positive negative edge. MWKPND register latches pending trigger conditions.
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Multi-Input Wakeup
(Continued)
LPEN control flag ICNTRL register functions global interrupt enable Port interrupts. Setting LPEN flag enables interrupts. Note that register must also enable these Port interrupts. global pending flag needed since each corresponding pending flag MWKPND register. Since Port also used exiting device from HALT IDLE mode, user elect exit HALT IDLE mode either with without interrupt enabled. user elects disable interrupt, then device restarts execution from point which stopped (first instruction cycle instruction following enter HALT IDLE mode instruction). other case, device finishes instruction which being executed when part stopped (the (Note instruction following enter HALT IDLE mode instruction), then branches interrupt service routine. device then reverts normal operation.
Note user must place NOPs after enter HALT IDLE mode instruction.
prevent erroneous clearing receive FIFO when entering HALT/IDLE mode, user needs enable MIWU port setting MWKEN register. RECEIVE WAKEUP Receive Wakeup source enabled disabled. There specific enable Wakeup feature. Although wakeup feature pins L0.17 M0.M7 programmed generate interrupt (Port Port interrupt), interrupt generated upon receive wakeup condition. block it's own, dedicated receiver interrupt upon receive buffer full (see Section). Wake-Up: interface programmed wake device from HALT/IDLE mode. This done setting Port wake-up enable register (MWKEN). transition will cause Port wake-up pending (MWKPND) thereby waking device. frame will lost. MWEDG port wake-up edge) register programmed high (high will wake-up first falling edge Rx0). Resetting MWKEN will disable wake-up. following sequence should executed before entering HALT/IDLE mode: RBIT MWKPND ;clear wake-up pending CBUS #0CF ;resetTxEN0 TxEN1 CBUS ;disable main receive ;comparator After device woke-up CBUS bits TxEN0 and/or TxEN1 need allow synchronization enable transmission/reception frames.
Interrupts
device supports vectored interrupt scheme. supports total fourteen interrupt sources. following table lists possible device interrupt sources, their arbitration ranking memory locations reserved interrupt vector each source.
bytes program memory space reserved each interrupt source. interrupt sources except software interrupt maskable. Each maskable interrupts have Enable Pending bit. maskable interrupt active associated enable pending bits set. interrupt active, then processor will interrupted soon ready start executing instruction except above conditions happen during Software Trap service routine. This exception described Software Trap sub-section. interruption process accomplished with INTR instruction (opcode 00), which jammed inside instruction Register replaces opcode about executed. following steps performed every interrupt: (Global Interrupt Enable) reset. address instruction about executed pushed into stack. (Program Counter) branches address 00FF. This procedure takes cycles execute. this time, since other maskable interrupts disabled. user free whatever context switching required saving context machine stack with PUSH instructions. user would then program (Vector Interrupt Select) instruction order branch interrupt service routine highest priority interrupt enabled pending time VIS. Note that this necessarily interrupt that caused branch address location 00FF prior context switching. Thus, interrupt with higher rank than which caused interruption becomes active before decision which interrupt service made VIS, then interrupt with higher rank will override lower ones will acknowledged. lower priority interrupt(s) still pending, however, will cause another interrupt immediately following completion interrupt service routine associated with higher priority interrupt just serviced. This lower priority interrupt will occur immediately following RETI (Return from Interrupt) instruction interrupt service routine just completed. Inside interrupt service routine, associated pending cleared software. RETI (Return from Interrupt) instruction interrupt service routine will (Global Interrupt Enable) bit, allowing processor interrupted again another interrupt active pending. instruction looks active interrupts time executed performs indirect jump beginning service routine with highest rank. addresses different interrupt service routines, called vectors, chosen user stored table starting 01E0 (assuming that located between 00FF 01DF). vectors 15-bit wide therefore occupy locations. vector table must located same 256byte block (0y00 0yFF) except located last address block. this case, table must next block. vector table cannot inserted first 256byte block. vector maskable interrupt with lowest rank located 0yE0 (Hi-Order byte) 0yE1 (Lo-Order byte) forth increasing rank number. vector maskable interrupt with highest rank located 0yFA (Hi-Order byte) 0yFB (Lo-Order byte).
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Interrupts
(Continued)
Software Trap highest rank vector located 0yFE 0yFF. accident, gets executed interrupt active, then (Program Counter) will branch vector located 0yE0-0yE1. WARNING: Default interrupt handle routine must present. minimum, this handler should confirm that cleared (this indicates that interrupt sequence been taken), take care required housekeeping, restore con-
text return. Some sort Warm Restart procedure should implemented. These events occur without error part system designer programmer.
Note: There always possibility interrupt occurring during instruction which attempting reset other interrupt enable bit. occurs when single cycle instruction being used reset interrupt enable bit, interrupt enable will reset interrupt still occur. This because interrupt processing started same time interrupt being reset. avoid this scenario, user should always two, three, four cycle instruction reset interrupt enable bits.
Figure shows Interrupt Block diagram.
TABLE Interrupt Vector Table Arbitration Rank Interrupt Source Software Trap reserved Receive Error (transmit/receive) Transmit Edge MICROWIRE/PLUS Interface Timer UART UART Timer Timer Timer Timer Port Port MIWU Default Interrupt
Note depending location instruction.
Description INTR Instruction RBF, TERR, RERR External BUSY Goes SRBF STBE Idle Timer Underflow receive buffer full transmit buffer empty T2A/Underflow T1A/Underflow Port Edge Port Edge Interrupt
Vector Address (Note 0yFE-0yFF 0yFC-0yFD 0yFA-0yFB 0yF8-0yF9 0yF6-0yF7 0yF4-0yF5 0yF2-0yF3 0yF0-0yF1 0yEE-0yEF 0yEC-0yED 0yEA-0yEB 0yE8-0yE9 0yE6-0yE7 0yE4-0yE5 0yE2-0yE3 0yE0-0yE1
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Interrupts
(Continued)
DS012871-15
FIGURE Interrupt Block Diagram SOFTWARE TRAP Software Trap (ST) special kind non-maskable interrupt which occurs when INTR instruction (used acknowledge interrupts) fetched from placed inside instruction register. This happen when pointing beyond available address space when stack over-popped. When occurs, user re-initialize stack pointer recovery procedure (similar RESET, necessarily containing same initialization procedures) before restarting. occurrence latched into pending bit. affected pending (not accessible user used inhibit other interrupts direct program service routine with instruciton. RPND instruction used clear software interrupt pending bit. This also cleared reset. highest rank among interrupts. Nothing (except another interrupt being serviced. transmit receive registers. user's program check status bytes order information state received transmitted messages. device capability generate interrupt soon byte been transmitted received. Care must taken more than bytes message frame transmitted/received. this case user's program must poll transmit buffer empty (TBE)/receive buffer full (RBF) bits enable their respective interrupts perform data exchange between user data Tx/Rx registers. Fully automatic transmission error supported messages longer than bytes. Messages which longer than bytes have processed software. interface compatible with Specification part without capability receive/transmit extended frames. Extended frames checked acknowledged according specification. maximum speed achievable with interface function crystal frequency, message length software overhead. device support speed Mbit/s with oscillator byte messages. Mbit/s speed refers rate which protocol data bits transferred bus. Longer messages require slower speeds time required software intervention between data bytes. device will support maximum 125k bit/s with eight byte messages oscillator.
Block Description
This device contains serial interface described Specification Rev. part *Patents Pending.
Interface Block
This device supports applications which require speed interface. designed programmed with
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Interface Block
(Continued)
DS012871-16
FIGURE Interface Block Diagram
Functional Block Description Interface
Interface Management Logic (IML) executes CPU's transmission reception commands controls data transfer between CPU, Rx/Tx registers. provides Interface with Rx/Tx data from memory mapped Register Block. also sets resets status information generates interrupts CPU. Stream Processor (BSP) sequencer controlling data stream between Interface Management Logic (parallel data) line (serial data). controls transceive logic with regard reception arbitration, creates error signals according specification Transceive Logic (TCL) state machine which incorporates stuff logic controls output drivers, logic Rx/Tx shift registers. also controls synchronization with clock signal generated BTL.
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Error Management Logic (EML) responsible fault confinement protocol. also responsible changing error counters, setting appropriate error flag bits interrupts changing error status (passive, active off). Cyclic Redundancy Check (CRC) Generator Register Generator consists 15-bit shift register logic required generate checksum destuffed bitstream. informs about result receiver checksum.
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Functional Block Description Interface (Continued)
checksum generated polynomial: Receive/Transmit (Rx/Tx) Registers Rx/Tx registers 8-bit shift registers controlled BSP. They loaded read Interface Management Logic, which holds data transmitted data that received. Time Logic (BTL) time logic divider divides input clock value defined prescaler (CSCAL) timing register (CTIM). resultig time (tcan) computed formula:
user's responsibility ensure that time between setting reload TxD2 longer than length phase segment indicated following equation:
Table shows examples minimum required tLOAD different CSCAL settings based clock frequency MHz. Lower clock speeds require recalculation rate mimimum tLOAD.
TABLE Timing (CKI CSCAL Rate (kbit/s) Minimum tLOAD (µs) 12.5
Where divider value clock prescaler, programmable value phase segment (1.8) programmed value propagation segment (1.8) (located CTIM). Timing Considerations internal architecture interface been optimized allow fast software response times within messages more than data bytes. (Transmit Buffer Empty) last data bytes when internal sample points high.
DS012871-17
FIGURE Rate Generation
Figure illustrates minimum time required tLOAD.
DS012871-18
FIGURE Timing case interrupt driven interface, calculation actual tLOAD time would done follows: ;Interrupt latency PUSH ;2tc PUSH ;3tc ;5tc CANTX: ;20tc this point INT:
;additional time instructions which check ;status prior reloading transmit data ;registers with subsequent data bytes. TXD2,DATA
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Functional Block Description Interface
(Continued)
Interrupt driven programs more time than programs which poll flag, however programs which operate lower baud rates (which more likely sensitive this issue) have more time interrupt response. Output Drivers/Input Comparators output drivers/input comparators physical interface bus. Control bits provided TRI-STATE output drivers. dominant represented data registers recessive represented data registers. TABLE Level Definition Level "dominant" "recessive" drive (GND) TRI-STATE dirve high (VCC) TRI-STATE Data
Register Block register block consists fifteen 8-bit registers which described more detail following paragraphs.
Note: contents receiver related registers RxD1, RxD2, RDLC, RIDH RTSTAT only changed received frame passes acceptance filter Receive Identifier Acceptance Filter (RIAF) accept received messages.
TRANSMIT DATA REGISTER (TXD1) (Address X'00A0) Transmit Data Register contians first data byte transmitted within frame then successive byte numbers (i.e., bytes number 1,3,.,7). TRANSMIT DATA REGISTER (TXD2) (Address X'00A1) Transit Data Register contains second data byte transmitted within frame then successive even byte numbers (i.e., bytes number 2,4,.,8). TRANSMIT DATA LENGTH CODE IDENTIFIER REGISTER (TDLC) (Address X'00A2) TID3 This register read/write. TID3.TIDO Transmit Identifier Bits (lower bits) transmit identifier composed eleven bits total, bits stored bits this register. TDLC3.TDLC0 Transmit Data Length Code These bits determine number data bytes transmitted within frame. specification allows maximum eight data bytes message. TRANSMIT IDENTIFIER HIGH (TID) (Address X'00A3) TRTR This register read/write. TRTR Transmit Remote Frame Request This frame transmitted remote frame request. TID10.TID4 Transmit Identifier Bits (higher bits) Bits TID10.TID4 upper bits transmit identifier. RECEIVER DATA REGISTER (RXD1) (Address X'00A4) Receive Data Register (RXD1) contains first data byte received frame then successive byte numbers (i.e., bytes 3,.7). This register read-only. RECEIVE DATA REGISTER (RXD2) (Address X'00A5) Receive Data Register (RXD2) contains second data byte received frame then successive even byte numbers (i.e., bytes 2,4,.,8). This register read-only. TID10 TID9 TID8 TID7 TID6 TID5 TID4 TID2 TID1 TID0 TDLC3 TDLC2 TCLC1 TDLC0
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Functional Block Description Interface
RID3 This register read only. RID2 RID1 RID0 RDLC3 RDLC2
(Continued)
REGISTER DATA LENGTH CODE IDENTIFIER REGISTER (RIDL) (Address X'00A6) RDLC1 RDLC0
RID3.RID0 Receive Identifier bits (lower four bits) RID3.RID0 bits lower four bits eleven long Receive Identifier. received message that matches upper bits Receive Identifier (RID10.RID4) accepted Receive Identifier Acceptance Filter (RIAF) zero. RDLC3.RDLC0 Receive Data Length Code bits RDLC3.RDLC0 bits determine number data bytes within received frame. RECEIVE IDENTIFIER HIGH (RID) (Address X'00A7) unused RID10 RID9 RID8 RID7 RID6 RID5 RID4
This register read/write. RID10.RID4 Receive Identifier bits (upper bits) RID10.RID4 bits upper bits eleven long Receive Identifier. Receive Identifier Acceptance Filter (RIAF) (see CBUS register) zero, bits received identifier compared with mask bits RID4.RID10. corresponding bits match, message accepted. RIAF one, filter function disabled messages, independent identifier, will accepted. PRESCALER REGISTER (CSCAL) (Address X'00A8) CKS7 This register read/write. CKS7.0 Prescaler divider select. resulting clock value Prescaler clock. TIMING REGISTER (CTIM) (00A9) PPS2 PPS1 PPS0 Reserved Reserved CKS6 CKS5 CKS4 CKS3 CKS2 CKS1 CKS0
This register read/write. PPS2.PPS0 Propagation Segment, bits PPS2.PPS0 bits determine length propagation delay Prescaler clock cycles (PSC) time. (For more detailed discussion propagation delay phase segments, SYNCHRONIZATION.) PS2.PS0 Phase Segment bits PS2.PS0 bits number Prescaler clock cycles time phase segment phase segment PS2.PS0 bits also synchronization Jump Width value equal lesser length PS1/2 (Min: length PS1/2). TABLE Synchronization Jump Width Length Phase Segment tcan tcan tcan tcan tcan tcan tcan tcan tcan tcan tcan tcan tcan tcan tcan tcan Synchronization Jump Width
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Functional Block Description Interface
LENGTH TIME SEGMENTS (See Figure
(Continued)
Synchronization Segment Prescaler clock (PSC) Propagation Segment programmed (PPS) 1,2.,8 length. Phase Segment Phase Segment programmable (PS) 1,2,.,8 long.
Note: (BTL settings high speed; on-chip delay from rx-pins through receive comparator (worst case assumption: clocks delay (devices bus) delay) user needs sample point (2*3 i.e., clocks ensure correct communication under circumstances. With prescaler settings this given (i.e., caution applied). Example: Mbit CTIM b'10000100 (PSS Example kbit CTIM b'01011100 (PPS CSCAL
CONTROL REGISTER (CBUS) (00AA) Reserved RIAF TxEN1 TxEN0 RxREF1 RxREF0 Reserved FMOD
Reserved This reserved should zero. RIAF Receive identifier acceptance filter RIAF zero, bits received identifier compared with mask bits RID4.RID10 corresponding bits match, message accepted. RIAF one, filter function disabled messages independent identifier will accepted. TxEN0, TxEN1 Output Driver Enable TABLE Output Drivers TxEN1 TxEN0 Output Tx0, TRI-STATE, input comparator disabled enabled enabled enabled
synchronization device done following way: output disabled (TxEN1, TxEN0 "0") either TxEN1 TxEN0, both device will start transmission reception frame until eleven consecutive "recessive" bits have been received. Resetting TxEN1 TxEN0 bits will disable output drivers input comparator. other related registers flags will unaffected. recommended that user reset TxEN1 TxEN0 bits before switching device into HALT mode (the receive wakeup will still work) order reduce current consumption assure proper resychronization after exiting HALT mode.
Note: "bus off" condition will also cause TRI-STATE (independent values TxEN1 TxEN0 bits).
RXREF1 Reference voltage applied RXREF0 Reference voltage applied FMOD Fault Confinement Mode select Setting FMOD (default after power reset) will select Standard Fault Confinement mode. this mode device goes from "bus off" "error active" after monitoring 128*11 recessive bits (including idle) bus. This mode been implemented compatibility with existing solutions. Setting FMOD will select Enhanced Fault Confinement mode. this mode device goes from "bus off" "error active" after monitoring "good" messages, indicated reception consecutive "recessive" bits including Frame, whereas standard mode time after recessive bits (e.g., idle).
DS012871-19
FIGURE Acceptance Filter Block-Diagram
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Functional Block Description Interface
TRANSMIT CONTROL/STATUS (TCNTL) (00AB) NS1.NS0 Node Status, i.e., Error Status. TABLE Node Status Node Status bits read only. TERR Transmit Error TERR RERR CEIE
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TXSS
Output Error active Error passive
This automatically when error occurs during transmission frame. TERR programmed generate interrupt setting Error Interrupt Enable (CEIE). This must cleared user's software.
Note: This used messages more than bytes. error occurs during transmission frame with more than data bytes, user's software handle correct reloading data bytes registers retransmission frame. frames with less data bytes interface logic this chip does automatic retransmission. Regardless number data bytes, user's software must reset this CEIE enabled. Otherwise interrupt will generated immediately after return from interrupt service routine.
RERR Receiver Error This automatically when error occurred during reception frame. RERR programmed generate interrupt setting Error Interrupt Enable (CEIE). This cleared user's software. CEIE Error Interrupt Enable user's software, this enables tansmit receive error interrupts. interrupt pending flags TERR RERR. Resetting this with pending error interrupt will inhibit interrupt, will clear cause interrupt (RERR TERR). then without clearing cause interrupt, interrupt will reoccur. Transmit Interrupt Enable user's software, this enables transmit interrupt. (See TXPND.) Resetting this with pending transmit interrupt will inhibit interrupt, will clear cause interrupt. then without clearing cause interrupt, interrupt will reoccur. Receive Interrupt Enable user's software, this enables receive interrupt remote transmission request interrupt (see RBF, RRTR). Resetting this with pending receive interrupt will inhibit interrupt, will clear cause interrupt. then without clearing cause interrupt, interrupt will reoccur. TXSS Transmission Start/Stop This user's software initiate transmission frame. Once this set, transmission pending, indicated TXPND flag being set. reset software cancel pending transmission. Resetting TXSS will only cancel transmission, transmission frame hasn't been started (bus idle), arbitration been lost (receiving) error occurs during transmission. device already started transmission (won arbitration) TXPND TXSS flags will stay until transmission completed, even user's software written zero TXSS bit. more data bytes transmitted, care must taken user, that Transmit Data Register(s) have been loaded before TXSS set. TXSS will cleared three conditions only: Successful completion transmitted message; successful cancellation pending transmision; Transition interface bus-off state. Writing zero TXSS will request cancellation pending transmission TXSS will cleared until completion operation. error occurs during transmission frame, logic will check cancellation requests prior restarting transmission. zero been written TXSS, retransmission will canceled. RECEIVE/TRANSMIT STATUS (RTSTAT) (Address X'00AC) TXPND RRTR ROLD RORN
This register read only. Transmit Buffer Empty This soon TxD2 register copied into Rx/Tx shift register, i.e., data byte each pair been transmitted. automatically reset TxD2 register written (the user should write dummy byte TxD2 register when transmitting number bytes zero bytes). programmed generate interrupt setting Trans29 www.national.com
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Functional Block Description Interface
(Continued)
Interrupt Enable (TIE). When servicing interrupt user make sure that gets cleared executing WRITE instruction TxD2 register, otherwise interrupt will generated immediately after return from interrupt service routine. read only. upon reset. also upon completion transmission valid message. TXPND Transmission Pending This soon Transmit Start/Stop (TXSS) user. will stay until frame successfully transmitted, until transmission successfully canceled writing zero Transmission Start/Stop (TXSS), device enters bus-off state. Resetting TXSS will only cancel transmission transmission frame hasn't been started (bus idle) arbitration been lost (receiving). device already started transmission (won arbitration) TXPND flag will stay until transmission completed, even user's software requested cancellation message. error occurs during transmission, requested cancellation occur prior begining retransmission. RRTR Received Remote Transmission Request This when remote transmission request (RTR) received frame set. automatically reset through read RXD1 register. detect RRTR user either poll this flag enable receive interrupt (the reception remote transmission request will also cause interrupt receive interrupt enabled). receive interrupt enabled, user should check RRTR flag service routine order distinguish between RRTR interrupt interrupt. responsibility user clear this reading RXD1 register, before next frame received. ROLD Received Overload Frame This automatically when Overload Frame received bus. automatically reset through read Receive/Transmit Status register. responsibility user clear this reading Receive/Transmit Status register, before next frame received. RORN Receiver Overrun This automatically overrun receive data register, i.e., user's program does maintain RxDn registers when receiving frame. automatically reset through read Receive/Transmit Status register. responsibility user clear this reading Receive/Transmit Status register before next frame received. Received Frame Valid This received frame valid, i.e., after penultimate Frame received. automatically reset through read Receive/Transmit Status register. responsibility user clear this reading receive/ transmit status register (RTSTAT), before next frame received. will cause Receive Interrupt enabled RIE. user should careful read last data byte (RxD1) length messages data bytes) receipt RFV. only indication that last byte message been received. Receive Mode This after data length code message that passes device's acceptance filter been received. automatically reset after CRC-delimiter same frame been received. indicates user's software that arbitration lost that data coming that node. Receive Buffer Full This second data byte received. reset automatically, after RxD1-Register been read software. programmed generate interrupt setting Receive Interrupt Enable (RIE). When servicing interrupt, user make sure that gets cleared executing instruction from RxD1 register, otherwise interrupt will generated immediately after return from interrupt service routine. read only.
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Functional Block Description Interface
TRANSMIT ERROR COUNTER (TEC) (Address X'00AD) TEC7 This register read/write. TEC6 TEC5 TEC4 TEC3 TEC2
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TEC1
TEC0
test purposes identify node status, transmit error counter, 8-bit error counter, mapped into data memory. lower seven bits counter overflow, i.e., TEC7 set, device error passive. CAUTION prevent interference with fault confinement, user must write REC/TEC registers. Both counters automatically updated following specification. RECEIVE ERROR COUNTER (REC) (00AE) ROVL REC6 REC5 REC4 REC3 REC2 REC1 REC0
This register read/write. ROVL receive error counter overflow test purposes identify node status receive error counter, 7-bit error counter, mapped into data memory. counter overflows ROVL indicate that device error passive won't transmit active error frames. ROVL then counter frozen. MESSAGE IDENTIFICATION Transmitted Message user select Transmit Identifier Bits transmit message whigh fulfills CAN2.0, part spec without extended identifier (see note below). Fully automatic retransmission supported messages longer than bytes. Received Messages lower four bits Receive Identifier don't care, i.e., controller will receive messages that that window messages). upper bits defined user Receive Identifier High Register mask groups messages. RIAF set, messages will received.
Note: interface tolerates extended frame format identifier bits gives acknowledgment. error occurs receive error counter will increased, decreased frame valid.
SYNCHRONIZATION DURING OPERATION Resetting TxEN1 TxEN0 bits Control Register will disable output drivers resynchronization bus. other related registers flags will unaffected. synchronization device this case done following way: output disabled (TxEN1, TxEN0 "0") either TxEN1 TxEN0, both device will start transmission reception frame until eleven consecutive "recessive" bits have been received. "bus off" condition will also cause output drivers TRI-STATE (independent status TxEN1 TxEN0). device will switch from "bus off" "error active" mode described under FMOD-bit description (see Control register). This will ensure that device synchronized bus, before starting transmit receive. information synchronization status related registers after external reset refer RESET section. ON-CHIP VOLTAGE REFERENCE on-chip voltage reference ratiometric reference. electrical characteristics voltage reference refer electrical specifications section. ANALOG SWITCHES Analog switches used selecting between VREF between VREF.
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Basic Concepts
following paragraphs provide generic overview basic concepts Controller Area Network (CAN) described Chapter ISO/DIS11519-1. Implementation related issues National Semiconductor device will discussed well. This device will process standard frame format only. Extended frame formats will acknowledged, however data will discarded. this reason description frame formats following section will cover only standard frame format. following section provides some more detail device will handle received extended frames: device's remote identifier acceptance filter (RIAF) "1", extended frame messages will acknowledged. However, data will discarded device will reply remote transmission request received extended frame format. device's RIAF "0", upper received bits extended frame that match device's receive identifier (RID) acceptance filtler bits, stroed device's register. However, device does reply data discarded. device will only acknowledge message. MULTI-MASTER PRIORITY BASED ACCESS protocol message based protocol that allows total 2032 -16) different messages standard format million -16) different messages extended frame format. MULTICAST FRAME TRANSFER ACCEPTANCE FILTERING Every Frame common bus. Each module receives every frame filters frames which required module's task. REMOTE DATA REQUEST master module ability specific called "remote transmission request bit" (RTR) frame. This causes another module, either another master slave, transmit data frame after current frame been completed. SYSTEM FLEXIBILITY Additional modules added existing network without configuration change. These modules either perform completely functions requiring data process existing data perform function. SYSTEM WIDE DATA CONSISTENCY network message oriented, message used like variable which automatically updated controlling processor. module cannot process information send overload frame. device incapable initiating overload frame, will join overload frame initiated another device required specifications. NON-DESTRUCTIVE CONTENTION-BASED ARBITRATION protocol allows several transmitting modules start transmission same time soon they monitor idle. During start transmission every node monitors line detect whether message overwritten message with higher priority. soon
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transmitting module detects another module with higher priority accessing bus, stops transmitting frame switches receive mode. illustration Figure AUTOMATIC RETRANSMISSION FRAMES data remote frame overwritten either higherprioritized data frame, remote frame error frame, transmitting module will automatically retransmit This device will handle automatic retransmission data bytes automatically. Messages with more than data bytes require user's software update transmit registers. ERROR DETECTION ERROR SIGNALING messages checked each node acknowledge they correct. node detects error starts transmission error frame. Switching Defective Nodes There error counters, transmitted data received data, which incremented, depending error type, soon error occurs. either counter goes beyond specific value node goes error state. valid frame causes error counters decrease. device three states with respect error handling:
Error active: error active unit participate communication sends active ("dominant") error flag. Error passive: error passive unit participate communication. However, unit detects error allowed send active error flag. unit sends only passive ("recessive") error flag.
unit that "bus off" output drivers disabled, i.e., does participate activity. (See ERROR MANAGEMENT DETECTION more detailed information.)
Frame Formats
INTRODUCTION There basically different types frames used protocol. data transmission frames are:: data/remote frame control frames are:: error/overload frame
Note: This device cannot send overload frame result being able process information. However, device able recognize overload condition join overload frames initiated other devices.
message being transmitted, i.e., idle, kept "recessive" level. Figure Figure give overview various frame formats. DATA REMOTE FRAME Data frames consist seven fields remote frames consist different fields: Start Frame (SOF) Arbitration field Control field (IDE bit, bit, field) Data field (not remote frame) field field
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Frame Formats
Frame (EOF)
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remote frame data field used requesting data from other (remote) nodes. Figure shows format data frame.
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FIGURE Message Arbitration
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remote frame identical data frame, except that "recessive", there data field. Identifier Extension standard format transmitted "dominant", whereas extended format "recessive" expanded bits. recessive dominant
FIGURE Data Transmission Frames
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Frame Formats
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error frame start anywhere middle frame.
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Intermission Suspend Transmission only error passive nodes.
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overload frame only start frame.
FIGURE Control Frames
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FIGURE Frame Format FRAME CODING Remote Data Frames codes with bit-stuffing every field which holds computable information interface, i.e., Start Frame arbitration field, control field, data field present) field. Error overload frames coded without stuffing. STUFFING After five consecutive bits same value, stuff inverted value inserted transmitter deleted receiver. Destuffed Stream Stuffed Stream 100000x 1000001x 011111x 0111110x CONTROL FIELD control field consists bits. starts with bits reserved future expansion followed four-bit Data Length Code. Receivers must accept possible combinations reserved bits. Until function these re34
START FRAME (SOF) Start Frame indicates beginning data remote frames. consists single "dominant" bit. node only allowed start transmission when idle. nodes have synchronize leading edge (first edge after idle) caused node which starts transmission first. ARBITRATION FIELD arbitration field composed identifier field (Remote Transmission Request) bit. value "dominant" data frame "recessive" remote frame.
Note: {0,1}
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Frame Formats
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served bits defined, transmitter only sends (dominant) bits. first reserved (IDE) actually defined indicate extended frame with Identifier bits "1". chips must tolerate extended frames, even they only understand standard frames, prevent destruction extended frames existing network. Data Length Code indicates number bytes data field. This Data Length Code consists four bits. data field length zero. permissible number data bytes data frame ranges from DATA FIELD Data field consists data transferred within data frame. contain bytes each byte contains bits. remote frame data field. FIELD field consists sequence followed delimiter. sequence derived transmitter from modulo division preceding fields, starting with data field, excluding stuff-bits, generator polynomial: remainder this division sequence transmitted over bus. receiver side module divides fields delimiter, excluding stuff-bits, checks result zero. This will then interpreted valid CRC. After sequence single "recessive" transmitted delimiter. FIELD field bits long contains slot delimiter. slot filled with "recessive" transmitter. This overwritten with "dominant"
every receiver that received correct sequence. second field "recessive" called acknowledge delimiter. consequence acknowledge flag valid frame surrounded "recessive" bits, CRC-delimiter delimiter. FIELD Frame Field closes data remote frame. consists seven "recessive" bits. INTERFRAME SPACE Data remote frames separate from every preceding frame (data, remote, error overload frames) interframe space Figure Figure details. Error overload frames preceded interframe space. They transmitted soon condition occurs. interframe space consists minimum three fields depending error state node. These fields coded follows: intermission fixed form three "recessive" bits. While this field active, node allowed start transmission data remote frame. only action taken signaling overload condition. This means that error this field would interpreted overload condition. Suspend transmission inserted errorpassive nodes that were transmitter last message. This field form eight "recessive" bits. However, overwritten "dominant" start-bit from another error passive node which starts transmission. idle field consists "recessive" bits. length specified depends load.
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FIGURE Interframe Space Nodes Which Error Passive Have Been Receiver Last Frame
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FIGURE Interframe Space Nodes Which Error Passive Have Been Transmitter Last Frame ERROR FRAME Error Frame consists fields: error flag error delimiter. error field built from various error flags different nodes. Therefore, length vary from minimum bits maximum twelve bits depending when module detects error. Whenever error, stuff error, form error, acknowledgment error detected node, this node starts transmission error flag next bit. error detected, transmis35
sion error flag starts following acknowledge delimiter, unless error flag previous error condition already been started. Figure shows local fault module (module leads 12-bit error frame bus. level either "dominant" error-active node "recessive" error-passive node. error active node detecting error, starts transmitting active error flag consisting "dominant" bits. This causes dewww.national.com
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Frame Formats
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struction actual frame bus. other nodes detect error flag either violation rule bitstuffing value fixed field destroyed. consequence other nodes start transmission their error flag. This means, that error sequence which monitored maximum length twelve bits. error passive node detects error transmits "recessive" bits bus. This sequence does destroy mes-
sage sent another node detected other nodes. However, node detecting error transmitter frame other modules will error condition violation fixed stuff rule. Figure shows error passive transmitter transmits passive error frame when detected receivers. After module transmitted active passive error flag waits error delimiter which consists eight "recessive" bits before continuing.
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module error active transmitter detects error module error active receiver with local fault module error active receiver detects stuff error
FIGURE Error Frame Error Active Transmitter
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Frame Formats
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module error active receiver with local fault module error passive transmitter detects error module error passive receiver detects stuff error
FIGURE Error Frame Error Passive Transmitter OVERLOAD FRAME Like error frame, overload frame consists fields: overload flag overload delimiter. fields have same length error frame field: bits overload flag eight bits delimiter. overload frame only sent after frame (EOF) field they destroys fixed form intermission field. ORDER TRANSMISSION frame transmitted starting with Start Frame, sequentially followed remaining fields. every field transmitted first.
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FIGURE Order Transmission within Frame FRAME VALIDATION Frames have different validation point transmitters receivers. frame valid transmitter message, there error until last Frame field. frame valid receiver, there error until including penultimate Frame. FRAME ARBITRATION PRIORITY Except error passive node which transmitted last frame, nodes allowed start transmission frame after intermission, which lead more nodes starting transmission same time. prevent node from destroying another node's frame, monitors during transmission identifier field RTR-bit. soon detects "dominant" while transmitting "recessive" releases bus, immediately stops transmission starts receiving frame. This causes data remote frame destroyed another. Therefore highest priority message with identifier 0x000
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Frame Formats
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0x7EF (including remote data request (RTR) bit) always gets bus. This only valid standard frame format. Note that while specification allows valid standard identifiers only range 0x000 0x7EF, device will allow identifiers 0x7FF. There three more items that should taken into consideration avoid unrecoverable collisions bus:
acknowledgment error detected whenever transmitting node does acknowledgment from other node (i.e., when transmitter does receive "dominant" during frame). device three states with respect error handling: Error active error active unit participate communication sends active ("dominant") error flag.
Within system each message must assigned unique identifier. This prevent errors, module transmit "dominant" data while other transmitting "recessive" data bit. This could happen more modules start transmission frame same time arbitration. Data frames with given identifier non-zero data length code initiated node only. Otherwise, worst case, nodes would count busoff state, errors, they always start transmitting same with different data. Every remote frame should have system-wide data length code (DLC). Otherwise modules starting transmission remote frame same time will overwrite each other's which result errors.
Error passive error passive unit participate communication. However, unit detects error allowed send active error flag. unit sends only passive ("recessive") error flag. device error passive when transmit error counter greater than when receive error counter greater than 127. device becoming error passive sends active error flag. error passive device becomes error active again when both transmit receive error counter less than 128. unit that "bus off" output drivers disabled, i.e., does participate activity. device when transmit error counter greater than 255. device will become error active again ways depending which mode selected user through Fault Confinement Mode select (FMOD) Control Register (CBUS). Setting FMOD (default after power reset) will select Standard Fault Confinement mode. this mode device goes from "bus off" "error active" after monitoring 128*11 recessive bits (including idle) bus. This mode been implemented compatibility reasons with existing solutions. Setting FMOD will select Enhanced Fault Confinement mode. this mode device goes from "bus off" "error active" after monitoring "good" messages, indicated reception consecutive "recessive" bits including Frame. enhanced mode offers advantage that "bus off" device (i.e., device with serious fault) allowed destroy messages until other devices transmit least messages. This guaranteed standard mode, where defective device could seriously impact communication. When device goes from "bus off" "error active", both error counters will have value "0". each module there error counters perform sophisticated error management. receive error counter (REC) bits wide switches device error passive state overflows. transmit error counter (TEC) bits wide. greater than 127, device switched error passive state. soon overflows, device switched bus-off, i.e., does participate activity.
ACCEPTANCE FILTERING Every node perform acceptance filtering identifier data remote frame filter messages which required node. they only data frames which match acceptance filter stored corresponding data buffers. However, every node which bus-off state received correct CRCsequence acknowledges each frame. ERROR MANAGEMENT DETECTION There multiple mechanisms protocol, detect errors inhibit erroneous modules from disabling activities. following errors detected:
Error device that sending also monitors bus. monitored value different from value that sent, error detected. reception "dominant" instead "recessive" during transmission passive error flag, during stuffed stream arbitration field during acknowledge slot, interpreted error. Stuff error stuff error detected, level after consecutive times changed message field that coded according stuffing method. Form Error form error detected, fixed frame (e.g., delimiter, delimiter) does have specified value. receiver "dominant" during last Frame does constitute form error. Error error detected remainder calculation received polynomial non-zero.
Acknowledgment Error
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Frame Formats
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counters modified device's hardware according following rules: TABLE Receive Error Counter Handling Condition receiver detects Error during sending active error flag. receiver detects "dominant" first after sending error flag. After detecting 14th consecutive "dominant" following active error flag overload flag after detecting consecutive "dominant" following passive error flag. After each sequence additional consecutive "dominant" bits. other error condition (stuff, frame, CRC, ACK). valid reception transmission. Receive Error Counter Increment
only device this device transmits message, will acknowledgment. This will detected error message will repeated. When device goes "error passive" detects acknowledge error, counter incremented. Therefore device will from "error passive" "bus off" state such condition.
Increment
Increment
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FIGURE States
Figure shows connection different states according error counters.
Increment Decrement Counter SYNCHRONIZATION Every receiver starts with "hard synchronization" falling edge bit. time consists four segments: Synchronization segment, propagation segment, phase segment phase segment falling edge data signal should synchronization segment. This segment fixed length time quanta. compensate various delays within network, propagation segment used. length programmable from time quanta. Phase segment phase segment used resynchronize during active frame. length these segments from time quanta long. types synchronization supported: Hard synchronization done with falling edge while idle, which then interpreted SOF. restarts internal logic. Soft synchronization used lengthen shorten time while data remote frame received. Whenever falling edge detected propagation segment phase segment segment lengthened specific value, resynchronization jump width (see Figure 30). falling edge lies phase segment shown Figure shortened resynchronization jump width. Only resynchronization allowed during time. sample point lies between phase segments point where received data supposed valid. transmission point lies phase segment start time with synchronization segment.
Note: resynchronization jump width (RJW) automatically determined from programmed value soft resynchronization done during phase segment propagation segment, then will either equal internal clocks (CKI/(1 divider) programmed value whichever less. will never shorter than internal clock. Note: (PS1 settings setting) should always programmed values greater than allow device resynchronization positive negative phase errors bus. programmed one, time could only lengthened never shortened which basically disables half synchronization).
TABLE Transmit Error Counter Handling Condition transmitter detects Error during sending active error flag. After detecting 14th consecutive "dominant" following active error flag overload flag after detecting consecutive "dominant" following passive error flag. After each sequence additional consecutive "dominant" bits. other error condition (stuff, frame, CRC, ACK). valid reception transmission. Transmit Error Counter Increment
Increment
Increment Decrement Counter
Special error handling counter performed following situations: stuff error occurs during arbitration, when transmitted "recessive" stuff received "dorminant" bit. This does lead incrementation TEC.
ACK-error occurs error passive device "dominant" bits detected while sending passive error flag. This does lead incrementation TEC.
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Frame Formats
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Synchronization segment Propagation segment
FIGURE Timing
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FIGURE Resynchronization
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FIGURE Resynchronization
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Detection Illegal Conditions
device detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading underfined gets zeros. opcode software interrupt zero. program fetches instructions from undefined ROM, this will force software interrupt, thus signaling that illegal condition occurred. subroutine stack grows down each call (jump subroutine), interrupt, PUSH, grows each return POP. stack pointer initialized location during reset. Consequently, there more returns than calls, stack pointer will point addresses (which undefined RAM). Undefined from address read 1's, which turn will cause program return address 7FFF Hex. This undefined location instruction fetched (all 0's) from this location will generate software interrupt signaling illegal condition. Thus, chip detect following illegal conditions: Executing from undefined ROM. Over "POP"ing stack having more returns than calls. When software interrupt occurs, user re-initialize stack pointer recovery procedure before restarting (this recovery program probably similar that following reset, might contain same program initialization procedures).
shift register (SIO) with serial data input (SI), serial data output (SO) serial shift clock (SK). Figure shows block diagram MICROWIRE/PLUS logic. shift clock selected from either internal source external source. Operating MICROWIRE/PLUS arrangement with internal clock source called Master mode operation. Similarly, operating MICROWIRE/ PLUS arrangement with external shift clock called Slave mode operation. CNTRL register used configure control MICROWIRE/PLUS mode. MICROWIRE/PLUS, MSEL CNTRL register one. master mode clock rate selected bits, SL1, CNTRL register. Table details different clock rates that selected. MICROWIRE/PLUS OPERATION Setting BUSY register causes MICROWIRE/PLUS start shifting data. gets reset when eight data bits have been shifted. user reset BUSY software allow less than bits shift. enabled, interrupt generated when eight data bits have been shifted. device enter MICROWIRE/PLUS mode either Master Slave. Figure shows COP888 family microcontrollers several peripherals interconnected using MICROWIRE/PLUS arrangements. WARNING: register should only loaded when clock low. Loading register while clock high will result undefined data register. clock normally when shifting. Setting BUSY flag when input clock high MICROWIRE/PLUS slave mode cause current clock shift register narrow. safety, BUSY flag should only when input clock low.
MICROWIRE/PLUS
MICROWIRE/PLUS serial synchronous communications interface. MICROWIRE/PLUS capability enables device interface with National Semiconductor's MICROWIRE peripherals (i.e., converters, display drivers, E2PROMs etc.) with other microcontrollers which support MICROWIRE interface. consists 8-bit serial
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FIGURE MICROWIRE/PLUS Block Diagram
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MICROWIRE/PLUS
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FIGURE MICROWIRE/PLUS Application MICROWIRE/PLUS Master Mode Operation MICROWIRE/PLUS Master mode operation shift clock (SK) generated internally. MICROWIRE Master always initiates data exchanges. MSEL CNTRL register must enable functions onto Port. pins must also selected outputs setting appropriate bits Port configuraiton register. Table summarizes settings required Master Slave mode operation. TABLE MICROWIRE/PLUS Master Mode Clock Selection Alternate Phase Operation device allows either normal clock alternate phase clock shift data register. both modes normally low. normal mode data shifted rising edge clock data shifted falling edge clock. register shifted each falling edge clock normal mode. alternate phase mode register shifted rising edge clock. control flag, SKSEL, allows either normal clock alternate clock selected. Resetting SKSEL causes MICROWIRE/PLUS logic clocked from normal signal. Setting SKSEL flag selects alternate clock. SKSEL mapped into configuration bit. SKSEL flag will power reset condition, selecting normal signal. TABLE MICROWIRE/PLUS Mode Selection MICROWIRE/PLUS Slave Mode Operation MICROWIRE/PLUS Slave mode operation clock generated external source. Setting MSEL CNTRL register enables functions onto Port. must selected input selected output setting resetting appropriate Port configuration register. Table summarizes settings required enter Slave mode operation. user must BUSY flag immediately upon entering Slave mode. This will ensure that data bits sent Master will shifted properly. After eight clock pulses BUSY flag will cleared sequence repeated. (SO) Config. (SK) Config. TRI-STATE TRI-STATE Int. Int. Ext. Ext. MICROWIRE/ PLUS Master MICROWIRE/ PLUS Master MICROWIRE/ PLUS Slave MICROWIRE/ PLUS Slave This table assumes that control flag MSEL set. Fun. Fun. Operation
Where instruction cycle clock
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Serial Peripheral Interface
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FIGURE Transmission Example Serial Peripheral Interface (SPI) used master-slave systems. synchronous bidirectional serial communication interface with data lines MISO MOSI (Master Slave Out, Master Slave In). serial clock slave select (SS) signal always generated Master. interface receives/transmits protocol frames with bytes length within frame, where frame defined time between falling edge rising edge THEORY OPERATION [7:0]) host programmable general purpose signals. SS-Expander programmed with content first MOSI-byte (i.e., content byte [7:0] appears [7:0]) (N-port[7:0]), respectively), programming mode selected. programming mode selected condition MOSI falling edge expander requires setup four conditions user. SESSEN SPICNTL. PORTNX select which bits used expansion. Configure PORTNC register enable desired expansion bits outputs. Have condition (MOSI falling edge SS).
Figure shows block diagram illustrating basic operation circuit. interface, data transmitted/received packets bits length which shifted into/out shift register with active edge shift clock SCK. byte FIFOs, which serve receive transmit buffer, allow maximum message length bits both transmit receive direction without intervention. With intervention, many more bytes received. registers, Control Register (SPICNTL) Status Register (SPISTAT), used control interface internal bus. Several different operation modes, such master slave operation, possible. SS-Expander allows generation signals N-port, which used additional SS-signals (ESS
Loop Back Mode Setting SLOOP enables Loop Back mode, which used test purposes. Loop Back mode selected, FIFO data communicated FIFO Register. slave mode, MISO output internally connected MOSI input. master mode, MOSI output internally connected MISO input.
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FIGURE Loop Back Mode Block Diagram
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Serial Peripheral Interface
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FIGURE Block Diagram
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Serial Peripheral Interface
SPIU Control Register
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TABLE Control (SPICNTL) (0098) SRIE SRIE STIE SESSEN SPIEN SLOOP
SPIMOD[1:0]
Receive Interrupt Enable disable receive interrupt enable receive interrupt
STIE
Transmit buffer Interrupt Enable disable transmit buffer interrupt enable transmit buffer interrupt
SESSEN
Expander (ESS enable detection programming mode disabled, i.e., value MOSI falling edge "don't care". programming mode detection enabled, i.e., condition "MOSI falling edge occurs, -Expander selected bits [7:0] first transmitted byte determine state N-port (ESS [7:0]). [7:0] will positive edge
B[4:3]
SPIMOD[1:0]
operation mode select SPIMOD[1:0] Slave mode, clock input MISO data output MOSI data input slave select input Standard Master mode, clock output (CKI/40) MISO data input MOSI data output slave select output Master mode, different clock frequencies available: fSCK 1/(tc) CKI/10 fSCK 1/(4 CKI/40 fSCK 1/(16 CKI/160
active clock edge select data shifted falling edge shifted rising edge data shifted rising edge shifted falling edge
SPIEN
enable Enables interface alternate functions MISO, MOSI, pins. disable enable SPI, Port MESS signals
SLOOP
loop back mode disable loop back mode enable loop back mode, MISO MOSI internally connected (see Figure
PROGRAMMING EXPANDER Expander enabled setting SESSEN Control Register (SPICNTL), N-port will programmed with content first MOSI-byte (i.e.,
content byte [7:0] appears N-port[7:0] after complete reception first byte), programming mode detected. bytes follow after MOSI byte, data will ignored SPI.
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Serial Peripheral Interface
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programming mode detected control logic, which decodes condition "MOSI falling edge further details, Figure selected N-port bits will after positive edge
Single N-port bits enabled expansion, disabled allow general purpose I/O, respective bits PORTNX register.
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FIGURE Programming Expander
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SESSEN MOSI falling edge programming mode detected N-port alternate functions enabled.
FIGURE Programming Expander
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Status Register
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Slave mode; rising edge active edge. (SPIMOD[1,0] [0,0],
Slave mode; falling edge active edge. (SPIMOD[1,0] [0,0],
FIGURE Slave Mode Communication
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Master mode; rising edge active edge. (SPIMOD[1,0] [1,0],
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Master mode; falling edge active edge. (SPIMOD[1,0] [1,0],
FIGURE Master Mode Communication
TABLE Status Register (SPISTAT) (0099) SRORN SRBNE STBF STBE STFL SESSDET
Status Register read only register.
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Status Register
SRORN
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receiver overrun. This attempt overwrite valid data FIFO interface. (The condition detect this SRWP SRRP read data SRRP attempting write FIFO interface.) This generate receive interrupt receive interrupt enabled (SRIE Note this condition write operation will executed data lost. Note SRORN stays until reset condition. This reset with dummy write SPISTAT register. register read only dummy write does have effect other bits this register.) result SRORN condition, SRWP becomes frozen (i.e., does change until SRORN reset) will store data FIFO. Note With SRRP being still available, user read data FIFO before resetting SRORN bit.
SRBNE
Receive buffer empty This with write FIFO resulting SRWP SRRP (caution rollover!). This reset with read SPIRXD register resulting SRWP equal SRRP.
STBF
This generate receive interrupt enabled with bit. Transmit buffer full This after write operation SPITXD register (from side), which results STRP STWP. gets reset soon STRP gets incremented reading data FIFO.
STBE
transmit buffer empty This after last read from SPITXD register, which results STRP STWP. gets reset soon STWP gets incremented writing data into FIFO. reset.
STFL
Transmit buffer flush This indicates that contents transmit buffer discharged signal becoming high before data transmit buffer could transmitted. This gets signal gets high 1.STRP STWP 2.STRP STWP current byte been completely transmitted from shift register These conditions will reset STRP STWP These virtual pointers cannot viewed. Note: STRP STWP STBE will generate interrupt. This gets reset with write SPITXD register.
SESSDET
SSExpander detection This indicates detection expand condition (MOSI falling edge immediately after N-port been programmed (8th bit, MHz). This reset rising edge expand condition detected. normal communication. Note: master must hold long enough allow device read SESSDET. Otherwise SESSDET information will lost.
unused unused
SYNCHRONIZATION After enabled (SPIEN internal receive transmit shift clock kept disabled until becomes inactive. This includes being active time SPIEN set, i.e., receive/transmit possible until becomes inactive after enabling SPI.
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Status Register
HALT/IDLE MODE
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FIFO FIFO byte first first buffer. FIFO data read from controller reading SPIRXD register. pointer (SRRP) controls controller read location. Data written this register interface. write location controlled SRWP. SRWP incremented after data stored FIFO SRWP never decremented SRWP roll-over etc. circularly linked list. SRRP incremented after data read from FIFO SRRP never decremented SRRP roll-over etc. circularly linked list. Both pointers cleared reset. following bits indicate status FIFO: SRBNE (SRWP SRRP) !SRORN .SRORN (SRWP SRRP) after write from side, reset write SPISTAT. Special conditions: .SRORN set, writes FIFO allowed from side. SRWP frozen. Resetting .SRORN (after set) clears both SRWP SRRP. prevent erroneous clearing Receive FIFO when entering HALT/IDLE mode, user needs enable MIWU port (SS) setting MWKEN register. FIFO FIFO byte first first buffer. Data written FIFO controller executing write instruction SPITXD register. pointer (STWP) controls controller write location. Data read from this register interface. read location controlled STRP. STRP incremented after data read from FIFO STRP never decremented STRP roll-over etc. circularly linked list. STWP incremented after data written FIFO STWP never decremented STWP roll-over etc. circularly linked list. Both pointers cleared reset. following bits indicate status FIFO: STBF (STRP STWP) after write from controller reset ((STRP STWP) STBE) after read from STBE (STRP STWP) after read from SPI. Special conditions: signal becomes high before data last last byte FIFO transmitted both STRP STWP will STFL will set. (STBE will well.)
Note: SRRP, SRWP, STRP STWP registers available user. Their operation description included clarity enhance user's understanding.
device enters HALT/IDLE mode, both FIFOs reset (Flushed). device exiting HALT/IDLE mode, synchronization takes place described above. SPIRXD SPITXD have same state after Reset, SPISTAT bits after HALT/IDLE mode are: SRORN: SRBNE: STBF: STBE: STFL: SESSDET: unchanged (depending MOSI line)
TRANSMISSION START MASTER MODE transmission data Master mode started user controlled signal switched active. will generated Master mode thus data transmitted signal kept high, i.e., must switched generate SCK. Resetting signal Master mode will immediately stop transmission flush transmit FIFO. Thus, user must only reset high (SCE (SCE
FIFO disabled (SPIEN FIFO related pointers reset kept zero until enabled again. Also, Read/Write operation both SPITXD SPIRXD will cause pointers change, SPIEN set, Read operations from RXFIFO Write operation TXFIFO will increment respective Read/Write pointers. SPIRXD Receive Data Register SPIRXD address location "009A". read/write register. This register holds receive data current SRRP location: read operation from this register accumulator will read FIFO SRRP location increment SRRP afterwards. write this register controllers will write FIFO current SRRP location. SRRP changed.
Note: During breakpoint SRRP incremented.
write this register from interface side will write current SRWP location increment SRWP afterwards. SPITXD Transmit Data Register SPITXD address location "009B". read/write register. This register holds transmit data current STWP location: write from controller this register will write STWP location increment STWP afterwards. read from controller this register will read FIFO current STWP location. pointer changed. Writing data into this register will start transmission data master mode.
Note: read modify write instructions should used this register.
Converter
device contains 8-channel, multiplexed input, successive approximation, Analog-to-Digital convertor. device contains AGND/AVCC ADVREF voltage reference. OPERATING MODES convertor supports ratiometric measurements. supports both Single Ended Differential modes operation. Four specific analog channel selection modes supported. These follows: Allow specific channel selected time. convertor performs specific conversion requested stops.
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Reading this register from side will read byte current STRP location afterwards increment STRP.
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Converter
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Channel Pairs
Allow specific channel scanned continuously. other words, user specifies channel convertor scans continuously. arbitrary time user immediately read result last conversion. user must wait only first conversion complete. Allow differential channel pair selected time. convertor performs specific differential conversion requested stops. Allow differential channel pair scanned continuously. other words, user specifies differential channel pair convertor scans continuously. arbitrary time user immediately read result last differential conversion. user must wait only first conversion complete. convertor supported memory mapped registers, result register mode control register. When device reset, mode control register (ENAD) cleared, powered down result register unknown data. Control Register ENAD control register contains bits channel selection, bits prescaler selection, bits mode selection Busy bit. conversion initiated setting ADBSY ENAD control register. result conversion available user result register, ADRSLT, when ADBSY cleared hardware completion conversion. ENAD (address (0xCB)
CHANNEL SELECT ADCH2 ADCH1 ADCH0 MODE SELECT ADMOD1 ADMOD0 PRESCALER SELECT PSC1 PSC0 ADBSY BUSY
MODE SELECT This 2-bit field used select mode operation (single conversion, continuous conversions, differential, single ended) shown following table. Mode Single Ended mode, single conversion Single Ended mode, continuous scan single channel into result register Differential mode, single conversion Differential mode, continuous scan channel pair into result register
PRESCALER SELECT This 2-bit field used select four prescaler clocks converter. following table shows various prescaler options. Convertor Clock Prescaler Clock Select Divide Divide Divide Divide
CHANNEL SELECT This 3-bit field selects eight channels VIN+. mode selection determines VIN- input. Single Ended mode: Differential mode:
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BUSY ADBSY ENAD register used control starting stopping conversion. When ADBSY cleared, prescale logic disabled clock turned off. Setting ADBSY starts clock initiates conversion based mode select value currently ENAD register. Normal completion conversion clears ADBSY turns convertor. ADBSY remains during continuous conversion. user stop continuous conversion writing zero ADBSY bit. user wishes restart conversion which already progress, this accomplished only writing zero ADBSY stop current conversion then writing ADBSY start conversion. This done consecutive instructions. Operation convertor interface works follows. Setting ADBSY control register ENAD initiates conversion. conversion sequence starts beginning write ENAD operation which sets ADBSY, thus powering A/D. first falling edge convertor clock following write operation, sample signal turns seven clock cycles. single conversion mode, conversion complete signal from will generate power down convertor will clear ADBSY ENAD register next instruction cycle boundary. continuous mode, conversion complete signal will restart conversion sequence deselecting convertor clock cycle before starting
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