Data Sheet January 2002 FEATURES 25ns (3.3 volt supply) maximum a

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Data Sheet January 2002 FEATURES 25ns (3.3 volt supply) maximum a

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QCOTSUT8Q512 512K SRAM
Data Sheet January 2002
FEATURES 25ns (3.3 volt supply) maximum address access time Asynchronous operation compatibility with industrystandard 512K SRAMs compatible inputs output levels, three-state bidirectional data Typical radiation performance Total dose: 50krads >100krads(Si), orbit, using Aeroflex UTMC patented shielded package Immune >100 MeV-cm2/mg TH(0.25) MeV-cm 2/mg Saturated Cross Section bit, 1.0E-9 <1E-10 errors/bit-day, Adams geosynchronous heavy Packaging options: 36-lead ceramic flatpack (3.42 grams) 36-lead flatpack shielded (10.77 grams) Standard Microcircuit Drawing 5962-99607 compliant
INTRODUCTION QCOTSUT8Q512 Quantified Commercial Off-theShelf product high-performance CMOS static organized 524,288 words bits. Easy memory expansion provided active Chip Enable (E), active Output Enable (G), three-state drivers. This device power-down feature that reduces power consumption more than when deselected. Writing devicei accomplished taking Chip Enable input Write Enable inputs LOW. Data eight pins (DQ0 through then written into location specified address pins through Reading from device accomplished taking Chip Enable Output Enable while forcing Write Enable HIGH. Under these conditions, contents memory location specified address pins will appear pins. eight input/output pins (DQ0 through placed high impedance state when device deselected HIGH), outputs disabled HIGH), during write operation LOWand LOW).
Clk. Gen.
Pre-Charge Circuit
Select
Memory Array 1024 Rows 512x8 Columns
Circuit Column Select Data Control Gen.
Figure UT8Q512 SRAM Block Diagram
DEVICE OPERATION
UT8Q512 three control inputs called Enable Write Enable Output Enable (G); address inputs, A(18:0); eight bidirectional data lines, DQ(7:0). Device Enable controls device selection, active, standby modes. Asserting enables device, causes rise active value, decodes address inputs select 524,288 words memory. controls read write operations. During read cycle, must asserted enable outputs. Table Device Operation Truth Table Mode 3-state Data 3-state Data Mode Standby Write Read2 Read
Figure 25ns SRAM Pinout (36)
NAMES A(18:0) DQ(7:0) Address Data Input/Output Enable Write Enable Output Enable Power Ground
Notes: defined "don't care" condition. Device active; outputs disabled.
READ CYCLE combination greater than (min) less than (max) defines read cycle. Read access time measured from latter Device Enable, Output Enable, valid address valid data output. SRAM Read Cycle Address Access figure initiated change address inputs while chip enabled with asserted deasserted. Valid data appears data outputs DQ(7:0) after specified AVQV satisfied. Outputs remain active throughout entire cycle. long Device Enable Output Enable active, address inputs change rate equal minimum read cycle time (tAVAV SRAM read Cycle Chip Enable Controlled Access figure initiated going active while remains asserted, remains deasserted, addresses remain stable entire cycle. After specified ETQV satisfied, eight-bit word addressed A(18:0) accessed appears data outputs DQ(7:0). SRAM read Cycle Output Enable Controlled Access figure initiated going active while asserted, deasserted, addresses stable. Read access time tGLQV unless AVQV tETQV have been satisfied.
WRITE CYCLE combination less than (max) less than VIL(max) defines write cycle. state "don't care" write cycle. outputs placed high-impedance state when either greater than (min), when less than (max). Write Cycle Write Enable Controlled Access figure defined write terminated going high, with still active. write pulse width defined WLWH when write initiated ETWH when write initiated Unless outputs have been previously placed highimpedance state byG, user must wait WLQZ before applying data nine bidirectional pins DQ(7:0) avoid contention. Write Cycle Chip Enable Controlled Access figure defined write terminated latter going inactive. write pulse width defined tWLEF when write initiated ETEF when write initiated going active. initiated write, unless outputs have been previously placed high-impedance state
user must wait WLQZ before applying data eight bidirectional pins DQ(7:0) avoid contention. TYPICAL RADIATION HARDNESS Table Typical Radiation Hardness Design Specifications Total Dose Heavy Error Rate2 3.8E-11 krad(Si) nominal Errors/Bit-Day
Notes: SRAM will latchup during radiation exposure under recommended operating conditions. worst case particle environment, Geosynchronous orbit, Aluminum.
ABSOLUTE MAXIMUM RATINGS1 (Referenced SYMBOL TSTG PARAMETER supply voltage Voltage Storage temperature Maximum power dissipation Maximum junction temperature Thermal resistance, junction-to-case3 input current LIMITS -0.5 4.6V -0.5 4.6V +150°C 1.0W +150°C 10°C/W
Notes: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability performance. Maximum junction temperature increased +175°C during burn-in steady-static life. Test MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Positive supply voltage Case temperature range LIMITS 3.6V screening: -55° +125°C screening: -40° +125°C input voltage
ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-55°C +125°C screening -40oC +125oC screening) 3.3V 0.3) SYMBOL VOH1 VOH2 PARAMETER High-level input voltage Low-level input voltage Low-level output voltage Low-level output voltage High-level output voltage High-level output voltage Input capacitance Bidirectional capacitance Input leakage current Three-state output leakage current (CMOS) (CMOS) 8mA, =3.0V 200µA,VDD =3.0V -4mA,VDD =3.0V -200µA,VDD =3.0V 1MHz 1MHz (max) (max) (max) (OP) Short-circuit output current Supply current operating 1MHz Inputs: 0.8V, 2.0V IOUT (max) DD1(OP) Supply current operating @40MHz Inputs: 0.8V, 2.0V IOUT (max) IDD2 (SB) Nominal standby supply current @0MHz Inputs: IOUT (max) 0.5V
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method Measured only initial qualification after process design changes that could affect input/output capacitance. Supplied design limit guaranteed tested. more than output shorted time maximum duration second.
CONDITION
UNIT
0.08 DD-0.10
-55°C 25°C -40oC 25oC +125°C
CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (-55°C +125°C screening -40oC +125oC screening) 3.3V 0.3) SYMBOL tAVAV tAVQV tAXQX tGLQX tGLQV tGHQZ tETQX tETQV tEFQZ Read cycle time Read access time Output hold time G-controlled Output Enable time G-controlled Output Enable time (Read Cycle G-controlled output three-state time E-controlled Output Enable time E-controlled access time E-controlled output three-state time PARAMETER UNIT
Notes: Post-radiation performance guaranteed MIL-STD-883 Method 1019. Functional test. Three-state defined 300mV change from steady-state output voltage (see Figure (enable true) notation refers falling edge immunity does affect read parameters. (enable false) notation refers rising edge immunity does affect read parameters.
High Active Levels
Active High Levels
VLOAD 300mV VLOAD VLOAD 300mV
300mV
300mV
Figure 3-Volt SRAM Loading
tAVAV A(18:0)
DQ(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: (max) (min)
tAXQX Figure SRAM Read Cycle Address Access
A(18:0) ETQV DQ(7:0) tETQX tEFQZ
DATA VALID
Assumptions: (max) (min)
Figure SRAM Read Cycle Chip Enable -Controlled Access
AVQV A(18:0) tGHQZ tGLQX DQ(7:0)
Assumptions: (max) (min)
DATA VALID
tGLQV
Figure SRAM Read Cycle Output Enable-Controlled Access
CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (-55°C +125°C screening -40oC +125oC screening) 3.3V 0.3) SYMBOL tAVAV tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ tWHQX tETEF tDVWH tWHDX2 tWLEF tDVEF tEFDX tAVWH tWHWL1 Write cycle time Device Enable write Address setup time write controlled) Address setup time write controlled) Write pulse width Address hold time write controlled) Address hold time Device Enable controlled) controlled three-state time controlled Output Enable time Device Enable pulse width controlled) Data setup time Data hold time Device Enable controlled write pulse width Data setup time Data hold time Address valid write Write disable time PARAMETER UNIT
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method Functional test performed with outputs disabled high). Three-state defined 300mV change from steady-state output voltage (see Figure
A(18:0) AVAV2 tAVWH ETWH tAVWL Q(7:0) tWLQZ D(7:0)
Assumptions: (max). (min) then Q(8:0) will three-state entire cycle. high AVAV cycle. APPLIED DATA
WHWL tWHAX
WLWH
tWHQX
tDVWH
tWHDX
Figure SRAM Write Cycle Write Enable Controlled Access
tAVAV A(18:0) AVET tETEF tEFAX
AVET tETEF tWLEF
APPLIED DATA
tEFAX
D(7:0)
WLQZ Q(7:0)
DVEF
EFDX
Assumptions Notes: (max). (min) then Q(7:0) will three-state entire cycle. Either scenario above occur. high AVAV cycle.
Figure SRAM Write Cycle Chip Enable Controlled Access
CMOS DD-0.05V ohms LOAD 1.55V 0.5V
50pF Notes: 50pF including scope probe test socket capacitance. Measurement data output occurs high high transition mid-point (i.e., CMOS input DD/2). Input Pulses
Figure Test Loads Input Waveforms
DATA RETENTION MODE
2.0V
Figure Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) Second Data Retention Test) SYMBOL PARAMETER tEFR tR1,3 data retention Data retention current Chip select data retention time Operation recovery time
MINIMUM tAVAV
MAXIMUM -2.0
UNIT
Notes: .2V, other inputs Data retention current 25oC. guaranteed tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) Second Data Retention Test, +125oC screening SYMBOL PARAMETER tEFR2, tR2, data retention Chip select data retention time Operation recovery time
MINIMUM tAVAV
MAXIMUM
UNIT
Notes: Performed (min) (max). other inputs guaranteed tested.
PACKAGING
exposed metalized areas gold plated over electroplated nickel MIL-PRF-38535. electrically connected Lead finishes accordance MIL-PRF-38535. Lead position coplanarity measured. mark vendor option. Total weight approx. 3.42 grams
Figure 36-pin Ceramic FLATPACK
package finishes MIL-PRF-38535. Letter designations cross-reference MIL-STD-1835. leads increase max. limit 0.003 measured center flat, when lead finish (solder) applied. Total weight approx. 10.77
Figure 36-lead flatpack shielded package
ORDERING INFORMATION 512K SRAM:
UT8Q512K
Lead Finish: solder dipped Gold Factory option (gold solder)
Screening: Military Temperature Range flow Prototype flow Extended Industrial Temperature Range Flow (-40o +125o
Package Type: 36-lead flatpack shielded package (bottom brazed) 36-lead flatpack package (bottom brazed)
25ns access time, 3.3V operation
-Aeroflex UTMC Core Part Number
Notes: Lead finish (A,C, must specified. specified when ordering, then part marking will match lead finish will either (solder) (gold). Prototype flow UTMC Manufacturing Flows Document. Tested only. Lead finish GOLD ONLY. Radiation neither tested guaranteed. Military Temperature Range flow UTMC Manufacturing Flows Document. Devices tested -55°C, room temp, +125°C. Radiation neither tested guaranteed. 36LBBFP Shielded Package reduced high orders only. Extended Industrial Temperature Range flow UTMC Manufacturing Flows Document. Devices tested -40°C +125 Radiation neither tested guaranteed. Gold Lead Finish Only.
512K SRAM:
5962 99607
Lead Finish: solder dipped Gold Factory Option (gold solder) Case Outline: 36-lead flatpack shielded package (bottom-brazed) 36-lead ceramic flatpack (bottom-brazed) Class Designator: Class Class
Device Type 25ns access time, 3.3V operation, Mil-Temp 25ns access time, 3.3V operation, Extended Industrial Temp (-40o +125 Drawing Number: 99607 Total Dose: none (10krad)(Si)) (30krad)(Si)) (contact factory) (50krad(Si)) (contact factory) Federal Stock Class Designator: options
Notes: .Lead finish (A,C, must specified. specified when ordering, part marking will match lead finish will either (solder) (gold). .Total dose radiation must specified when ordering. available without radiation hardening.

Data Sheet January 2002 FEATURES 25ns (3.3 volt supply) maximum a

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