LM4543 Codec with National Sound LM4543 audio codec systems which

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LM4543 Codec with National Sound LM4543 audio codec systems which

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LM4543 Codec with National Sound
LM4543 Codec with National Sound
LM4543 audio codec systems which performs analog-intensive function Analog Codec 1.03 architecture. Using 18-Bit converters, LM4543 provides 90dB dynamic range. LM4543 designed specifically provide high quality audio path provide analog functionality audio system. features full duplex stereo A/D's D/A's analog mixer with stereo mono inputs, each which separate gain, attenuation mute control. addition, LM4543 provides National's Sound stereo enhancement technology. LM4543 features AC-Link, synchronous, fixed rate serial connection digital Controller. separation analog digital functions architecture allows system design flexibility increased overall performance.
Specifications
Analog Mixer Dynamic Range Dynamic Range Dynamic Range 95dB (typ) 89dB (typ) 90dB (typ)
Features
Audio Codec compliant Stereo 18-Bit A/D's D/A's with 128X oversampling National's Sound circuitry Power management support Digital Interface compliant
Applications
Desktop Audio Systems Portable Audio Systems Mobile Audio Solutions
Block Diagram
DS100907-1
FIGURE LM4543 Block Diagram
1999 National Semiconductor Corporation
DS100907
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Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage Storage Temperature Input Voltage Susceptibility (Note pins Susceptibility (Note Junction Temperature Soldering Information 6.0V -65°C +150°C -0.3V +0.3V 2500V 1500V 750V 200V 100V 150°C
TQFP Package Vapor Phase sec.) Infrared sec.) AN-450 Surface Mounting their Effects Product Reliability other methods soldering surface mount devices. (typ) VBH48A 74°C/W 215°C 220°C
Operating Ratings
Temperature Range TMIN TMAX Analog Supply Range Digital Supply Range -40°C 85°C 4.2V AVDD 5.5V 3.0V DVDD 5.5V
Electrical Characteristics (Notes following specifications apply AVDD DVDD unless otherwise noted. Limits apply 25°C. reference 1Vrms unless otherwise specified.
Symbol Parameter Conditions LM4543 Typical (Note AVDD DVDD IDDD Analog Supply Range Digital Supply Range Digital Quiescent Power Supply Current Analog Quiescent Power Supply Current Shutdown Current Reference Voltage Power Supply Rejection Ratio Input Line Output, -60dB Input THD+N, A-Weighted -3dB, 1kHz, DVDD DVDD 3.3V IDDA VREF PSRR 2.23 Limit (Note (min) (max) (min) (max) Units (Limits)
Analog Loopthru Mode Dynamic Range (Note Total Harmonic Distortion Line Input Voltage Input with 20dB Gain Input with Gain Xtalk Crosstalk Input Impedance Input Capacitance Interchannel Gain Mismatch Record Gain Amplifier Mixer Section Step Size Mute Attenuation Resolution +12dB -34.5dB Bits Step Size 22.5dB Left Right Left Right 0.01 0.04 0.02 (min) (max) Vrms Vrms Vrms (max) (min)
Analog Input Section
Analog Digital Converters
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Electrical Characteristics (Notes
Symbol Parameter
(Continued)
following specifications apply AVDD DVDD unless otherwise noted. Limits apply 25°C. reference 1Vrms unless otherwise specified. Conditions LM4543 Typical (Note Analog Digital Converters Dynamic Range (Note Frequency Response Digital Analog Converters Resolution Dynamic Range (Note Total Harmonic Distortion Frequency Response Group Delay (Note Band Energy Stop Band Rejection Discrete Tones Step Size Mute Attenuation -46.5dB Output Volume Section 0.30 DVDD 0.40 DVDD 0.50 DVDD 0.20 DVDD Link inputs High impedance Link outputs Link outputs 12.288 81.4 Variation BIT_CLK period from duty cycle 20.8 19.5 SDATA_IN, SDATA_OUT falling edge BIT_CLK Hold time SDATA_IN, SDATA_OUT from falling edge BIT_CLK BIT_CLK, SYNC, SDATA_IN SDATA_OUT BIT_CLK, SYNC, SDATA_IN SDATA_OUT cold reset cold reset 162.8 -60dB Input THD+N, A-Weighted -3dB, f=1kHz, -1dB Bandwidth 0.01 0.03 Bits (min) (max) (max) -60dB Input THD+N, A-Weighted -1dB Bandwidth (min) Limit (Note Units (Limits)
Digital (Note TBCP FSYNC TSETUP THOLD TRISE TFALL TRST_LOW TRST2CLK level input voltage High level input voltage High level output voltage level output voltage Input Leakage Current state Leakage Current Output drive current BIT_CLK frequency BIT_CLK period BIT_CLK high SYNC frequency SYNC period SYNC high pulse width SYNC pulse width Setup Time Hold Time Rise Time Fall Time RESET# active pulse width RESET# inactive BIT_CLK start (max) (min) (min) (max) (max) (max)
Digital Timing Specifications (Note
(max) (min) (min) (max) (max) (min) (min)
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Electrical Characteristics (Notes
Symbol Parameter
(Continued)
following specifications apply AVDD DVDD unless otherwise noted. Limits apply 25°C. reference 1Vrms unless otherwise specified. Conditions LM4543 Typical (Note Digital Timing Specifications (Note TSYNC2CLK TSU2RST TRST2HZ SYNC active high pulse width SYNC inactive BIT_CLK start Setup trailing edge RESET# Rising edge RESET# Hi-Z warm reset warm reset Test Mode Test Mode 162.8 (min) (min) (max) Limit (Note Units (Limits)
Note voltages measured with respect ground pin, unless otherwise specified. Note These specifications guaranteed design characterization; they production tested. Note Absolute Maximum Ratings indicate limits beyond which damage device occur. Operating Ratings indicate conditions which device functional, guarantee specific performance limits. Electrical Characteristics state electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that device within Operating Ratings. Specifications guaranteed parameters where limit given, however, typical value good indication device performance. Note maximum power dissipation must derated elevated temperatures dictated TJMAX, ambient temperature maximum allowable power dissipation PDMAX (TJMAX-TA)/JA number given Absolute Maximum Ratings, whichever lower. LM4543, TJMAX 150°C. typical junction-to-ambient thermal resistance 74°C/W package number VBH48A. Note Human body model, discharged through resistor. Note Machine Model, pF-240 discharged through pins. Note Typicals measured 25°C represent parametric norm. Note Limits guaranteed National's AOQL (Average Outgoing Quality Level).
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Timing Diagrams
Clocks
DS100907-10
Data Setup Hold
DS100907-11
Digital Rise Fall
DS100907-12
Cold Reset
DS100907-13
Warm Reset
DS100907-14
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Typical Application
DS100907-3
FIGURE LM4543 Typical Application Circuit
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Connection Diagram
DS100907-2
View Order Number LM4543VH Package Number VBH48A
Description Analog
Name Functional Description This mono input which gets summed into stereo line output after National Sound block. PC_BEEP level adjusted from -45dB steps, muted, register 0Ah. This mono input which gets summed into stereo line output after National Sound block. PHONE level adjusted from +12dB -34.5dB 1.5dB steps well muted register 0Ch. This line level input routed through Input recorded left ADC. addition, this analog input gets summed into left output stream. amount AUX_L signal mixed left output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 16h. This line level input routed through Input recorded right ADC. addition, this analog input gets summed into right output stream. amount AUX_R signal mixed right output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 16h.
PC_BEEP
PHONE
AUX_L
AUX_R
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Description Analog
Name
(Continued)
(Continued) Functional Description This line level input routed through Input recorded left ADC. addition, this analog input gets summed into left output stream. amount VIDEO_L signal mixed left output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 14h. This line level input routed through Input recorded right ADC. addition, this analog input gets summed into right output stream. amount VIDEO_R signal mixed right output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 14h. This line level input routed through Input recorded left ADC. addition, this analog input gets summed into left output stream. amount CD_L signal mixed left output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 12h. This input used reject common mode signals CD_L CD_R inputs. CD_GND ground point, ground point. This input must AC-coupled source signal's ground. This line level input routed through Input recorded right ADC. addition, this analog input gets summed into right output stream. amount CD_R signal mixed right output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 12h. Either MIC1 MIC2 selected software routed through Input recording. 20dB boost circuit enabled/disabled register 0Eh. Also, amount signal mixed output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 0Eh. Either MIC1 MIC2 selected software routed through Input recording. 20dB boost circuit enabled/disabled register 0Eh. Also, amount signal mixed output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 0Eh. This line level input routed through Input recorded left ADC. addition, this analog input gets summed into left output stream. amount LINE_IN_L signal mixed left output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 10h. This line level input routed through Input recorded right ADC. addition, this analog input gets summed into right output stream. amount LINE_IN_R signal mixed right output stream adjusted from +12dB -34.5dB 1.5dB steps well muted register 10h. This post-mixed output left audio channel. level this output adjusted from -45dB 1.5dB steps well muted register 02h. This post-mixed output right audio channel. level this output adjusted from -45dB 1.5dB steps well muted register 02h. This line level output switched between outputting post-mixed combined left right outputs signal. level this output adjusted from -45dB 1.5dB steps well muted register 06h.
VIDEO_L
VIDEO_R
CD_L
CD_GND
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
LINE_OUT_L LINE_OUT_R
MONO_OUT
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Description
(Continued)
Digital Clocking
Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET# Functional Description 24.576 crystal input. fundamental-mode type crystal. When operating from crystal, resistor must connected across pins 24.576 crystal output. When operating from crystal, resistor must connected across pins This data stream contains both control data audio data. This input sampled LM4543 falling edge BIT_CLK. 12.288 clock which derived (divide two) from 24.576MHz crystal input (XTL_IN). This data stream contains both control data audio data. This output clocked LM4543 rising edge BIT_CLK. 48kHz sync pulse which signifies beginning both SDATA_IN SDATA_OUT serial streams. SYNC must synchronous BIT_CLK. This active signal causes hardware reset which returns control registers their default conditions.
Power Supplies References
Name AVDD AVSS DVDD DVSS VREF VREFOUT AFILT1 AFILT2 25,38 26,42 Analog supply pins. Analog ground pins. Digital supply pins. Digital ground pins. Nominal 2.2V reference output. intended sink source current. Bypassing this should done with short traces maximize performance. Nominal 2.2V reference output. source current used bias microphone. connect external capacitance this pin. This used should left open (NC). However, capacitor ground this permitted will affect performance. This used should left open (NC). However, capacitor ground this permitted will affect performance. These pins used complete National Sound circuit. Connect 0.022µF capacitor between pins 3DN. National Sound turned control register 20h. This fixed-depth type stereo enhance circuit, thus writing register effect. National Sound desired, then these pins should left connect (NC). Functional Description
3DP,3DN
31,32
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Typical Performance Characteristics
Noise Floor Noise Floor Analog Loopthru Noise Floor
DS100907-15
DS100907-16
DS100907-18
Frequency Response
Frequency Response
DS100907-19
DS100907-20
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Register
Name Reset Master Volume Master Volume Mono Mute Mute Mute Mute Mute Mute Mute Mute Mute Mute LPBK 20dB Reserved Phone Volume Volume Line Volume Volume Video Volume Volume Record Select Record Gain Reserved Mute Default 0d50h 8008h 8000h 8008h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 4E53h 4300h
PC_BEEP Volume
General Purpose
Reserved Powerdown Ctrl/Stat
Control fixed depth center)
Vendor Vendor
Vendor Reserved
Vendor Reserved
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Application Information
Link Serial Interface Protocol
DS100907-4
FIGURE Bidirectional Audio Frame
DS100907-6
FIGURE Link Audio Output Frame Link Output Frame audio output frame (output from Controller) contains control data targeted LM4543 control registers stereo DAC. slot, slot contains bits that tell Link interface circuitry LM4543 validity following data slots. audio output frame signaled with high transition SYNC. SYNC synchronous rising edge BIT_CLK. next rising edge BIT_CLK, Controller drives SD_OUT with first slot LM4543 samples SD_OUT falling edge BIT_CLK. Controller will continue outputting SD_OUT stream each successive rising edge BIT_CLK.
DS100907-5
SD_OUT Slot Phase first slot designated Valid Frame bit. this indicates that current data frame contains least slot valid data LM4543 will further sampled next four bits determine which frames fact have valid data. Valid slots signified their respective slot position.
FIGURE Start Audio Output Frame Description Valid Frame Control register address Control register data Left Playback Data Comment Valid Frame Valid slot
Valid slot Valid slot
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Application Information
Description Right Playback Data
(Continued)
Bits 19:4
Description Control Register Write Data Reserved
Comment bits read operation
Comment Valid slot
SD_OUT Slot Control Address Slot used both write LM4543 registers well read back register's current value. Slot (bit signifies whether current control operation read write. BIts through used specify register address read write operation. least significant twelve bits reserved should stuffed with zeros AC'97 controller. Bits 18:12 11:0 Description Read/Write Control Register Reserved Comment Write, Read Identifies Control Register
SD_OUT Slot Playback Left Channel Slot field used transmit data intended left LM4543. unused bits should padded with zeros. LM4543 DAC's have resolution thus will first bits stream. Bits 19:0 Description Audio Data Left Comment unused bits
SD_OUT Slot Control Data Slot used transmit control data LM4543 event that current operation write operation. least significant four bits should stuffed with zeros controller. current operation register read, entire slot, bits through should stuffed with zeros.
SD_OUT Slot Playback Right Channel Slot field used transmit data intended right LM4543. unused bits should padded with zeros. LM4543 DAC's have resolution thus will first bits stream. Bits 19:0 Description Audio Data Right Comment unused bits
SD_OUT Slots 5-12: Reserved these SD_OUT slots they currently used reserved future use.
DS100907-8
FIGURE Link Audio Input Frame Link Input Frame audio input frame (input Digital Controller) contains status data from LM4543 control registers stereo ADC. slot, slot contains bits that tell Digital Controller whether LM4543 ready validity data from certain device subsections. audio input frame signaled with high transition SYNC. SYNC synchronous rising edge BIT_CLK. next rising edge BIT_CLK, LM4543 drives SD_IN with first slot Digital Controller samples SD_IN falling edge BIT_CLK. LM4543 will continue outputting SD_IN stream each successive rising edge BIT_CLK. LM4543 outputs data first, justified format. reserved bits slots stuffed with LM4543. SD_IN Slot Codec Status Bits first SD_IN Slot (bit 15), asserted (=1), indicates that Codec ready. digital controller must probe further which other subsections ready.
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Application Information
(Continued)
Bits
Description Reserved
Comment Stuffed with
SD_IN Slot Record Right Channel This slot contains right sample data. signal digitized selected register subsequently routed through Input recording right ADC. Bits 19:2
DS100907-7
Description Record Right Channel data Reserved
Comment audio sample from right Stuffed with
FIGURE Start Audio Input Frame Description Codec Ready Slot data valid Slot data valid Slot data valid Slot data valid Comment 0=Not Ready, 1=Ready Status Address valid Status Data valid Left Audio Data valid Right Audio Data valid
SD_IN Slots 5-12: Reserved These SD_IN slots they reserved future use. Link Power Mode
DS100907-9
FIGURE Link Powerdown Timing Reset Register (00h) Writing value this register causes register reset which changes registers back their default values. this register read, codec will return value 0D50h indicating that National Sound implemented data supported both ADCs DACs. Master Volume Registers (02h, 06h) These registers allows output levels from LINE_OUT port MONO_OUT port attenuated muted. Each step nominally 1.5dB each output individually muted setting most significant Mute Mx5:Mx0 0000 1111 XXXX XXXX Function attenuation 46.5dB attenuation 46.5dB attenuation mute
SD_IN Slot Status Address slot echoes control register which read requested address echoed initiated read request previous SD_OUT frame, slot Bits 18:12 11:0 Description Reserved Control Register Index Reserved Comment Stuffed with Echo Control Register which data being returned. Stuffed with
SD_IN Slot Status Data slot returns control register data. data returned initiated read request previous SD_OUT frame, slot Bits 19:4 Description Control Register Read Data Reserved Stuffed with Comment
Default: 8000h Beep Register (0Ah) This register controls level PC_BEEP input. PC_BEEP both attenuated muted register 0Ah. Step size nominally 3dB. signal present after attenuation mute block summed into both left right channels. Mute Default: 8000h PV3:0 0000 1111 XXXX Function attenuation 45dB attenuation mute
SD_IN Slot Record Left Channel This slot contains left sample data. signal digitized selected register subsequently routed through Input recording left ADC. Bits 19:2 Description Record Left Channel data Comment audio sample from left
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Application Information
(Continued)
Mute
Gx3:Gx0 1111 0000 XXXX
Function 22.5dB gain gain mute
Mixer Input Volume Registers (Index 18h) These registers control input volume controls including mute. Each volume control which provides from range +12dB gain 34.5dB attenuation. stereo ports, left right levels independently set. Muting given port accomplished setting Setting stereo ports mutes both left right channel. Register additional 20dB boost microphone level input. This enabled setting register Mute Gx4:Gx0 00000 01000 01111 XXXXX Function +12dB gain gain 34.5dB attenuation mute
Default: 8000h General Purpose Register (20h) This register controls many miscellaneous functions implemented LM4543. miscellaneous functions include which allows bypass National Sound circuitry, which enables disables National Sound circuitry, which selects MONO_OUT source, which selects microphone source LPBK which connects output stereo input stereo DAC. LPBK provides digital loopthru path when enabled. LPBK Function path mute, post National Sound Mono output select Mix, select Mic1 Mic2 ADC/DAC loopback
Default: 8008h (mono regs.), 8808h (stereo regs.) Record Select Register (1Ah) This register independently controls source right left channel which will recorded stereo ADC. default value 0000h which corresponds SL2:SL0 SR2:SR0 Left Record Source Video Line Stereo Mono Phone Right Record Source Video Line Stereo Mono Phone
Powerdown Control Status Register (26h) This read/write register used monitor subsystem readiness program LM4543 powerdown states. lower half this register read only with indicated subsection ready. Writing lower bits will have effect. When Link Codec Ready indicator (SDATA_IN slot indicates that Link registers fully operational state. Controller must further probe Powerdown Control Status Register determine exactly which subsections ready. Function Vref's nominal level Analog mixers ready section ready accept data section ready transmit data
supported powerdown modes follows. Function ADC's Input powerdown DAC's powerdown Analog Mixer powerdown (VREF still Analog Mixer powerdown (VREF off) Digital Interface Link) powerdown (external off) Internal disable used
Record (Input) Gain Register (1Ch) This registers controls Record (Input) Gain level stereo input selected Record Select Control Register (1Ah). gain programmed from +22.5dB 1.5dB steps. level left right channel individually controlled. input also muted setting
Reserved Registers (28h 7Ah) write these registers they reserved.
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LM4543 Codec with National Sound
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead TQFP, 1.4mm, JEDEC Order Number LM4543VH Package Number VBH48A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION. used herein: critical component component life support Life support devices systems devices sysdevice system whose failure perform reatems which, intended surgical implant into sonably expected cause failure life support body, support sustain life, whose faildevice system, affect safety effectiveness. perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: 80-530 Email: europe.support@nsc.com Deutsch Tel: 80-530 English Tel: 80-532 Tel: 80-532 Italiano Tel: 80-534 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
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National does assume responsibility circuitry described, circuit patent licenses implied National reserves right time without notice change said circuitry specifications.

LM4543 Codec with National Sound LM4543 audio codec systems which

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