highlights Cyclic Redundancy Codes (CRC) Generator follow: Calculation

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Cyclic Redundancy Code Generator Macro
highlights Cyclic Redundancy Codes (CRC) Generator follow: Calculation Multiple Algorithm Support CRC8 A(HEC) CRC10 A(OAM) CANbus (SDLC, HDLC, CRC-CCITT) CRC16 CRC16 inverted CRC32 User defined polynomial Win32 console application that generates VHDL code Performance (CRC32, 54SXA Serial 32-bit Parallel, 8-bit Data-130 Generator application generates VHDL code specifically SX-A, ProASIC, ProASICPLUS families. VHDL code generated simply designed take advantage SX-A silicon features. This necessary meet timing requirement greater than MHz-oriented toward telecommunications applications.
Many designers alternative parity checksum calculation checking (and sometimes correcting) data transmission errors. 16-bit detects single double-burst errors ensures detection 99.998% possible errors. This level error protection considered sufficient data transmission blocks kilobytes less. larger transmissions, 32-bit often employed. Gigabit Ethernet, ATM, other higher-speed protocols require CRC, although exact polynomial changes depend upon transmission protocol (Figure ATM, 8-bit used header error check, addition (optional) error checking often done data. larger transmissions, 32-bit often used. method treats data frame large binary number. This number then divided generator end) fixed binary number (the generator polynomial) resulting value appended data frame. receiver then repeats calculation compares value with generated value. classic serial implementation method uses shift register with gates feedback taps shown Figure polynomial (G(x)=x16+x12+x5=1). serial implementation suitable about Mb/s using FPGAs. blocks described here used higher rates including Gigabit Ethernet Gb/sec serial rate stepped down A(620 Mb/sec serial rate stepped down 77.5 MHz).
CCITT Generator Polynomial G(x)
Data
Figure Serial Calculation
2002 Actel Corporation
Shift Sequence
initial contents feedback shift register shown row; namely, through After first data shifted into shift register, contents shift register functions previous
contents. continue shift until eight shifts have been made, shown diagram. shift register contents functions both original contents data bits after clocks, shown Figure
Initial:
shifted
shifted
shifted
Figure Serial Parallel Sequence input data bits available parallel, number steps generate reduced. example, 16-bit generation would two-step process- each eight input data bits. same technique extends 32-bit CRCs. Alternatively, expand equations full 32-bit step. There pipelining other than register itself. N-bit serial CRC, data becomes available clock edge after first (which clocks first into shift register). This actually cycle N+1. N-bit parallel CRC, with data bits available, should integer. Again, cycle cycle which data clocked into shift register, first bits available parallel cycle N/M+1, next bits cycle N/M+2, etc. This widely used method slow Gigabit Ethernet high-speed ATM, where rates Mbps. alternative method parallel computation CRC. Serial-to-parallel conversion data effectively divides input clock frequency calculate N-bit M-bits time. typical implementation shown Figure 8-bit parallel 16-bit CRC.
DI[7:0]
[7:0]
PARCRC8
[15:0]
>CLK
[15:0
ENABLE
>CLK
>CLK
INIT
>CLK
Figure 8-Bit Parallel CCITT-16
Top-Level Interface
Top-Level Block Diagrams
Figure illustrates serial parallel cases block. addition, Table describes signals serial parallel CRC.
RSTn INITn LOAD (M:0) (N:0)
Figure Block Table Top-Level Signal Description
RSTn INITn LOAD Input Input Input Input This master clock signal. Asynchronous system reset (initialization) signal. Synchronous reset (initialization) signal. parallel mode, when this signal high macro enabled allowing calculated incoming data. When this signal previous value retained output. serial mode, when this signal high macro enabled allowing calculated incoming data. When this signal calculated shifted unaltered incoming data. input data bits. serial computation, this single bit. output data bits. serial computation, this single bit.
D(M:0) CRC(N:)
Input Output
Win32 console application (NT/Win95/Win98/Win2000 compatible) allows choosing desired polynomial from menu. There several common generator polynomials supported with Actel Macro follow: sCRC8, A(HEC) x8+x2+x+1 CRC10, A(OAM Cell) x10+x9+x5+x4+x+1 CANbus x15+x14+x10+x8+x7+x4+x3+1 CRC16 x16+x12+x2+1 CRC16 inverted x16+x14+x+1 (SDLC, HDLC, CRC-CCITT) x16+x12+x5+1 CRC32 (Ethernet, FDDI)
user wants different polynomial, "Enter your polynomial" option available. example, polynomial would entered 10001000000100001. User-defined polynomials 32nd order (comparable CRC32, example) supported. addition, number input data bits calculated parallel selected. program will generate fully synthesizable, completely behavioral VHDL description. simple test bench been implemented illustrating generation using polynomial supplied with macro. test bench reads random data calculates both serially with 8-bit parallel data. simulation, CRCs compared verify that parallel implemented correctly (serial CRCs correct inspection). test bench easily modified accommodate different polynomials.
Estimated Performance Device Utilization
expected performance utilization statistics given Table Table serial parallel implementations using SX-A ProASICPLUS devices. clock frequency rate which Table 54SX-A Utilization Performance Statistics
Configuration with SXA08 Device CRC-32 Generator Polynomial CRC-16/CCITT Generator Polynomial 32-bit wide input 8-bit wide input 1-bit wide input 16-bit wide input 8-bit wide input 1-bit wide input Sequential/Total Used Modules 32/392 32/36 32/115 16/106 16/57 16/35
clocked. serial data rate effective system clock rate assuming serialization deserialization data parallel cases.
Percent 54SXA08
Maximum Clock Frequency (MHz)1
Maximum System Frequency 255MHz
TDPR used obtain timing results. Pipelining inputs macro were also used obtain parallel timing results.
Table ProASICPLUS Utilization Performance Statistics
Configuration with APA750 Device CRC-32 Generator Polynomial CRC-16/CCITT Generator Polynomial 32-bit wide input 8-bit wide input 1-bit wide input 16-bit wide input 8-bit wide input 1-bit wide input Sequential/Total Used Tiles 177/32768 177/32768 105/32768 128/32768 80/32768 38/32768 Percent APA750 Maximum Clock Frequency (MHz)1 Maximum System Frequency
TDPR used obtain timing results. Pipelining inputs macro were also used obtain parallel timing results.
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Actel Europe Ltd. Maxfli Court, Riverside Camberley, Surrey GU15 United Kingdom Tel: (0)1276 401450 Fax: (0)1276 401590
Actel Corporation East Arques Avenue Sunnyvale, California 94086 Tel: 408-739-1010 Fax: 408-739-1540
Actel Asia-Pacific EXOS Ebisu Bldg. 1-24-14 Ebisu Shibuya-ku Tokyo Japan Tel: +81-(0)3-3445-7671 Fax: +81-0)3-3445-7668
5172158-1/1.02

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