FAST Field Programmable Gate ArrayPredictable, Fast, Patented Active R

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DY6000Family
FAST Field Programmable Gate ArrayPredictable, Fast, Patented Active RepeaterArchitecture Data-Transfer Rates 200MHz 2.7ns Clock-to-Output Time with 10pf Load; 3.2ns with 50pf Load 1.4ns Input Register Setup Time 9,000 55,000 Usable Gates 32-Bit Synchronous 8ns-Access, Two-Clock, Two-Port SRAM Every Logic Block, Support 125MHz FIFOs PLLs 8MHz-to-200MHz Clock Multiplication, Division, Locking with Programmable Latency Clock Trees with 200ps Worst-Case Clock Skew 150ps Worst-Case Pin-to-Pin Skew Between Registered Logic Outputs Support Fast Buses In-System Reprogrammability Dynamic Single-Block Reconfigurability TTL, LV-TTL, GTL, GTLP Interface Levels; 24mA Drive GTL, 48mA Drive GTLP Nineteen LVDS-Compatible Input Pairs Nineteen Differential LV-PECL Input Pairs 66MHz, 64-Bit, Zero-Wait-State Soft Core 3.3V Operation with 5V-Tolerant Hot-Swappability System Shutdown Required When Exchanging Circuit Boards JTAG (IEEE1149.1) Boundary-Scan Conformance Individual Slew-Rate Controls Each Output Fully-Automatic Design Implementation Using DynaTool432-Pin EBGA 240-Pin EQFP Packages
Applications Examples
Data Communications: Gigabit Ethernet, ATM, Fibre Channel, Token Ring, SONET Switching, Routing, Functions Telecommunications High-Speed Graphics On-the-Fly-Reconfigurable Systems Servers Supercomputers Interfaces ASIC Emulation Semiconductor Testers High-Performance Instrumentation Medical Imaging Systems
Device DY6009 DY6020 DY6035 DY6055
Gates 9,000 20,000 35,000 55,000
Logic Blocks 1,024 1,600
User SRAM Bits 8,192 18,432 32,768 51,200
Flip- flops 1,536 2,560 3,840
Clock Trees
Blocks
Table DY6000 Family
DY6000 Family Datasheet Revision
April 1999
DY6000 Fast Field Programmable Gate Array
Table Contents
Features Applications Examples Introduction DY6000 Enhancements Performance Examples High-Performance Active Repeater Technology Top-Level Architecture Routing Architecture Input/Output Blocks LVDS External GTL/GTLP LV-PECL Reference Voltage Logic Blocks SRAM Clock Distribution Phase-Locked Loops Power Consumption Advance Estimates Configuration. Configuration Usage Configuration Modes Reconfiguration Resetting. Configuration-Related Pins JTAG Product Specifications. Maximum Ratings Recommended Operating Conditions Clock Set/Reset Buffer Switching Characteristics Block Switching Characteristics Logic Block Switching Characteristics Description 432-Pin EBGA 240-Pin EQFP Package Drawings 432-Pin EBGA 240-Pin Thermal Enhanced EQFP Ordering Information Sales Corporate Offices Back Pages
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DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
Introduction
DynaChip's third generation DY6000 family Fast Field Programmable Gate Array devices incorporate improvements internal architecture versatility. Fabricated using deep-submicron CMOS process, this family devices supports applications with system clock rates 200MHz well above rates achievable using conventional FPGAs. DY6000 family devices feature DynaChip's patented Active Repeaterarchitecture, which provides shorter, highly-predictable internal routing path delays. Every programmed LV-TTL GTL/GTLP interface levels well standard-TTL CMOS levels support fast data rates high-performance applications. Every logic block DY6000 family devices contains bits synchronous two-clock twoport SRAM, with access time; architecture particularly well suited implementing many small, fast, distributed SRAMs FIFOs customer designs. data rate matching applications, FIFO have completely independent read write clocks. High operating frequencies, on-chip distributed SRAM/FIFO, fast I/O, compatibility make DY6000 family devices ideal high-performance data communications, telecommunications, graphics, emulation applications. SRAM-based DY6000 family devices enable in-circuit configuration reprogramming on-the-fly. Dynamic single-block reconfiguration also possible, where portion device reprogrammed without affecting operation remaining logic. DY6000 family devices hot-swappable, system operation remains uninterrupted during power down things like exchanging circuit board.
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DY6000 Fast Field Programmable Gate Array
DY6000 Enhancements
DY6000 family incorporates numerous improvements: Wider functions single-logic level: 7-Input 2-Bit Full Adder 2-Bit Identity Comparator 9-Input Gate 16-Input AND/OR Function Local Fast-Carry-Chain Paths: Higher-Performance Full Adders Higher-Performance Identity Comparators Higher-Performance Parity Logic 125MHz Distributed Two-Clock Data-Rate-Matching FIFOs: 32-Bit Two-Clock, Two-Port SRAM Every Logic Block Separate Write Clock Read Clocks External Reference Voltage Blocks Supports GTLP Higher-Current Drive: 48mA GTLP Mode 24mA Mode) Programmable Latency: Adjustable from -3.0ns 2.0ns 150ps increments LV-PECL/LVDS Differential Input Pairs Chip Power-Down Mode `Green Design'
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DY6000 Fast Field Programmable Gate Array
Performance Examples
DY6000 family devices DynaChip's patented Active Repeaterarchitecture support high-performance applications clock rates chip-to-chip data-transfer rates 200MHz. Active repeaters significantly reduce routing delays even routing-intensive designs with high-fanout nets. Table gives performance values various macros implemented within DY6055G (fastest speed grade) device over commercial voltage temperature ranges. Circuit
Fully-Synchronous Loadable Up-Counters: 8-bit 16-bit 32-bit 64-bit Adders: 8-Bit, Using Carry Chain 16-Bit, Using Carry Chain Pipelined Multiplier SRAM-Based FIFOs: 32x32 64-Bit Shift Register 125MHz 160MHz 7.5ns 8.8ns 145MHz 145MHz 140MHz 125MHz 100MHz
DY6055G
Logic Block Count
Table Performance Various Applications (Includes Routing Delays) Assumptions: speed grade over commercial voltage temperature range; 10pF load fast slewrate setting outputs.
Notes: When measuring these performance values over industrial voltage temperature ranges, derate values percent. When comparing DY6000 family FPGA performance with competing products, values Table include block routing delays within same routing region. maximum chip-to-chip data-transfer rate 250MHz assuming 10pF loads, GTL/GTLP interface levels, fastest slew rate.
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DY6000 Fast Field Programmable Gate Array
High-Performance Active Repeater Technology
Active Repeater Routing, illustrated Figure enabling technology behind DynaChip's patented Fast Field Programmable Gate Arrays. Conventional FPGA devices pass gates create programmable interconnections. When using multiple pass gates create net, they like series resistors with distributed capacitance ground, shown Figure Nets formed series these pass gates slow down dramatically number programmable connections increases, resulting long, unpredictable delays, especially those nets which must traverse long physical distance drive large number loads. contrast, DynaChip DY6000-family devices Active Repeaters create programmable interconnections. shown Figure these repeaters buffer signal every interconnection point isolate capacitance rest net. result fast, predictable performance even long, high-fanout nets.
Logic Block
Figure Pass Gates Series Delay Degrade Signals
Logic Block
Figure DynaChip's Active Repeaters Build Fast, Predictable Interconnect
Figure illustrates comparison delays between circuit technologies number programmable interconnection points grow. FPGA devices using pass gate-based interconnect, delays increase quadratically with number interconnection points, resulting performance bottlenecks long and/or heavily-loaded nets. Conversely, using Active Repeater interconnect produces delays which increase only linearly with number interconnection points, affected increased fanout, resulting higher performance superior predictability.
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DY6000 Fast Field Programmable Gate Array
Interconnect Delay
Connections
Pass-gate Interconnect Active Repeater
Figure Active Repeatervs. Pass Gate Delays
Top-Level Architecture
Figure illustrates architecture common DY6000 family devices, reduced number blocks. border blocks forms outer perimeter device. rectangular array logic blocks occupies device's interior. spaces between these logic blocks form channels, which filled horizontal vertical routing tracks. structure individual DY6000 routing tracks entirely different from corresponding structures conventional FPGAs. illustrations Figure Figure Figure emphasize effect these differences. Using Active Repeaters eliminates need numerous levels routing tracks varying lengths, resulting more predictable convergence optimized solutions.
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DY6000 Fast Field Programmable Gate Array
Vertical Routing Tracks
Input Output Blocks Logic Blocks
Horizontal Routing Tracks
Figure Overview DY6000 Architecture
Routing Architecture
Dynachip's Active Repeater technology provides higher performance than more complex multi-level routing architectures. shown Figure routing region consists logic blocks horizontal vertical routing tracks, interconnected buffers controlled programmable configuration SRAM bits. routing programmed selecting which these buffers turn there pass gates other passive routing types. Active Repeater buffers drive fixed loads optimized those loads. result, their logic delays fixed performance large complex user designs deterministic predictable. There four types Active Repeater buffers: Horizontal (Horizontal-to-Horizontal Bidirectional Buffers) Vertical (Vertical-to-Vertical Bidirectional Buffers) Vertical-to-Horizontal Connection Buffers Horizontal-to-Vertical Connection Buffers shown Figure each DY6000 logic block nine-block local routing region; three rows high three columns wide. Active Repeaters staggered that every block associated routing region, which overlaps routing regions nearby blocks.
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DY6000 Fast Field Programmable Gate Array
Routing regions connected bidirectional Active Repeater buffers. signal which passed through Active Repeater available throughout next routing region.
Logic Block Logic Block Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
In-Line Active Repeater
Corner-Turning Connection Buffer
Input Connection
Each vertical line shown represents actual vertical tracks. Each horizontal line shown represents actual horizontal tracks. Figure Routing Architecture
This architecture allows logic block drive nine logic blocks routing region, with additional routing delays even high-fanout nets, shown Figure Performance completely deterministic within that routing region. DY6000 parameters presented Table allow designers accurately estimate performance because they include connection buffer delays other routing delays within logic block's routing region. DY6000 parameters presented Table show logic block delays without connection buffer routing delays useful comparing DY6000 other FPGA technologies.
Logic Block Logic Block Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
In-Line Active Repeater
Corner-Turning Connection Buffer
Input Connection
Figure Routing Region With Interconnect Delay
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DY6000 Fast Field Programmable Gate Array
signal driving block blocks within next region, fixed delay through Active Repeater added logic block delay. Thereafter, additional Active Repeater delay added every logic blocks signal traverses. Figure shows number logic blocks that driven with active repeaters. Active Repeater delays only routing delays DY6000 device. Active Repeaters performance values given Table this data sheet. Each logic block typically implements twenty logic gates thirty-two SRAM bits. total logic memory resources which reached with Active Repeater delays shown Table illustrated Figure Active Repeater Delays
Logic Blocks
Gates
1,460
SRAM Bits
1,056 2,336
Table Accessing Neighboring Logic Blocks
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DY6000 Fast Field Programmable Gate Array
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
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LOGIC BLOCK
LOGIC BLOCK
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LOGIC BLOCK
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LOGIC BLOCK
LOGIC BLOCK
Source block Access with repeaters Access with repeater Access with repeaters
Figure Logic Blocks Reachable with Active Repeaters
Input/Output Blocks
DY6000 block structure illustrated Figure Each block includes input flipflop output flip-flop, both featuring clock enables. Every block independently accommodate either LV-TTL tolerant) GTL/GTLP interface levels. However, levels GTLP levels mixed same physical FPGA chip. Thirty-eight blocks have slightly different input circuitry accommodate LVPECL and/or LVDS input signals well LV-TTL GTL/GTLP signals. These configured differential pairs single-ended inputs. When used LV-PECL LVDS, these used inputs only. These inputs tolerant.
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DY6000 Fast Field Programmable Gate Array
Input/ Output
From Global Set/Reset Line
Bidirectional Boundary Scan Circuit From Global Clock Array From Global Clock Array From Quadrant Clock Array From Quadrant Clock Array
Vertical Horizontal Routing Channels (Input Data)
From Horizontal Vertical Routing Channels (Output Enable) From Global Set/Reset Line From Horizontal Vertical Routing Channels (Output Data) From Horizontal Vertical Routing Channels (Clock Enable)
Output Slew Rate Control
From Global Clock Array Bidirectional Boundary Scan Circuit From Global Clock Array From Quadrant Clock Array From Quadrant Clock Array
Key:
Programmable
Point
Figure Input/Output Block Note: numbers within logic symbols used DynaTool identify particular logic elements.
Each block configured handle input, output, bidirectional signals. Clock signals either flip-flops block come from either global clocks which serve entire chip, from either quadrant clocks which serve that particular region device. Each output individual slew rate control three-state enable control. output's slew rate fast, medium, slow, regardless settings other outputs chip, unless it's GTL/GTLP-compatible. Each output also equipped with high-resistance, individually-programmable active pull-up active pull-down elements. Using DynaTool, connect pullup, connect pulldown, leave both them unconnected that output float. Connecting both pullup pulldown elements simultaneously allowed.
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DY6000 Fast Field Programmable Gate Array
With supply voltage 3.3V, current pull-up pull-down element limited less than 100µA. Each block includes JTAG Boundary Scan logic, conformant IEEE 1149.1 (JTAG) Specification.
LVDS
LV-PECL capable input pairs interface directly LVDS levels. these inputs LVDS levels, must place shunt resistor between input pairs, illustrated Figure
3.3V Coax Cable LVDS Resistor
DY6000 Input
3.3V
Coax Cable
LV-PECL Input
Figure Interfacing LVDS LV-PECL using DY6000 Inputs
External GTL/GTLP LV-PECL Reference Voltage
DY6000 blocks external reference voltage. block programmed this externally-supplied reference voltage. Recommended voltage settings GTL, GTLP, LV-PECL are: Required Compatibility
GTLP LV-PECL
Reference Voltage
0.8V 1.0V (VCC 1.3V)
Table Recommended Settings Reference-Voltage Input
GTLP settings two-thirds recommended termination voltage VTT. Using external reference voltage mandatory GTLP optional LVPECL. external reference voltage used, internal reference voltage provided.
Logic Blocks
DY6000 Logic Block, simplified Figure shown fully Figure contains AND, gates, flip-flops, muxes, 32-bit, two-clock, two-port SRAM, making this block versatile powerful. DynaTool(DynaChip's development system) automatically maps logic from designer's application into these logic block resources. logic block implement two-bit full adder identity comparator, nine-input gate, seven-input parity tree, multiplexer, other logic functions comparable complexity.
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DY6000 Fast Field Programmable Gate Array
logic block includes sixteen general purpose logic inputs, plus Clock Set/Reset inputs. inputs equipped with polarity control circuits, which programmed pass their signals either noninverted (true) inverted (false). There also Global Clock Inputs, Quadrant Clock Inputs, Global Set/Reset Input, `Top' `Bottom' Carry Inputs. There three logic outputs, plus `Top' `Bottom' Carry outputs. three logic outputs driven logic blocks' combinatorial logic, flip-flops, SRAM. logic outputs direct registered. third output always direct. Carry inputs outputs form fast-carry paths through logic block, `Top' path `Bottom' path, providing high-speed routing logic blocks immediately above below given logic block. These fast-carry paths useful speeding adders, identity comparators, functions. adder applications, delay carry signals using these fast-carry paths consists initial delay required access fast-carry path, incremental delay each bits adder, final delay required exiting fastcarry path.
Local, Global, Quadrant Clock Local Global Set/Reset Carry
AND/OR ARITHMETIC 32-bit SRAM Bottom Carry
COMB
Figure Conceptual Diagram Logic Block
functional areas shown Figure AND/OR logic section, multiplexer section, arithmetic logic section, thirty two-bit, two-clock, two-port SRAM section. Each block includes flip-flops that configurable either D-type T-type element. Both flip-flops clocked from five sources (local clock (LCLK)), global clocks (GCLK1 GCLK2), quadrant clocks (QCLK1 QCLK2), which serve this region. Flip-flops programmed active either rising falling clock edge.
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DY6000 Fast Field Programmable Gate Array
GCLK1 GCLK2 QCLK1 QCLK2
Clock Enable
LCLK
AND/OR Logic
Multiplexer Logic
Arithmetic Logic
CLKW CLKR A0(0) A0(1) A0(2) A0(3) A1(0) A1(1) A1(2) A1(3) A4/W
SRAM
Logic
(Rout1) (Rout0)
Key:
64,65,66
Programmable
Point
Note: numbers within logic symbols used DynaTool identify particular logic elements. Figure Schematic Diagram Logic Block
Programmable
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DY6000 Fast Field Programmable Gate Array
flip-flops share common set/reset signal from either sources: local interconnect (LSR), FPGA's global set/reset (GSR). set/reset input programmable polarity control. choose assertive-HIGH operation assertiveLOW operation resetting flip-flops, although your choice must same both. Likewise, configure flip-flops together either operation reset operation.
SRAM
Each logic block DY6000-family FPGA includes bits fully-synchronous dual-port, two-clock SRAM with three configuration options: 32x1 two-port SRAM. 32x1 single-port SRAM. separate 16x1 single-port SRAMs. Functional block diagrams corresponding each these configurations shown Figure Figure Figure signals one-bit except addresses, which five-bit 32x1 configurations, four-bit double-16x1 configuration. SRAM separate read write clocks. Either these clocks originate from five sources: local interconnect (LCLK), either FPGA's global clocks (GCLK1 GCLK2), either FPGA's quadrant clocks (QCLK1 QCLK2) serving that region chip. single-port configurations, write clock read clock automatically tied together. three SRAM configurations, both writing reading synchronous operations.
Write Address Write Enable Write Port Write Clock Write Data
A14-0 CLKW 32x1 SRAM Read Data
Read Address Read Port Read Clock
A04-0 CLKR
Global Power-Down
Figure 32x1 Two-Port SRAM
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DY6000 Fast Field Programmable Gate Array
Write Enable
Write Data Read/Write Address Read/Write Clock
A04-0
32x1 SRAM Read Data
Global Power-Down
Figure 32x1 Single-Port SRAM
rising edge LOW-to-HIGH transition) write clock, address, data inputs latched. HIGH, data written same clock cycle. Writing single-clock operation. While write operation progress, state data output(s) indeterminate.
Write Enable
Write Data SRAM Port Read/Write Address Read/Write Clock
A03-0
16x1 SRAM
Read Data
Global Power Down
Write Enable
Write Data SRAM Port Read/Write Address Read/Write Clock
A13-0
16x1 SRAM
Read Data
Global Power-Down
Figure Separate 16x1 Single-Port SRAMs
rising edge read clock, outputs latched available output(s). Reading single-clock operation. two-port SRAM configuration separate write port read port, with separate read address clock signals. Single-port configurations have common read/write clocks addresses.
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DY6000 Fast Field Programmable Gate Array
single-port configurations, SRAM write mode whenever asserted read mode whenever asserted. two-port configurations, SRAM always read mode regardless state except when read-write collision occurs; that when attempt made read write same location same time. this case, writing takes precedence over reading, data output indeterminate. Timing waveforms SRAM write read operations shown Figure Figure Figure Figure Figure apply 32x1 two-port configuration. Figure common case where write read addresses same, Figure applies `read-write collision' case where addresses same. Figure applies both 32x1 single-port configuration two-16x1 single-port configuration.
Read/Write Cycle CLKR
CLKW
Write Address Read Address
Figure Two-Port SRAM Read/Write Cycle, with Differing Write Read Addresses
Read/Write Cycle CLKR tRBW CLKW tRAW
Indeterminate Results*
Write Address
Figure Two-Port SRAM Read/Write Cycle, with Identical Write Read Addresses rising edge CLKW occurs this region, output indeterminate.
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DY6000 Fast Field Programmable Gate Array
Write Cycle CLKW* Addresses Data
Read Cycle CLKR* Addresses Figure Read/Write Cycle Timing Single-Port SRAM Configurations single-port operation, CLKW CLKR automatically tied together.
SRAM powered down using Global Power-Down (GPD) signal. This signal must meet setup-time hold-time conditions with respect clock (write read), entry exit from powered-down mode effective that clock. powereddown mode, SRAM bits retain their previously stored information, cannot written into read from long powered-down mode remains effect, illustrated Figure signal (pin name IO3/PECL1_GPD) tolerant.
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DY6000 Fast Field Programmable Gate Array
CLKW CLKR
Output
Active
Powered Down
Active
tGSS Internal
tGSH
tGSS
tGPD
tGPD
Figure SRAM Power-Down Cycle
Clock Distribution
DY6000-family FPGAs have low-skew clock distribution networks. these global networks which access entire device; other eight quadrant networks which access quarter device. Each clock networks driven from package pin, from PLLs, from signals generated within FPGA. signal clock networks driven off-chip through package pins. Every logic block five clock signals: either global clocks either quadrant clocks quadrant local interconnect clock (LCLK) generated user's logic Every block four clock signals: either global clocks either quadrant clocks quadrant. input pins that drive clock networks programmable LV-TTL, GTL, GTLP, single-ended LV-PECL, differential LV-PECL, differential LVDS interface levels. Clock inputs tolerant.
Phase-Locked Loops
DY6000 devices contain PLLs clock latency reduction, clock multiplication, clock division. Each PLLs drive global clock network four quadrant-clock networks. PLLs multiply divide clock signals default, reduces clock latency zero. latency programmed 150ps increments, over range -3ns +2ns. filter required power supply. Refer DynaChip's application note more information filter requirements.
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External resistors connected device pins PLL1REST PLL2REST signal optimization. most applications, these pins should tied ground. PLL1 located top-left corner chip, drive GCLK1, QCLK1TL, QCLK1TR, QCLK1BL, QCLK1BR. PLL2 located top-right corner chip, drive GCLK2, QCLK2TL, QCLK2TR, QCLK2BL, QCLK2BR. PLLs support clock frequency 8MHz 200MHz. Table shows supported input frequency range different multiplication factors. Multiplier Minimum Input Frequency Maximum Input Frequency
*Contact factory additional information applications that require multiplier frequencies below MHz. Table PLLs' Supported Input Frequency Ranges
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DY6000 Fast Field Programmable Gate Array
Figure shows, simplified form, clock networks entire chip.
QCLK2TL
QCLK1TL
QCLK1TR
QCLK2TR
Quadrant
Global Clock
Network
Quadrant
G1CLK PLL1
G2CLK PLL2
Global
Clock Network
Quadrant
Quadrant
QCLK2BL
QCLK1BL
QCLK1BR
QCLK2BR
Figure Clock Networks
jitter incoming clock 100ps less, then jitter clock signal produced less than 350ps over commercial voltage temperature range, 450ps over industrial voltage temperature range.
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Power Consumption
Power consumption DY6000 device depends upon: number logic blocks, SRAM bits, clocks, PLLs used. operating frequency. operating supply voltage. number outputs used. interface-levels (TTL GTL/GTLP) slew-rate settings. speed grade FPGA. general, on-chip logic resources draw power only programmed something. Power consumption frequency-dependent, also depends upon percentage flipflops which switching each clock. power estimates, reasonable assume that flip-flops design switching each clock. addition, DY6000-FPGA power consumption affected actual core supply voltages, which nominally 3.3V. Faster speed grade devices typically consume more power. power consumption increases approximately speed grade.
Advance Estimates
methodology first-order estimate power dissipation provided here. DynaTool reports more accurate power estimate. estimation process divided into parts: dynamic power drawn internal resources when they clocked, static power being drawn FPGA regardless clock. dynamic power estimate, there baseline typical power-dissipation value, which assumes 3.3V power supply, 100MHz operation, 30pf capacitive load each active output. There also sensitivity values each volt supply voltage, each 1MHz frequency, each capacitive loading output pins. values given logic blocks. value blocks where logic strictly combinatorial, other blocks where flip-flop included registered operation. Baseline Voltage Frequency Estimate Sensitivity Sensitivity (mW) (mW/V) (mW/MHz) Combinatorial Input* 2.43 0.96 0.013 Registered Input* 4.62 3.99 0.017 Combinatorial Output* 17.85 7.06 0.033 Registered Output* 18.81 5.51 0.033 Combinatorial Logic Block* 5.78 0.50 0.026 Registered Logic Block* 7.03 3.86 0.013 22.44 10.00 0.155 Global Clock 340.43 160.22 6.755 Quadrant Clock 85.11 40.06 1.690 Element Output-Loading Sensitivity (mW/pF) 0.33 0.33
*These numbers should multiplied percentage design that switching each clock (Typically 25%). Table Typical Switching Power Consumption
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static-power estimate, it's assumed that FPGA idle that that flipflops switching, either logic blocks blocks. most obvious method placing FPGA into this condition disable clock networks, some means either on-chip off-chip. components static power are: standby power. bias power. static power. memory static power. Standby power drawn entire FPGA when flip-flops disabled from switching when SRAM bits subject Global Power-Down (GPD). Bias power drawn whenever blocks programmed GTL/GTLP PECL interface levels. external-voltage-reference used, voltage present affect bias power. blocks programmed GTLP levels, this external-voltagereference must held voltage suitable GTLP. Static power that which drawn zero frequency. Memory static power drawn 32-bit memory logic block when block programmed power down asserted. Here, power drawn depends upon memory configuration; 32x1 two-port configuration draws twice much static power single-port configurations. static power, there baseline typical value 3.3V, sensitivity value indicated parameter changes with voltage. Item Standby Power (Entire Chip) Bias Power (Entire Chip) Static Power (per PLL) Static Single-Port Memory (per Bits)* Static Dual-Port Memory (per Bits)* Baseline Estimate mW/Item Voltage Sensitivity mW/V
Table Typical Static Power Consumption This item becomes zero when (General Power-Down) asserted.
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Configuration
Configuration memory DY6000 stores programming bits that control operation programmable elements device. These programming bits called bitstream. configuration memory volatile does retain information when FPGA powered off. configuration process must repeated each power only portion FPGA's resources used, bitstream needs include only bits necessary program those resources. Table gives maximum possible number bitstream bits each DY6000-family FPGA. Device DY6009 DY6020 DY6035 DY6055 Array 16x16 24x24 32x32 40x40 Maximum Number Programming Bits 235,524 304,856 452,696 686,776
Table Maximum Number Programming Bits
configuration mode controlled state mode pins these mode pins left unconnected, weak pulldown resistor holds them logic `0.' Table shows mode states required each configuration mode. Configuration Mode Mode Serial/Internal Last Mode Serial/External Last Mode (Reserved Future Use) Mode Readback Mode Serial/External Last Mode Parallel/External Last Mode Parallel/External Last Mode Full-Chip Reset
Table Mode-Pins Settings
Readback Mode used read bitstream from configured FPGA determine bitstream been properly loaded.
Configuration Usage
There categories configuration pins: dedicated dual-purpose. Dedicated pins always reserved their configuration function. Dual-purpose pins have configuration function during downloading become user after configuration. dedicated pins are: PCKI/PCKO, STPRGM, RESET, SYSDONE. dual-purpose pins are: DONE, RDY, DOUT. Serial Configuration modes dual-purpose pins used follows: used configuration during download readback. DONE used configuration during download readback, only several FPGAs `chained.'
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DY6000 Fast Field Programmable Gate Array
DOUT used configuration only readback required. remaining dual-purpose pins used downloading readback. Parallel Configuration Modes dual-purpose pins used follows: used downloading and/or readback. DONE downloading and/or readback only when several FPGAs chained.' Otherwise, this available connections. DOUT used only readback required. Otherwise, this available connections user designs. DynaChip FPGAs capable being partially reconfigured during operation; however, dual-purpose pins used configuration downloading and/or readback must reserved, available user connections. Otherwise, dual purpose becomes available when configuration completes.
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Configuration Modes
Three Serial Configuration Modes available, described previously Table below Table Serial Configuration Mode Mode Serial/Internal Last Description This mode used situations: program single DY6000 device from serial PROM. this mode, DY6000 device generates clock signal drive serial PROM. last DY6000 device, programming chain that uses serial PROM. this mode, DY6000 device generates clock signal drive both serial PROM other DynaChip devices chain. Mode Serial/External Last This mode used each DY6000 device, except last DY6000 device, programming chain that uses serial PROM regardless source programming clock. This mode used situations: program single DY6000 device, using serial bitstream usersupplied clock. last DY6000 device, programming chain that programmed using serial bitstream usersupplied clock.
Table Serial Configuration Modes
Mode Serial/External Last
Parallel Configuration Modes available, described previously Table below Table Parallel Configuration Mode Mode Parallel/External Last Description This mode used situations: program single DY6000 device from microprocessor. last DY6000 device, programming chain that uses microprocessor. Mode Parallel/External Last This mode used each DY6000 device, except last DY6000 device, programming chain that uses microprocessor.
Table Parallel Configuration Modes
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DY6000 Fast Field Programmable Gate Array
There nine possible cases when reconfiguring DY6000 FPGA, indicated Table These cases determined Bitstream format bit-serial, byte-parallel. Clocking source internal FPGA, from external clock. Loading position standalone, chained. chained, loading position within chain last, last. combination these choices, byte-parallel with internal clocking from within FPGA, supported DY6000 family FPGAs. Although there mode clocking differences between `Standalone FPGA' case `Chained FPGAs Last' case, presented inTable their wiring connections different, illustrated Figures which each case refers. Format Clock Standalone FPGA Last (Only) Serial/Internal Mode Serial/Internal Last 2.5MHz Clock, Generated Within FPGA, Output PCKO Figure Serial/External Mode Serial/ External Last 15.0MHz Clock, Supplied Externally, Input PCKI Figure Parallel/External Mode Parallel/ External Last 2.5MHz External Handshake Signals; Input Output Figure Chained FPGAs Last Mode Serial/ External Last 2.5MHz Clock, From Last FPGA, Input PCKI Figure Mode Serial/ External Last 15.0MHz Clock, Supplied Externally, Input PCKI Figure Mode Parallel/ External Last 2.5MHz External Handshake Signals; Input Output Figure Last Mode Serial/Internal Last 2.5MHz Clock, Generated Within FPGA, Output PCKO Figure Mode Serial/ External Last 15.0MHz Clock, Supplied Externally, Input PCKI Figure Mode Parallel/ External Last 2.5MHz External Handshake Signals; Input Output Figure
Table Serial Parallel Modes Clock Sources Configuration
Clocking three main configuration methods properties given Table
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DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
Mode
Clock Source
Frequency
Rate
Serial/Internal Serial/External Parallel/External
Last/Only FPGA External System External System
Approximately 2.5MHz Most 15.0MHz Most 2.5MHz
2.5Mbs 15.0Mbs 20.0Mbs
Table Configuration Clocking Ground Rules
Parallel/External method there `clocking' Rather, handshake exchange occurs between microprocessor FPGA being downloaded. microprocessor asserts Write Enable (WE) signal FPGA byte ready loaded, FPGA responds asserting ReaDY (RDY) when data been read device ready next byte.
Most-Positive Supply Voltage Data Clock Chip Enable RESET/OE RESET Most-Negative Supply Voltage Start Download DY6000
Serial Memory
PCKO SYSDONE STPRGM RESET
Figure Serial/Internal Configuration, Standalone
Serial/Internal method uses fewest external resources. Serial/External method fastest since supply clock MHz. Parallel/External method useful when microprocessor contained within system. setup Serial/Internal method consists only serial-output Programmable ReadOnly Memory (PROM) more DY6000 FPGAs. With standalone FPGA, internal oscillator within FPGA clock source both that FPGA PROM, shown interconnections illustration Figure With more FPGAs chain, last FPGA clock source both PROM entire chain, shown interconnections illustration Figure standalone, last, FPGA operates Mode not-last FPGA operates Mode frequency standalone last FPGA's internal oscillator, nominally about 2.5MHz, determines bit-transfer rate PROM FPGA(s).
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
Most-Positive Supply Voltage
DY6000 DONE PCKI Start Download STPRGM DONE
DY6000 DONE PCKI STPRGM DONE RESET
DY6000
Serial Memory PCKO Clock Chip Enable
STPRGM DONE RESET
RESET RESET
RESET/OE
Most-Negative Supply Voltage
Figure Serial/Internal Configuration, Chained
setup Serial/External method differs from Serial/Internal method only that clock comes from some outside source. interconnections standalone FPGA shown Figure chain more FPGAs Figure Here, standalone `Last' FPGA operates Mode not-last FPGA operates Mode transfer rate PROM FPGA(s) determined frequency outside clock source, which frequency 15.0MHz.
Most-Positive Supply Voltage External Clock Serial Memory Chip Enable RESET/OE RESET Most-Negative Supply Voltage Start Download Data Clock DY6000
PCKI SYSDONE STPRGM RESET
Figure Serial/External Configuration, Standalone
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DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
Most-Positive Supply Voltage External Clock DY6000 DONE PCKI DONE RESET STPRGM DONE PCKI STPRGM DONE RESET DY6000 DY6000 PCKI STPRGM DONE Serial Memory Clock Chip Enable
Start Download
RESET
RESET/OE
RESET Most-Negative Supply Voltage
Figure Serial/External Configuration, Chained
Parallel/External method, there handshake signaling between microprocessor FPGA. interconnections standalone FPGA shown Figure chain more FPGAs Figure Here, standalone `Last' FPGA operates Mode not-last FPGA operates Mode byte transfer rate determined frequency handshake, which should exceed 2.5MHz. Thus, maximum bittransfer rate eight times that value, which 20.0MHz.
Most-Positive Supply Voltage Microprocessor D[7:0] Status Interrupt Command Command Status Interrupt Command DY6000 D[7:0] STPRGM SYSDONE RESET
Most-Negative Supply Voltage
Figure Parallel/External Configuration, Standalone
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
Most-Positive Supply Voltage
DY6000 DONE RESET STPRGM DONE DONE
DY6000
DY6000 RESET STPRGM DONE D[7:0] Microprocessor
RESET STPRGM DONE D[7:0]
Status Interrupt
D[7:0]
DATA STPRGM RESET D[7:0] Command Command Status Interrupt Command Most-Negative Supply Voltage
Figure Parallel/External Configuration, Chained
configuration modes, programming process launched asserting STart PRoGraM (STPRGM) input. When that FPGA received enough bits that portion programming process complete, asserts SYStem DONE (SYSDONE) output. When more FPGAs chained, SYSDONE output (n)th FPGA connected STPRGM input (n+1)st FPGA. FPGA Serial modes treats incoming clock Programming ClocK Input (PCKI) edge-sensitive signal, responds positive (rising) edge. same true Parallel modes incoming handshake signal
Reconfiguration Resetting
DY6000 three different reset capabilities: Full-Chip Reset-All configuration bits, logic-block flip-flops, flip-flops, bits reset state. Full-Chip Reset initiated from different methods: Automatically initiated whenever FPGA device powered Initiated external system without shutting power applying code Mode then asserting RESET input. (The RESET `RESETN' list, assertive-LOW input.) This typically used applications that reprogram entire FPGA system. Partial Reconfiguration Reset-All configuration bits region being configured overwritten with values, flip-flops bits this region reset. This typically used applications that reprogram portion FPGA system.
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DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
Logic-block flip-flops bits regions that reconfigured unaffected. Partial Reconfiguration Reset must initiated external system without shutting power applying code mode except Mode then asserting RESET input. Global System Reset-No configuration bits affected. logic block flipflops either reset according their design definition, block flipflops reset. Refer Logic Block discussion Figure Global System Reset initiated external system without shutting power asserting input. (The `GSR/GSR' list, assertive-HIGH input.) Reprogramming, after Full-Chip Reset, must occur Modes Figure gives representative timing waveforms, case where Mode (Serial/External Last) used reprogramming. During programming, HIGH LOW. Figure shows minimum required timing asserting RESET (LOW).
(min)
RESET
(min)
(min)
(min)
Figure Full-Chip Reset Serial/External Last Mode
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
Configuration-Related Pins
types pins used configuration process. Fixed-function pins always dedicated configuration usage. Dual-purpose pins have special configuration functions become user-assignable pins after device configuration. PCKI/PCKO Name Type Function This different functions, depending programming mode: device only device programmed last programming chain, external clock being used, this output that provides master clock other devices serial PROM. device programming chain last device, external user-supplied clock controls configuration process, this input which receives clock from source outside FPGA. When FPGA being programmed, functionality this defaults that PCKI. STPRGM STart PRoGraM Fixed-Function This initiates configuration process. Depending that FPGA's position (standalone, last, last) receives input either from external system, from previous FPGA chain.
Programming Fixed-Function Clock Input/Output
Table Configuration-Related Pins
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DY6000 Fast Field Programmable Gate Array
RESETN
Name RESET
Type Fixed-Function
Function This controls changes configuration memory. Mode causes Full-Chip Reset clearing entire configuration memory, state, bits. other configuration modes, causes writing incoming bitstream over specified portions configuration memory. Figure shows timing required proper operation Full-Chip Reset. This output dedicated programming. configured CMOS open drain output. When configured open drain output, external pull-up resistor required. Once configuration been completed, SYSDONE goes from HIGH.It stays HIGH until either power turned off, RESET signal applied. FPGA last only device programmed, this signals that configuration been completed. FPGA last programming chain, this signals other devices that programming been completed, return normal operation. This signal also used control enabling disabling external serial PROM(s). These pins inputs during programming. They control mode used configuring FPGA. configuration-mode pins listed Table These pins become I/Os during normal operation. mode pins connected, they pulled down logic
SYSDONE
SYStem DONE
Fixed-Function
Mode
Dual-Purpose
Table Configuration-Related Pins
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
DONE
Name DONE
Type Dual-Purpose
Function This input during programming which used only chained-multiple-device configuration mode. device last chain, DONE tied SYSDONE last device. LOW-to-HIGH transition this signals that programming been completed device begins normal operation. This used during normal operation. This input during programming. accepts serial data from outside source. also accept (Least-Significant Bit) from byte-wide memory microprocessor bus. This used during normal operation. These data-input pins parallel configuration modes. They activated only after RESET signal been applied. Together with they accept byte-wide data loaded from parallel source such microprocessor. They used I/Os during normal operation. This input parallel configuration modes. activated only after RESET signal been applied. This used microprocessor signal DY6000 that eight-bit byte been placed D[7:0] inputs. This becomes during normal operation.
Data
Dual-Purpose
Data
Dual-Purpose
Write Enable
Dual-Purpose
Table Configuration-Related Pins
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DY6000 Fast Field Programmable Gate Array
Name ReaDY
Type Dual-Purpose
Function This output parallel configuration modes. signals external microprocessor that eightbit byte been loaded, that device ready receive next byte. Together with RDY, provides `handshake signaling' coordinate data-transfer process. This used during normal operation. This output supplies bitstream during readback. This used during normal operation.
DOUT
Data
Dual-Purpose
Table Configuration-Related Pins
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DY6000 Fast Field Programmable Gate Array
JTAG
devices DY6000 family provide JTAG (Joint Test Action Group) Boundary Scan, conformant IEEE1149.1 specification. This feature simplifies testing boards incorporating devices surface-mount packages, packages with closely-spaced pins. Four JTAG instructions supported, shown Table JTAG Instruction SAMPL/PRE EXTEST BYPASS IDCODE Register BYPASS
Table JTAG Instructions
Opcode 1000 0000 1111 1101
JTAG register read when DY6000 device reset, when 1101 opcode loaded. Upon power-up, opcode defaults 1101. Internal pullup resistors provided pins. DY6000 JTAG number (hexadecimal 06055, followed 0B91 irregularly-spaced fields).
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DY6000 Fast Field Programmable Gate Array
Product Specifications
Maximum Ratings
Symbol Description Potential Lead Input Voltage Normal Pins Low-Voltage Pins Voltage Applied 3-State Output Normal Pins Low-Voltage Pins Supply Voltage Rise Time, Storage Temperature (Ambient) Junction Temperature Ceramic Plastic Soldering Temperature Value -0.5 +5.0 -0.5 -0.5 +3.6 -0.5 -0.5 +3.6 +150 +150 +125 +260 Unit
TVCC TSTORE TSOL(3)
Table Absolute Maximum Rating Notes: Permanent damage device occur Absolute Maximum ratings exceeded. These stress ratings only. Functional operation device these other conditions, other than those listed under Recommended Operating Conditions, implied. Exposure Absolute Maximum Ratings conditions extended periods time degrade device reliability. TSOL should occur more than seconds. (EBGA package only.)
Recommended Operating Conditions
Symbol Description Supply Voltage Relative GND: Commercial: Junction Industrial: -40° 100° Junction (GTL) Terminating Voltage Relative GND: Commercial: Junction Industrial: -40° 100° Junction (GTLP) GTLP Terminating Voltage Relative GND: Commercial: Junction Industrial: -40° 100° Junction VREF(2) GTL/GTLP Reference Voltage Relative GND(3) LV-PECL Reference Voltage Input Signal Rise Fall Time 3.14 1.14 1.08 3.47 1.26 1.32 Unit
1.43 1.58 1.35 1.65 1.36 1.24
Table Recommended Operating Conditions Notes: junction temperatures above those listed Recommended Operating Conditions unsafe, destroy device. This voltage should applied VREF DY6000-family devices.
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DY6000 Fast Field Programmable Gate Array
Symbol VIMAX
Parameter Max. Voltage Applied Input Max. Voltage Applied Clock Low-Voltage Inputs HIGH-Level Input Voltage LOW-Level Input Voltage HIGH-Level Input Voltage LOW-Level Input Voltage HIGH-Level Input Voltage LOW-Level Input Voltage HIGH-Level Input Voltage LOW-Level Input Voltage HIGH Level Output Voltage Level Output Voltage
0.7VCC VREF 2.135 1.490
0.3VCC VREF 2.420 1.825 0.55 -150 -200 10.0
Units
Test Conditions
VCMAX(5) VIH(TTL) VIL(TTL) VIH(CMOS) VIL(CMOS) VIH(GTL
GTLP)
VIL(GTL GTLP) VIH(LVPECL) VIL(LVPECL) (TTL) VOL(TTL) VOH(GTL) VOL(GTL) VOH(GTLP) VOL(GTLP) VDR(8) IDDQ
3.3V 3.3V Min. Note Min. Note 20mA, 40mA,
HIGH Level Output Voltage (2,3) Level Output Voltage
HIGH Level Output Voltage (2,3) Level Output Voltage Data-Retention Voltage Quiescent Current Leakage Current Pullup Current (When Selected) Pulldown Current (When Selected) Input Capacitance
Max; I/Os Open VCCO 3.3V 5.5V EBGA Package
Table Electrical Characteristics over Operating Conditions Notes: Sink/Source current mode varies with slew-rate setting. Min, Fast Slew Rate: 16mA Medium Slew Rate: 11mA Slow Slew Rate: Sink current mode 20mA. Sink current GTLP mode 40mA. Source current provided external pullup resistor. VREF ±5%. pins except low-voltage input leads 5-volt-tolerant. maximum voltage applied low-voltage input pins should exceed this value, even they used single-ended I/O. outputs should terminated through resistor. GTLP outputs should terminated through termination, configured pair resistors, each net. Below this voltage, configuration data lost. Refer Table
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DY6000 Fast Field Programmable Gate Array
Clock Set/Reset Buffer Switching Characteristics
Speed Grade Description Global Clock Delay with Global Clock Delay without PLL(1, Global Clock Skew Quadrant Clock Delay with Quadrant Clock Delay(1, Quadrant Clock Skew Clock Pulse Width HIGH Clock Pulse Width Global Set/Reset Delay TQCKD TQCKS TMPH TMPL TGSR TGCKD TGCKS Symbol Units
Programmable from -3.0ns +2ns 150ps increments
Programmable from -3.0ns +2ns 150ps increments 18.7 17.0 15.3
Table Clock Set/Reset Buffer Characteristics (Input TTL) Notes: Global quadrant clock delays measured from input device flip-flop clock input. Default programming offsets actual clock delays, forcing them 0.0ns. delays specified over commercial voltage temperature range. industrial voltage temperature range, Clock delays also referred latency.
Speed Grade Description Global Clock Delay with Global Clock Delay without PLL(1, Global Clock Skew Quadrant Clock Delay with Quadrant Clock Delay(1, Quadrant Clock Skew Clock Pulse Width HIGH Clock Pulse Width Global Set/Reset Delay TQCKD TQCKS TMPH TMPL TGSR TGCKD TGCKS Symbol Units
Programmable from -3.0ns +2ns 150ps increments
Programmable from -3.0ns +2ns 150ps increments 19.6 17.9 16.2
Table Clock Set/Reset Buffer Characteristics (Input GTL, GTLP, PECL, LVDS) Notes: Global quadrant clock delays measured from input device flip-flop clock input. Default programming offsets actual clock delays, forcing them 0.0ns. delays specified over commercial voltage temperature range. industrial voltage temperature range, Clock delays also referred latency.
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
Block Switching Characteristics
Description Input Buffer Combinatorial Delay Input Flip-flop Setup Time (Global Clock) Input Flip-flop Hold Time (Global Clock) Input Flip-flop Clock Output (Global Clock) Output Buffer Combinatorial Delay Output Flip-flop Setup Time (Global Clock) Output Flip-flop Hold Time (Global Clock) Output Flip-flop Clock Output (Global Clock, Load) (2,3) Flip-flop Clock Enable Setup Time Flip-flop Clock Enable Hold Time Input Flip-flop Set/Reset Delays Output Flip-flop Set/Reset Delays Input Flip-flop Set/Reset Setup Time Output Flip-flop Set/Reset Setup Time Load)(2,3) Symbol TINPD TINIS1 TINIH1 TINCO1 TOUTIS1 TOUTIS2 TOUTIH1 TOUTCO1 TCES1 TCEH1 TGSRI TGSRO TGSRIS1 TGSROS1 Speed Grade Units
Table Input Output Buffer Parameters (I/O TTL) Notes: delays specified over commercial voltage temperature range. industrial voltage temperature range, Output delays specified with load. following delays adjust loading. Fast Slew Rate: 12ps/pF Medium Slew Rate: 25ps/pF Slow Slew Rate: 55ps/pF maximum loading outputs switching same time same direction shown below. power/ground pair provided each eight blocks device. Fast Slew Rate: 200pf between each power/ground pair Medium Slew Rate: 300pf between each power/ground pair Slow Slew Rate: 400pf between each power/ground pair Each output individual slew-rate control.
Speed Grade
Description Active Load)(2,3) Hi-Z Load)
(2,3)
Symbol T3SOE T3SOD
Units
Table Three-state Buffer Delays (I/O TTL) Notes: delays specified over commercial voltage temperature range. industrial voltage temperature range, Output delays specified with load. following delays adjust loading: Fast Slew Rate: 12ps/pF Medium Slew Rate: 25ps/pF Slow Slew Rate: 55ps/pF Each output individual slew-rate control. Should measured with output held 0.5V.
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DY6000 Fast Field Programmable Gate Array
Speed Grade Description Symbol Input Buffer Combinatorial Delay Input Flip-flop Setup Time (Global Clock) Input Flip-flop Hold Time (Global Clock) Input Flip-flop Clock Output (Global Clock) Output Buffer Combinatorial Delay Load)(2) Output Flip-flop Setup Time (Global Clock) Output Flip-flop Hold Time (Global Clock) Output Flip-flop Clock Output (Global Clock, Load) Flip-flop Clock Enable Setup Time Flip-flop Clock Enable Hold Time Input Flip-flop Set/Reset Delays Output Flip-flop Set/Reset Delays Input Flip-flop Set/Reset Setup Time Output Flip-flop Set/Reset Setup Time TCES1 TCEH1 TGSRI TGSRO TGSRIS1 TGSROS1 TINPD TINIS1 TINIH1 TINCO1 TOUTIS1 TOUTIS2 TOUTIH1 TOUTCO1 Units
Table Input Output Buffer Parameters (I/O GTLP) Notes: delays specified over commercial voltage temperature range. industrial voltage temperature range, Output delays specified with load. following delays adjust loading: GTL: 7ps/pF GTLP: 4ps/pF
Speed Grade Description Symbol Active Load)(2) T3SOE T3SOD Units
Hi-Z Load)
Table Three-state Buffer Delays (I/O GTLP) Notes: delays specified over commercial voltage temperature range. industrial voltage temperature range, Output delays specified with load. following delays adjust loading: GTL: 7ps/pF GTLP: 4ps/pF Should measured with output held 0.5V.
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DY6000 Fast Field Programmable Gate Array
Speed Grade Description Symbol Input Buffer Combinatorial Delay Input Flip-flop Setup Time (Global Clock) Input Flip-flop Hold Time (Global Clock) Input Flip-flop Clock Output (Global Clock) Flip-flop Clock Enable Setup Time Flip-flop Clock Enable Hold Time Input Flip-flop Set/Reset Delays Input Flip-flop Set/Reset Setup Time TINPD TINIS1 TINIH1 TINCO1 TCES1 TCEH1 TGSRI TGSRIS1 Units
Table Input Buffer Parameters (I/O LV-PECL LVDS) Note: delays specified over commercial voltage temperature range. industrial voltage temperature range,
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DY6000 Fast Field Programmable Gate Array
Logic Block Switching Characteristics
Speed Grade Description 3-Input AND/OR Flip-flop Delay 6-Input AND/OR Flip-flop Delay 9-Input AND/OR Flip-flop Delay 7-Input Flip-flop Delay Multiplexer Data Flip-flop Multiplexer Select Flip-flop 2-Bit-Adder/Multiplier Flip-flop (Sum) 3-Input AND/OR Combinatorial Delay 6-Input AND/OR Combinatorial Delay 9-Input AND/OR Combinatorial Delay 7-Input Combinatorial Delay 2-Bit-Adder/Multiplier Delay (Sum) Multiplexer Data Combinatorial Delay Multiplexer Select Combinatorial Delay Carry Chain Initial Delay Carry Chain Delay Bits Carry Chain Final Delay D-Flip-flop Setup Time D-Flip-flop Hold Time T-Flip-flop Setup Time T-Flip-flop Hold Time Flip-flop Clock (GCLK QCLK) Flip-flop Clock (LCLK) Set/Reset Delay Set/Reset Delay Logic Block Pass-Through Symbol TANDR3 TANDR6 TANDR9 TXORR7 TMUXR8 TMUXSR8 TADDCR TANDC3 TANDC6 TANDC9 TXORC7 TADDC TMUXC8 TMUXS8 TCRYI TCRY TCRYF TSUT TTHD TCOG TCOL TGSR TLSR TLBPT 0.35 Units
Table Logic Block Switching Parameters (Includes Routing Delays Within Routing Region(5)) Notes: delays specified over commercial voltage temperature range. industrial voltage temperature range, Refer Figure schematic logic paths described Table AND/OR combinatorial delay, combinatorial delay, comparator combinatorial delay, adder/multiplier delay, multiplexer combinatorial delay, carry chain final delay include complete path through logic block from inputs through outputs, connection buffers, routing next logic block Active Repeater. AND/OR-to-flip-flop delay, XOR-to-flip-flop delay, multiplexer-to-flip-flop delay include elements from inputs input either flip-flop. Logic block delays shown Table include connection buffer routing delays within nine-block routing region. Additional delays incurred only when must through Active Repeater reach block another routing region.
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block Corner-Turning Connection Buffer Input Connection Routing
Logic Block
Logic Block
Logic Block
delays through these elements included logic block delays Table those Table
Logic Block
Logic Block
Logic Block
Figure Logic Block Delays Includes Routing Within Region
Speed Grade Description 3-Input AND/OR Combinatorial Delay 6-Input AND/OR Combinatorial Delay 9-Input AND/OR Combinatorial Delay 7-Input Combinatorial Delay Multiplexer Data Combinatorial Delay Multiplexer Select Combinatorial Delay Flip-flop Clock-to-Out (GCLK QCLK) Symbol TANDR3 TANDR6 TANDR9 TXORR7 TMUXR8 TMUXSR8 TCOG 0.82 1.43 1.41 3.19 1.17 1.28 0.67 0.75 1.30 1.29 2.90 1.07 1.17 0.61 0.68 1.18 1.17 2.64 0.97 1.06 0.55 Units
Table Logic Block Switching Parameters (Excludes Routing Delays Within Routing Region(5)) Notes: delays specified over commercial voltage temperature range. industrial voltage temperature range, Refer Figure schematic logic paths described above table.
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DY6000 Fast Field Programmable Gate Array
Description Read/Write Operation Address Setup Time Before Clock Address Hold Time After Clock Setup Time Before Clock Hold Time After Clock Setup Time Before Clock Hold Time After Clock Clock Pulse Width HIGH Read Cycle Output Data Valid After Clock Enable/Disable SRAM Enable/Disable Buffer Delay SRAM Enable Setup with Read/Write Clock
Symbol TMPH TROS TGPD TGSS
Speed Grade 10.0
Units
SRAM Enable/Disable Hold Time with Read/Write Clock TGSH Clock Operation Read After Write Same Location TRAW Read Before Write Same Location TRBW
Table Switching Parameters Two-Port Mode Note: delays specified over commercial voltage temperature range. industrial voltage temperature range,
Speed Grade
Description Read/Write Operation Address Setup Time Before Clock Address Hold Time After Clock Setup Time Before Clock Hold Time After Clock Setup Time Before Clock Hold Time After Clock Read Cycle Output Data Valid After Clock
Symbol TROS
Units
Table Switching Parameters Single-Port Mode Note: delays specified over commercial voltage temperature range. industrial voltage temperature range,
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
Description Horizontal Active Repeater Delay Vertical Active Repeater Delay Vertical Horizontal Active Repeater Delay Horizontal Vertical Active Repeater Delay
Symbol THRPT TVRPT TVHRPT THVRPT
Speed Grade
Units
Table Active Repeater Switching Parameters Note: delays specified over commercial voltage temperature range. industrial voltage temperature range,
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DY6000 Fast Field Programmable Gate Array
Description
432-Pin EBGA
Description
GTL_REF_EXTERNAL LVPECL_REF_EXTERNAL PCKI_PCKO PLL1REST PLL2REST RESETN STRPRG SYSDONE IO_1 IO_2/PECL1N IO_3/PECL1_GPD IO_4 IO_5 IO_6 IO_7 IO_8 IO_9 IO_10 IO_11 IO_12 IO_13 IO_14/QCLK1TLN IO_15/QCLK1TL IO_16 IO_17 IO18/QCLK2TLN IO_19/QCLK2TL IO_20 IO_21 IO_22 IO_23 IO_24 IO_25 IO_26 IO_27 IO_28 IO_29 IO_30/ GCLK1N IO_31/GCLK1 IO_32 IO_33 IO_34/PECL2N IO_35/PECL2
DY6009 Ball
AJ25 AG28 AH27
DY6020 Ball
AJ25 AG28 AH27
DY6035 Ball
AJ25 AG28 AH27
DY6055 Ball
AJ25 AG28 AH27
Description
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Table 432-Pin EBGA Package Information
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
Description
IO_36 IO_37 IO_38/PECL3N IO_39/PECL3 IO_40 IO_41 IO_42/PECL4N IO_43/PECL4 IO_44 IO_45 IO_46/PECL5N IO_47/PECL5 IO_48 IO_49 IO_50 IO_51 IO_52 IO_53/WE IO_54 IO_55/RDY IO_56 IO_57/D7 IO_58 IO_59/D6 IO_60 IO_61 IO_62/QCLK1BLN IO_63/QCLK1BL IO_64 IO_65/D5 IO_66/QCLK2BLN IO_67/QCLK2BL IO_68 IO_69/D4 IO_70 IO_71/D3 IO_72 IO_73/D2 IO_74 IO_75/D1 IO_76 IO_77/D0 IO_78/TDO IO_79 IO_80 IO_81 IO_82 IO_83/M0 IO_84 IO_85
DY6009 Ball
AA31 AA28 AA29 AB30 AB28 AB29 AC29 AD31 AD29 AD28 AE28 AE31 AK26 AH25
DY6020 Ball
AA31 AB31 AA28 AA29 AB30 AB28 AB29 AC29 AD31 AD29 AD28 AE28 AE31 AF29 AH26 AK26 AH25
DY6035 Ball
AA31 AB31 AA28 AA29 AC31 AB30 AB28 AB29 AC29 AC28 AD31 AD29 AE30 AD28 AE28 AE31 AF29 AF28 AH26 AJ26 AK26 AH25
DY6055 Ball
AA31 AB31 AA30 AA28 AA29 AC31 AB30 AB28 AB29 AC30 AC29 AC28 AD31 AD30 AD29 AE30 AD28 AE29 AE28 AE31 AF29 AF28 AH26 AJ26 AK26 AH25 AK25
Description
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Table 432-Pin EBGA Package Information
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DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
Description
IO_86/M1 IO_87 IO_88/M2 IO_89 IO_90/DONE IO_91 IO_92/DOUT IO_93 IO_94 IO_95 IO_96 IO_97 IO_98 IO_99 IO_100 IO_101 IO_102 IO_103 IO_104 IO_105 IO_106 IO_107 IO_108 IO_109 IO_110 IO_111 IO_112 IO_113 IO_114 IO_115 IO_116 IO_117 IO_118 IO_119 IO_120 IO_121 IO_122 IO_123 IO_124 IO_125 IO_126 IO_127 IO_128 IO_129 IO_130 IO_131 IO_132 IO_133 IO_134 IO_135
DY6009 Ball
AL25 AJ24 AL24 AJ23 AH22 AL22 AH21 AH20 AL20 AH19 AH18 AL18 AH17 AK16 AL16 AL15 AL14 AJ14 AL13 AL12
DY6020 Ball
AL25 AJ24 AK24 AL24 AJ23 AL23 AH22 AL22 AH21 AJ21 AL21 AH20 AL20 AH19 AL19 AH18 AL18 AH17 AL17 AK16 AH16 AJ16 AL16 AL15 AJ15 AL14 AJ14 AL13 AJ13 AL12
DY6035 Ball
AL25 AJ24 AK24 AL24 AJ23 AK23 AL23 AH22 AJ22 AL22 AH21 AJ21 AL21 AH20 AJ20 AL20 AH19 AJ19 AL19 AH18 AJ18 AL18 AH17 AJ17 AK17 AL17 AK16 AH16 AJ16 AL16 AL15 AH15 AJ15 AL14 AK14 AH14 AJ14 AL13 AH13 AJ13 AL12
DY6055 Ball
AL25 AH24 AJ24 AK24 AL24 AH23 AJ23 AK23 AL23 AH22 AJ22 AK22 AL22 AH21 AJ21 AK21 AL21 AH20 AJ20 AK20 AL20 AH19 AJ19 AK19 AL19 AH18 AJ18 AK18 AL18 AH17 AJ17 AK17 AL17 AK16 AH16 AJ16 AL16 AL15 AK15 AH15 AJ15 AL14 AK14 AH14 AJ14 AL13 AK13 AH13 AJ13 AL12
Description
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Table 432-Pin EBGA Package Information
DY6000 Family Datasheet Revision
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DY6000 Fast Field Programmable Gate Array
Description
IO_136 IO_137 IO_138 IO_139 IO_140 IO_141 IO_142 IO_143 IO_144 IO_145 IO_146 IO_147 IO_148 IO_149 IO_150 IO_151 IO_152 IO_153 IO_154 IO_155 IO_156 IO_157 IO_158 IO_159/TMS IO_160/TCK IO_161/TDI IO_162 IO_163 IO_164 IO_165 IO_166 IO_167 IO_168 IO_169 IO_170 IO_171 IO_172 IO_173 IO_174 IO_175 IO_176/QCLK2BR IO_177/QCLK2BRN IO_178 IO_179 IO_180/QCLK1BR IO_181/QCLK1BRN IO_182 IO_183 IO_184 IO_185
DY6009 Ball
AJ12 AL11 AL10 AJ10
DY6020 Ball
AJ12 AL11 AH11 AJ11 AL10 AH10 AJ10
DY6035 Ball
AH12 AJ12 AL11 AH11 AJ11 AL10 AH10 AJ10
DY6055 Ball
AK12 AH12 AJ12 AL11 AK11 AH11 AJ11 AL10 AK10 AH10 AJ10
Description
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Table 432-Pin EBGA Package Information
Page
DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
Description
IO_186 IO_187 IO_188 IO_189 IO_190 IO_191 IO_192/GSR IO_193 IO_194 IO_195 IO_196/PECL6 IO_197/PECL6N IO_198 IO_199 IO_200/PECL7 IO_201/PECL7N IO_202 IO_203 IO_204/PECL8 IO_205/PECL8N IO_206 IO_207 IO_208/PECL9 IO_209/PECL9N IO_210 IO_211 IO_212/GCLK2 IO_213/GCLK2N IO_214 IO_215 IO_216 IO_217 IO_218 IO_219 IO_220 IO_221 IO_222 IO_223 IO_224/QCLK2TR IO_225/QCLK2TRN IO_226 IO_227 IO_228/QCLK1TR IO_229/QCLK1TRN IO_230 IO_231 IO_232 IO_233 IO_234 IO_235
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Description
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Table 432-Pin EBGA Package Information
DY6000 Family Datasheet Revision
Page
DY6000 Fast Field Programmable Gate Array
Description
IO_236 IO_237 IO_238 IO_239 IO_240 IO_241 IO_242 IO_243 IO_244 IO_245 IO_246 IO_247 IO_248 IO_249 IO_250 IO_251 IO_252 IO_253 IO_254 IO_255 IO_256 IO_257 IO_258 IO_259 IO_260 IO_261 IO_262 IO_263 IO_264 IO_265 IO_266 IO_267 IO_268 IO_269 IO_270 IO_271 IO_272 IO_273 IO_274 IO_275 IO_276 IO_277 IO_278 IO_279 IO_280 IO_281 IO_282 IO_283 IO_284 IO_285
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Description
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Table 432-Pin EBGA Package Information
Page
DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
Description
IO_286 IO_287 IO_288 IO_289 IO_290 IO_291 IO_292 IO_293 IO_294 IO_295 IO_296 IO_297 IO_298 IO_299 IO_300 IO_301 IO_302 IO_303 IO_304 IO_305 IO_306 IO_307 IO_308 IO_309 IO_310 IO_311 IO_312 IO_313 IO_314 IO_315 IO_316 IO_317 IO_318 IO_319 IO_320
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Description
DY6009 Ball
DY6020 Ball
DY6035 Ball
DY6055 Ball
Table 432-Pin EBGA Package Information
DY6000 Family Datasheet Revision
Page
DY6000 Fast Field Programmable Gate Array
432-Pin EBGA Internal Ground Connections
VCC_Int Balls
AK28 AJ27 AJ29 AH28 AH30 AG29 AF30
GND_Int Balls
AK27 AK29 AJ28 AJ30 AH29 AG30
VCC_I/O Balls
AL27 AL29 AL31 AK30 AJ31 AG31
GND_I/O Balls
AL26 AL28 AL30 AK31 AH31 AF31
VCC_PLL
GND_PLL
VCC_Int Balls
GND_Int Balls
VCC_I/O Balls
GND_I/O Balls
Table 432-Pin EBGA Internal Ground Connections Notes: means Connect. Both PLL1rest PLL2rest should tied ground. GTL_REF_EXTERNAL should tied ground when used. LVPECL_REF_EXTERNAL should tied when used. designates voltage pins, which tolerant.
Page
DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
240-Pin EQFP
Description
GTL_REF_EXTERNAL LVPECL_REF_EXTERNAL PCKI_PCKO PLL1REST PLL2REST RESETN STRPRG SYSDONE IO_2/PECL1N IO_3/PECL1_GPD IO_6 IO_7 IO_10 IO_11 IO_14/QCLK1TLN IO_15/QCLK1TL IO_18/QCLK2TLN IO_19QCLK2TL IO_22 IO_24 IO_26 IO_27 IO_30/GCLK1N IO_31/GCLK1 IO_32 IO_34/PECL2N IO_35/PECL2 IO_38/PECL3N IO_39/PECL3 IO_42/PECL4N IO_43/PECL4 IO_46/PECL5N IO_47/PECL5 IO_50 IO_51 IO_53/WE IO_55/RDY IO_57/D7 IO_59/D6 IO_62/QCLK1BLN IO_63/QCLK1BL IO_65/D5 IO_66/QCLK2BLN IO_67/QCLK2BL IO_69/D4 IO_71/D3 IO_73/D2 IO_75/D1 IO_77/D0
DY6009
DY6020, DY6035, DY6055
Description
DY6009
DY6020, DY6035, DY6055
Table 240-Pin EQFP Package Information
DY6000 Family Datasheet Revision
Page
DY6000 Fast Field Programmable Gate Array
Description
IO_78/TDO IO_79 IO_81 IO_83/M0 IO_84 IO_86/M1 IO_88/M2 IO_89 IO_90/DONE IO_92/DOUT IO_94 IO_95 IO_98 IO_99 IO_102 IO_103 IO_106 IO_107 IO_110 IO_111 IO_114 IO_115 IO_118 IO_119 IO_122 IO_123 IO_126 IO_127 IO_130 IO_131 IO_134 IO_135 IO_138 IO_139 IO_142 IO_143 IO_146 IO_147 IO_150 IO_151 IO_154 IO_155 IO_159/TMS IO_160/TCK IO_161/TDI IO_163 IO_166 IO_167 IO_170 IO_171 IO_174 IO_176/QCLK2BR
DY6009
DY6020, DY6035, DY6055
Description
DY6009
DY6020, DY6035, DY6055
Table 240-Pin EQFP Package Information
Page
DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
Description
IO_177/QCLK2BRN IO_180/QCLK1BR IO_181/QCLK1BRN IO_183 IO_186 IO_187 IO_190 IO_192/GSR IO_194 IO_195 IO_196/PECL6 IO_197/PECL6N IO_200/PECL7 IO_201/PECL7N IO_204/PECL8 IO_205/PECL8N IO_208/PECL9 IO_209/PECL9N IO_212/GCLK2 IO_213/GCLK2N IO_215 IO_218 IO_219 IO_222 IO_224/QCLK2TR IO_225/QCLK2TRN IO_228/QCLK1TR IO_229/QCLK1TRN IO_231 IO_234 IO_235 IO_238 IO_239 IO_240 IO_241 IO_242 IO_246 IO_250 IO_251 IO_254 IO_255 IO_258 IO_259 IO_262 IO_266 IO_267 IO_270 IO_273 IO_274 IO_275 IO_276 IO_277
DY6009
DY6020, DY6035, DY6055
Description
DY6009
DY6020, DY6035, DY6055
Table 240-Pin EQFP Package Information
DY6000 Family Datasheet Revision
Page
DY6000 Fast Field Programmable Gate Array
Description
IO_278 IO_279 IO_280 IO_281 IO_282 IO_283 IO_284 IO_285 IO_286 IO_287 IO_288 IO_290 IO_291 IO_294 IO_298 IO_299 IO_302 IO_306 IO_307 IO_310 IO_314 IO_315 IO_318
DY6009
DY6020, DY6035, DY6055
Description
DY6009 Lead DY6020, DY6035, DY6055 Lead
Table 240-Pin EQFP Package Information
Page
DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
240-Pin EQFP Internal Ground Connections
Pins
Ground Pins
Ground
Table 240-Pin EQFP Internal Ground Connections Notes: means Connect. Both PLL1rest PLL2rest should tied ground. GTL_REF_EXTERNAL should tied ground when used. LVPECL_REF_EXTERNAL should tied when used. designates voltage pins, which tolerant.
DY6000 Family Datasheet Revision
Page
DY6000 Fast Field Programmable Gate Array
Package Drawings
432-Pin EBGA
BALL CORNER
38.1
1.27 TYP. 38.1
.975
UNIT SHOWN FROM BALL ARRAY SIDE (Dimensions
0.91 1.54
0.63
SIDE VIEW Figure Package Drawing 432-pin EBGA
Page
DY6000 Family Datasheet Revision
DY6000 Fast Field Programmable Gate Array
240-Pin Thermal Enhanced EQFP
32.00
View
Dimension Millimeters Lead Pitch 0.50
Stand-Off 0.25
Metal Heat Sink
Side View
0.13 0.27
Figure Package Drawing 240-pin EQFP
DY6000 Family Datasheet Revision
Page
34.4 35.2
DY6000 Fast Field Programmable Gate Array
Ordering Information
Order codes shown below.
DY6009BG432FC
Prefix Prefix Device 6009 9,000 Gate Device 6020 20,000 Gate Device 6035 35,000 Gate Device 6055 55,000 Gate Device Package Type EBGA (Enhanced Ball-Grid Array) EQFP (Enhanced Quad Flat Pack) Count Speed Grade Product Specifications Temperature Range Commercial Industrial DynaChip, DY6000, DL5000, FFPGA, DynaTool registered trademarks DynaChip. These products covered following U.S. Patents: 5355035, 5397943, 5406133, 5497108, 5504440, 5570059, 5614844, 5654665, 5668495, 5742179, 5744981, 5808479. DynaChip Corporation 1255 Oakmead Parkway Sunnyvale, 94086-4040 Phone: 408-481-3100 Fax: 408-481-3136 Email: support@dyna.com http://www.dyna.com information contained this document subject change without notice.
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DY6000 Family Datasheet Revision

FAST Field Programmable Gate ArrayPredictable, Fast, Patented Active R

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