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ATJ2085
Actions
2085
PRODUCT
(Version 08/2004)
Actions Semiconductor Co.,
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ATJ2085
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Declaration
contents this document protected copyright reproduction whole part prohibited without prior written consent Actions Semiconductor Co., Ltd. Other product names used this publication identification purposes only trademarks registered trademarks their respective companies. information presented this document does form part quotation contract, believed accurate reliable. Actions Semiconductor Co., Ltd. reserves right make changes specifications product descriptions time without notice, discontinue make changes products time without notice. Actions Semiconductor Co., Ltd. specifically disclaims liability consequence application product circuit. Publication thereof does convey imply license under patent other industrial intellectual property rights. Actions Semiconductor Co., Ltd. Licensee Thomson Licensing S.A. approved distribute these semiconductor devices using MPEG Layer-3 ("mp3") coding technology ("mp3 decoder chips") Thomson Licensing S.A. Supply this product does convey license imply right distribute content created with this product revenue-generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications (via Internet, intranets and/or other networks), other content distribution systems (pay-audio audio-on-demand applications like) physical media (compact discs, digital versatile discs, semiconductor chips, hard drives, memory cards like). independent license such required. details, please visit http://mp3licensing.com. Actions Semiconductor Co., Ltd. Licensee Microsoft Licensing, Actions Semiconductor Co., Ltd. approved distribute these semiconductor devices using Windows Media Audio ("wma") coding technology ("wma codec chips") Microsoft Licensing, This product includes technology owned Microsoft Corporation cannot used distributed without license from Microsoft Licensing,
ADDITIONAL SUPPORT
Additional product company information obtained going Actions website www.actions.com.cn.
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CONTENTS
Declaration CONTENTS.2 Description Features Description Sort Number Function Description Functional Block Diagram.10 Core Core. Controller General Purpose Ports RTC/CTC/Watch Timer.13 Oscillator/PLL.13 Power Management Unit (PMU).14 ADC.15 4.10 DAC.16 4.11 Headphone Driver 4.13 External Memory Interface 4.14 Interface 4.15 2.0(FS) SIE.19 4.15.1 Hard Core 4.15.2 Interrupts.20 4.16 Interface.20 Electrical Characteristics.20 Absolute Maximum Ratings Capacitance Characteristics.21 Characteristics 5.4.1 test input waveform
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5.4.2 test output measuring points 5.4.3 Reset Parameter 5.4.4 Initialization Parameter.22 5.4.5 GPIO Interface Parameter.23 5.4.6 Ordinary Parameter 5.4.7 External System Parameter 5.4.8 Operation.25 5.4.9 Converter Characteristics 5.4.10 Headphone Driver Characteristics Table.27 5.4.11 Driver Parameter.29 MCU/DSP Dissipation (IVDD Frequency).30 Dissipation Dissipation Recommended Soldering Conditions Soldering Conditions.31 Precaution against Semiconductors Handling Unused Input Pins CMOS.31 Status before Initialization Devices Package Drawings
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ATJ2085
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Description
ATJ2085 single-chip flash-based digital music player. includes audio decoder with high performance DSP, ADPCM record capabilities interface downloading music uploading voice recordings. ATJ2085 also provides interface flash memory, LED, button switch inputs, headphone, microphone, radio input control. ATJ2085's programmable architecture supports MP3, other digital audio standards. devices like USB-Disk, ATJ2085 mass storage slave device personal computer system. power consumption allows long battery life, efficient flexible on-chip DC-DC converter allows many different battery configurations, including 1xAA, 1xAAA, 2xAA, 2xAAA Li-Ion. Built-in Sigma-Delta headphone driver directly drive impedance headphones. includes inputs both Microphone Analog Audio support voice recording radio integration features. Thus, ATJ2085 provides true `ALL-IN-ONE' solution that ideally suited highly optimized digital audio players with mass storage function.
Features
MPEG1/2/2.5 Audio Layer decoder Support Decoder Digital Voice Recording with Actions Speech Algorithm bits Core with memory on-chip Debug Support Unit (DSU) Integrated 8-bit with External 2(cs) 64M/128M/256M/512M/1G/2G bytes Nand type Flash accessed Built-in DMA, (Counter/Timer Controller) interrupt controller Energy saving dynamic power management (PMU) Support 2.0FS, Write speed(Max): 955k byte/s; Read speed(Max): 1033k byte/s Build Stereo 18-bit Sigma-Delta Build Scan Circuit (3*3) GPIO interface supports Master/Slave mode, with changeable slave address Support external 8080 Interface driver Support Radio input levels volume control Support Stereo 16-bit Sigma-Delta Microphone/FM Input, sample rate
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ATJ2085 8/12/16/22/24/32/48KHz
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24.576MHz(TYP), 60MHz SNR: 90dB (DAC TYP) Headphone driver output 2x11mW Ohm(TYP) Operating Voltage: 3.0V(TYP), Core: 2.0V(TYP) Standby Leakage Current: VCC: 35uA@3.0V(TYP) VDD: 110uA@2.0V(TYP) Power Consumption, designed greater than (TYP) hours operation single battery life. (<65mW typical decoder solution; <90mW typical decoder solution) 64-pin (10x10mm) LQFP package
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Description
Sort Number
Name Type Driver 1.9mA Driver Reset Default Short Description
GPIO_G0 RESETVCC USBDUSBD+ PAVCC
Bit0 General purpose port System reset input (active low) Digital power Digital ground data minus data plus Power supply power amplifier(two bypass
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DATA SHEET capacitors 47uF 0.1uF)
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AOUTR AOUTL PAGND VRDA MICIN VMIC FMINL FMINR AGND AVCC VREFI AVDD VDDIO
Int. right channel analog output Int. left channel analog output Power amplifier ground Bypass capacitor (typ 0.47uF) Microphone pre-amplifier input (0.8V-2.2V) Power supply microphone, 2.2V output Left channel line input Right channel line input Analog ground Analog power Voltage reference input (1.5V) Analog power Power output (connect through (typ) resistance) Power (When Batteries mode, connect BAT. Others mode Connect VCC) resolution input, 0.8-2.2V, 8Bit High frequency crystal input High frequency crystal output Battery select. LOne Battery HTwo Batteries Int. DC-DC control pin. Disable DC-DC. Enable DC-DC. Bit0 General purpose port Bit0 scan circuit input Bit2 General purpose port Bit1 General purpose port Bit1 scan circuit input Ground Battery monitor DC-DC
LRADC HOSCI HOSCO BATSEL
DCDIS GPIO_B0 KEYI0 GPIO_C2 GPIO_B1 KEYI1 LXVDD
1.9mA Driver 1.9mA Driver 1.9mA Driver
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ATJ2085 NGND LXVCC GPIO_B2 KEYI2 CE3CE2CE1VDD GPIO_B4 KEYO0 GPIO_B5 KEYO1 GPIO_B6 KEYO2 GPO_A1 ICECK GPO_A2 ICEDO GPO_A0 ICEDI ICEENICERSTVCC 1.9mA Driver 1.9mA Driver 1.9mA Driver 1.9mA Driver 3.5mA Driver 3.5mA Driver 3.5mA Driver
DATA SHEET NMOS ground DC-DC Bit2 General purpose port Bit2 scan circuit input 8080 interface chip enable Nand Flash chip enable (optional)
Actions
Boot Nand Flash chip enable (must connected Nand Flash) Digital power Bit4 General purpose port Bit0 scan circuit output Bit5 General purpose port Bit1 scan circuit output Bit6 General purpose port Bit2 scan circuit output Bit1 General purpose output port Clock input debug Bit2 General purpose output port Data output from debug Bit0 General purpose output port Data input debug enable (active low) reset (active low) Digital power Ground Bit7 ext. memory data Bit6 ext. memory data Bit5 ext. memory data Bit4 ext. memory data Bit3 ext. memory data Bit2 ext. memory data Bit1 ext. memory data Bit0 ext. memory data
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ATJ2085 MWRMRDCLE GPIO_C1 SIRQ63 Notes: PWR-Power Supply O-Output SCU-SCHIMITCU GPIO_C0 1.9mA Driver 1.9mA Driver
DATA SHEET Ext. memory write strobe Ext. memory read strobe
Actions
Command latch enable NAND type flash Address latch enable NAND type flash Bit1 General purpose port Serial data (Open drain) Ext. interrupt request input Bit0 General purpose port serial clock (Open drain) Digital power
AI-Analog Input I-Input
AO-Analog Output BI-Bi-direction
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Function Description
Functional Block Diagram
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Core
ATJ2085 integrates 8-bit with on-chip support. Instruction compatible with Z80. Process capability controlled software MHz. ATJ2085 includes Kbytes on-chip SRAM 29Kbytes on-chip ROM. following flag chip memory mapping.
Core
24-bit Harvard architecture with on-chip support built works with memory word length bits. ATJ2085 16KB*24bit Program Memory (PM) (16KB-256)*24bit Data Memory (DM). Memory-Mapped Register includes interface. Process capability controlled software MIPS.
Controller
ATJ2085 supports kinds channels. DMA1/2 support Data exchange Memory last DMA.
General Purpose Ports
ATJ2085 GPOA, GPIOB, GPIOC, GPIOG. They have different functions different modes.
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ATJ2085 Function GPIO GPOA GPIOB (Default)
DATA SHEET (Function
Actions
When used, GPO_A[2~0] Pins ICEDO, ICECK ICEDI; Otherwise GPO_A[2~0] used output function.
When choosing Keyboard function, GPIOB[2~0] Pins KEYI[2~0], GPIOB[6~4] KEYO[2~0]; when choosing Keyboard function,
GPIOB[6-4:2-0]When keyboard function enables, while some [2~0] used GPIOB, relative should masked.
When function enables, used I2C_SCL. When GPIO_C0, then enabled simultaneously GPIOC Only used GPIOC [3~0] When function enables, used I2C_SDA. When external interrupt enables, SIRQ-; when GPIO_C, multiple functions enabled
simultaneously. GPIOG GPIOG[0] when GPIO_C2
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RTC/CTC/Watch Timer
24-bit counter with following function: Time Alarm Timer counter whose clock source different with RTC's. Watchdog from 176-milisecond 180-second with different step.
Oscillator/PLL
ATJ2085 supports 24.576MHz crystal, which system clock source. jitter referenced 24.576MHz used generate clock serial communication protocols such USB, UART, etc. clock used serial communications 48MHz generates frequency multiple 48MHz support serial communication simultaneously. Another referenced 24.576MHz used generate 22.5792MHz sample rate 44.1K/22.05KHz/11.025KHz.
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Power Management Unit (PMU)
consists DC-DC converter, regulator battery monitor. ATJ2085, there DC/DC converters liner regulator. DC/DC converter power supply another VDD. liner regulator power supply when battery mode other conditions where need less external components. ATJ2085, default value 3.0V 2.0V. regulator's default output 2.0V; three values controlled Registers. from 2.8V 3.3V; from 1.6V 2.3V; regulator same VDD. ATJ2085 supports one-battery mode, two-battery mode, power supply power line-in.
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There pins mode configurations. "DCDIS"; other "BATSEL", truth table follow: DCDIS BATSEL DC/DC1(VDD) DC/DC2(VCC) Regulator Mode descriptions battery with more external
components, more efficiency battery battery with less external
components, less efficiency power power line-in
"DCDIS" on-chip pull down resistor. There built-in super speed resolution battery monitor ATJ2085. level minimum battery voltage warning configured registers; range from 0.98V 1.22V. voltage level resetting system controlled register; range from 0.9V 1.14V.
There Analog-to-Digital Converters integrated ATJ2085: 16-bit MIC/FM Input/Line Input, 8-bit Line Controller, 4-bit Battery Monitor
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internal microphone amplifier gain recording. VMIC power supply (2.2V) microphone. audio bits sigma delta Analog-to-Digital Converter. input source selected from amplifier external line-in, FIFO. ATJ2085 8-bit switched-capacitor Analog-to-Digital Converter (SARADC). input source LRADC pinfor remote control, input range 0.8-2.2V, remote controlonly most significant bits used
4.10
ATJ2085's DAC3 on-chip Sigma-Delta Modulator, composed high performance DAC. analog block refers following diagram. interface supports 4-level play back FIFO 20-bit data channel) variable sample rates, such 48K/ 44.1K 32K/ 24K/ 22.05K/ 16K/ 12K/ 11.025K/ 8KHz. on-chip PLL2 used generate 22.5792MHz from 24.576MHz support 44.1K/2 2.05 11.025KHz with 256xFS clock over-sampling, while 24.576MHz supports 48K/ 32K/ 24K/ 16K/ 12K/ 8KHz with 256XFS over-sampling.
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4.11 Headphone Driver
output power ATJ2085's amplifier 13mW(each channel).
4.12 Scan Interface
When scan circuit enabled, ATJ2085 will scan keyboard periodically. drives scan pulse turn. When pressed, corresponding will send scan pulse. When pressed, connecting will found level. There internal 8-bit registers value latch scan. only another register (Key Scan Data Register) access value. Those internal registers mapped into this register, internal pointer used point current register return scan data when read. write this register will clear internal register, pointer will increase point next register after read performed.
4.13 External Memory Interface
ATJ2085 support NAND type flash from bytes.
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following NAND flash Read/Write timing. Read:
Write:
4.14 Interface
ATJ2085's configured either master slave device. master mode generates clock (I2C_SCL) initiates transactions data line (I2C_SDA). Data byte oriented. Multi-Master mode, 10-bit address Hi-speed mode supported. I2C_Bus_Specification_1995 detailed information.
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Parameter period Clock time Clock high time Clock rise time Clock fall time data setup time data hold time
Symbol fSCL tLOW tHIGH tSU:DAT tHD:DAT
Typical
Unit
4.15 2.0(FS)
Communications with host made speed-programmable interface (compliant with SPEC 2.0FS). Such communications, including file downloading uploading, audio/video data transferring, etc., depend different implementations meet different requirements. endpoints provided. Endpoint endpoint capable isochronous transfer mode, this case, maximum packet size 1023, according SPEC.
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These endpoints employ independent FIFO bulk isochronous transfers. Endpoint endpoint have bytes maximum packet size. There interrupt requests each endpoint respectively. Generally, this setting should satisfying most practical needs. 4.15.1 Hard Core block includes function with upstream port. port interfaces micro-controller through programmable-speed serial interface engine (SIE). allows micro-controller communicate with host. 4.15.2 Interrupts groups interrupt requests used notify micro-controller that there some event pending handled. Global Interrupt group, other Endpoint Interrupt group. Whenever interrupt generated, will send pulse micro-controller. will invalidated until pending interrupts cleared.
4.16 Interface
ATJ2085 used controller with Philips FM5767 module. 2-wire 3-wire also used control module.
Electrical Characteristics
Absolute Maximum Ratings
Parameter Supply voltage Symbol Typical 2.0V 3.0V Rating -0.5 +2.7 -0.5 +3.6 -0.5 +3.9 -0.5 VCC+0.6 +150 Unit
Input voltage Storage temperature Note:
Tstg
(Operating Temperature) short-circuit more output pins simultaneously. even above parameters exceeds absolute maximum ratings even momentarily, quality product degraded. absolute maximum ratings, therefore, specify
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value exceeding which product physically damaged. product well within these ratings. specifications conditions shown Characteristics characteristics ranges normal operation quality assurance product.
Capacitance
Parameter Input capacitance capacitance Symbol Condition Unmeasured pins returned MIN. MAX. Unit
Note:
Characteristics
Parameter High-level output voltage Low-level output voltage High-level input voltage Low-level input voltage Input leakage current Output leakage current GPIO Drive Symbol Condition MIN. TYP. Unit
Idrive1 Idrive2
VCC, VCC, GPOA0,GPOA1,GPOA2 Other GPIO Full speed mode (MCU
0.7*VCC -0.3
2.60 1.25
0.4VCC
IVDD Supply Current (Two battery mode) Ivcc
24.576MHz internal SRAM, 36MIPS) Standby mode Full speed mode (MCU 24.576MHz internal SRAM, 36MIPS) Standby mode
Notes
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+70, IVDD total power supply current power supply. IVDD applied LOGIC, blocks. IVCC total power supply current power supply. IVCC applied USB, blocks.
Characteristics -10to +70,
5.4.1 test input waveform
5.4.2 test output measuring points
5.4.3 Reset Parameter Parameter Reset input low-level width Symbol tWRSL Condition RESET# MIN. MAX. Unit
5.4.4 Initialization Parameter Parameter Data sampling time (from RESET#) Output delay time (from RESET# Symbol 61.04 Condition MIN. MAX. 61.04 Unit
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ATJ2085 5.4.5 GPIO Interface Parameter Parameter Input level width GPIO input rise time GPIO input fall time Output level width Symbol tGPIN tGPRISE tGPFALL tGPOUT
Actions
Condition Normal operation
MIN. fMCUCLK
MAX.
Unit
fMCUCLK
Notes: fMCUclk frequency that running upon. Input level width
Input rise/fall time
Output level width
5.4.6 Ordinary Parameter Parameter
Data access time (from address) Data access time (from CEx#
Note
Symbol tACC
Condition HOSC=24.576MHz HOSC=24.576MHz HOSC=24.576MHz HOSC=24.576MHz
MIN.
MAX.
Unit
Note
Data input setup time Data input hold time
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5.4.7 External System Parameter
Parameter Address setup time command signal)Note Address hold time (from command signal)Note Data output setup time command signal)Note Data output hold time(from command signal)Note Data input setup time command signal)Note Data input hold time(from command signal)Note
Symbol tXAS tXAS tXAH tWXDS tWXDH tRXDS tRXDH
Condition Memory Read Memory Write
MIN. 0.5T 1.5T 0.5T
MAX.
Unit
0.5T
Notes: MRD#, MWR# called command signals External System Interface. (ns) fMCUCLK
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ATJ2085 5.4.8 Operation Instruction Fetch Timing
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Memory Read Timing
Memory Write Timing
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ATJ2085 Read Timing
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Write Timing
DMA1/2 Timing
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ATJ2085 Read/Write Timing
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5.4.9 Converter Characteristics +70, 3.0V, Sample Rate=32KHz) Characteristics Dynamic range Total Harmonic Distortion Noise Frequency Response (20-13KHz) Full Scale Input Voltage(Gain=0dB) Note: +70, 3.0V. Sample Rate=32 5.4.10 Headphone Driver Characteristics Table Characteristics Dynamic Range dBFS Input Total Harmonic Distortion Noise Frequency Response 20-20KHz Output Common Mode Voltage Full Scale Output Voltage Inter channel Isolation (1KHz) Inter channel Gain Mismatch(1KHz) Note:1. =-10 +70, Sample Rate=32 KHz. 0.025 ±0.6 Unit Typ. Unit mVpp
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ATJ2085 Bias Current=26uA. Volume Level=0x1F.
Actions
Frequency Response Diagram Headphone Driver
Action iconductor PAFrequencyR esponse(linein->PA)@ 1Vpp 02/09/04 14:24:58
Sweep race olor
LineSty Thick Data
Comment
agenta olid olid
Left Load=100uF*100Kohm nlr.A Left Load=100uF*32ohm nlr.A Untitled1
Amplitude Diagram Headphone Driver
Actions Semiconductor
-100
THD+N Amplitude (linein->PA)@ 1KHz Load=32ohm
02/09/04 10:19:46
200m
400m
600m
800m
Sweep Trace Color
Line Style Thick Data
Axis Comment Right Channel Left Channel Untitled1
agenta Solid Blue Solid
Anlr.THD+N Ratio Left Anlr.THD+N Ratio Left
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ATJ2085 5.4.11 Driver Parameter
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Parameter Data access time(write) Data access time (Read) Write cycle time Read cycle time Data setup time Data hold time Address setup time Address hold time Read access time Data input hold time
Symbol tPW80(W) tPW80(R) tCY80(W) tCY80(R) tDS80 tDH80 tAS80 tAH80 tACC80 tOD80
Condition HOSC=24.576mHZ HOSC=24.576mHZ HOSC=24.576mHZ HOSC=24.576mHZ HOSC=24.576mHZ HOSC=24.576mHZ HOSC=24.576mHZ HOSC=24.576mHZ HOSC=24.576mHZ HOSC=24.576mHZ
Unit
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MCU/DSP Dissipation (IVDD Frequency)
Dissipation
(VBAT=1.5V, under reset, VDD=2.0V, runs internal SRAM) Clock Source 32.768KHZ Divisor factor /(1-1024) 24.576MHz /128 /256 /512 /1024 350uA 5.9mA 3.3mA 1.9mA 1.2mA 1.9mA 0.7mA 0.6mA 0.58mA 0.56mA 0.55mA 0.54mA IVDD(Max)
Dissipation (VBAT=1.5V, LOSC, VDD=2.0V, =3.0V)
Speed (MIPS) IVDD (Max) 3.49mA VDD=2.0V 6.52mA VDD=2.0V 11.24mA VDD=2.0V 16.24mA VDD=2.0V 21.08mA VDD=2.0V 28.5mA VDD=2.3V 33.6mA VDD=2.3V 38.7mA VDD=2.3V
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Recommended Soldering Conditions
Soldering Conditions
Soldering Conditions Surface-Mount Devices Soldering Process Soldering Conditions Peak package's surface temperature: Infrared reflow Reflow time: seconds less (210or more) Maximum allowable number reflow processes: Exposure limit: days hours pre-baking required afterward). Partial heating method Terminal temperature: less Heat time: seconds less (for side device) Note: Maximum number days during which product stored temperature relative humidity less after dry-pack package opened. Caution: apply more different soldering methods chip (except partial heating method terminal sections).
Precaution against Semiconductors
Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
Handling Unused Input Pins CMOS
connection CMOS device inputs cause malfunction. connection provided
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input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
Status before Initialization Devices
Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
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Package Drawings
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Actions Semiconductor Co., Ltd.
Address: 15-1, NO.1, Road, Tangjia, Zhuhai, Guangdong, China Tel: +86-756-3392353 Fax: +86-756-3392251, 3392252, 3392253 Post code: 519085 http:// www.actions.com.cn Business Email: mp-sales@actions.com.cn Technical Service Email: mp-cs@actions.com.cn
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