The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

Fast Field Programmable Gate ArraySystem Clock Rates 9,000 105,000 Usa


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



DL6000Family
Fast Field Programmable Gate ArraySystem Clock Rates 9,000 105,000 Usable Gates Synchronous Dual-port with Access Time Analog PLLs Clock Multiplication, Division Locking LV-TTL Interface Levels LVDS Compatible Inputs Differential Single-Ended LV-PECL Inputs Input Register Setup Time 33/66 Compatible Partial Reconfiguration Clock Trees with Skew Volt Operation Volt Tolerant Patented Active Repeater Architecture In-System Reprogrammability (ISP) JTAG Support Output Slew Rate Control Fully Automatic Implementation With DynaTool
Introduction
DL6000 DynaChip's second generation Fast Field Programmable Gate Array family. Built deep sub-micron CMOS process, this family supports applications with system clock rates MHz.
DL6000 family features DynaChip's patented Active Repeater Architecture. This results extremely short routing delays allowing these devices system frequencies well above conventional FPGAs. support fast data rates high-speed applications, every programmed LV-TTL interface levels. DL6000 family devices contain synchronous with access time. These flexible structures operate true dual single port modes ideal applications that require fast access memory.
High operating frequencies, on-chip RAM, fast compatibility make these devices ideal high-speed telecommunications, datacommunications, graphics emulation applications.
Applications Examples
Telecommunication Datacommunication High Speed Graphics ASIC Emulation
DL6000 features SRAM-based programming allowing devices configured in-circuit reprogrammed on-the-fly. They support dynamic single-block reconfiguration enabling portion device reprogrammed without affecting operation remaining logic. Device DL6009 DL6020 DL6035 DL6055 DL6080 DL6105 Gates 9,000 20,000 35,000 55,000 80,000 105,000 Logic Blocks 1,024 1,600 2,304 3,136 User Bits 8,192 18,432 32,768 51,200 73,728 100,352 Flip Flops 1,536 2,560 3,840 5,376 7,168 Clock Trees Blocks
Table DL6000 Family
Datasheet
September 1998
DL6000 Fast Field Programmable Gate Array
Table Contents
Features Applications Examples. Introduction Performance Examples High Performance Active Repeater Technology Top-Level Architecture Routing Architecture Input/Output Blocks LVDS Logic Block Clock Distribution Phase Lock Loops Power Consumption Configuration Configuration Modes Serial Configuration Modes Microprocessor Configuration Modes. Dynamic Reconfiguration Using Full Chip Reset Partial Reprogramming Readback Configuration Clock Frequencies Mode Settings Flip Flop Initialization Configuration Schematics Serial PROM Configuration Mode Microprocessor Configuration Mode. Programming Chains Bitstream Size Configuration Pins JTAG Product Specifications Maximum Ratings. Operating Conditions Characteristics Over Operating Conditions Clock Set/Reset Buffer Switching Characteristics Input Output Block Switching Characteristics Three-state Buffer Characteristics. Logic Block Switching Characteristics Switching Characteristics Programmable Interconnect Characteristics Description 352-pin SBGA DL6035 208-pin DL6035. 352-pin SBGA DL6020 352-pin SBGA DL6009 Package Drawings 352-pin SBGA. 208-pin Thermal Enhanced PQFP (PQ208) Ordering Information.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Performance Examples
DL6000 family with DynaChip's patented Active Repeater Architecture supports high-speed applications with clock rates MHz. following table shows performance various size functions implemented DL6035*. Circuit
8-bit Fully Synchronous, Loadable Counter 16-bit Fully Synchronous, Loadable Counter 32-bit Fully Synchronous, Loadable Counter 64-bit Fully Synchronous, Loadable Counter 32x32 RAM-based FIFO 128x32 RAM-based FIFO 64-bit Shift Register Maximum chip-to-chip performance**
DL6035
Logic Block Count
Table Performance Various Applications Based speed grade over commercial voltage temperature range. With load fast slew rate.
High Performance Active Repeater Technology
enabling technology behind DynaChip's Fast Field Programmable Gate Arrays Active Repeater. Conventional FPGA devices pass gates create programmable interconnections. These pass gates like series resistors with distributed capacitance ground. Nets formed these pass gates slow down dramatically number programmable connections increases. This results long, unpredictable delays, especially nets that have travel long distance drive large number loads. contrast, DynaChip uses Active Repeaters create programmable interconnections. shown figure these repeaters buffer signal every interconnection point isolate capacitance rest net. result fast, predictable performance even long, high fanout nets.
Logic Block
Figure DynaChip's Active Interconnect
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
FPGA devices that pass-gate based interconnect, delays increase quadratically with number programmable interconnect points, shown figure This results performance bottleneck that especially troublesome nets that have travel long distance drive large number loads. devices that Active Repeaters interconnect, delays linear affected fanout. result much higher performance greater predictability.
Interconnect Delay
Connections
Pass-gate Interconnect Active Repeater
Figure Active Repeatervs. Pass Gate Delays
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Top-Level Architecture
very level, DynaChip devices look like conventional FPGA devices. shown figure input/output blocks surround edges device, array logic blocks fill interior routing tracks distributed between rows columns logic blocks. difference DynaChip's architecture lies routing resources.
Input Output Blocks Logic Blocks
Routing Tracks
Figure High Level View Architecture
Routing Architecture
DynaChip's architecture optimized Active Repeater technology. shown figure interconnect resources consist series vertical horizontal wires that make routing region. Buffers that drive these wires turned create required connections. Since every buffer drives fixed load, been carefully optimized provide maximum performance. fixed load nature interconnect results completely predictable performance since delay through buffer fixed. Routing regions connected with Active Repeaters. After passing through Active Repeater, signals available throughout next routing region. DL6000 family, each routing region columns wide rows tall. location Active Repeaters staggered that each logic block region.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Active Repeater
Connection Buffer
Input Connection
Each vertical line shown represents actual vertical lines Each horizontal line shown represents actual horizontal lines Figure Routing Architecture
This architecture results completely deterministic performance within routing region. logic block delays specified this datasheet include delay connection buffers routing within region (refer table logic block delays). shown figure this architecture allows logic block drive blocks column routing region with additional routing delays. This allows even high fanout nets have extremely high performance.
Logic Block Logic Block Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Logic Block
Figure Routing Region With Interconnect Delay
signals that drive blocks next region, fixed delay through Active Repeater added logic block delay. These Active Repeater delays only routing delays device their performance completely specified this datasheet (refer table Active Repeater delays).
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
shown figure logic block output drive logic blocks with just Active Repeater delay. This allows structures with gates logic 1,056 bits implemented with just routing delay. With Active Repeater delays, logic block output drive logic blocks. This allows 1,460 gates logic 2,336 bits with just routing delay. routing delays device fixed affected fanout net.
LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
LOGIC BLOCK
Source block Access with repeaters Access with repeater Access with repeaters
Figure Logic Block Reached With Repeaters
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Input/Output Blocks
Every input/output block DL6000 independently interface levels. clock inputs also single-ended differential LVPECL levels. When differential LV-PECL, inputs compatible with LVDS. these inputs used clock signals, they used general purpose inputs. When mode, input/output blocks 100% compliant with 33Mhz busses. Each input/output block configured input, output bi-directional signals. Each block flip flops that used register input output signals. Each flip flop clock enable input. Clock signals flip flops input/output blocks sourced from either global clock pins either quadrant clock pins that region. Each output individual slew rate control 3-state capability. 3-state enable each output controlled individually. Each input/output block contains dedicated JTAG Boundary Scan logic compatible with IEEE specifications.
Input/ Output From Global Set/Reset Line
Bidirectional Boundary Scan Circuit From Global Clock Array From Global Clock Array From Quadrant Clock Array From Quadrant Clock Array
Vertical Horizontal Routing Channels (Input Data)
From Horizontal Vertical Routing Channels (Output Enable) From Global Set/Reset Line From Horizontal Vertical Routing Channels (Output Data) From Horizontal Vertical Routing Channels (Clock Enable)
Output Slew Rate Control
From Global Clock Array Bidirectional Boundary Scan Circuit From Global Clock Array From Quadrant Clock Array From Quadrant Clock Array
Figure Input/Output Block
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
LVDS
When differential LV-PECL levels, clock inputs interface LVDS levels using shunt resistor shown following figure. these inputs used clock signals, they used general purpose inputs.
3.3V LVDS LV-PECL 3.3V
Figure Interfacing LVDS LV-PECL
Logic Block
logic block DL6000 extremely flexible implement wide variety functions. Each block inputs. inputs dedicated clocking reset signal. remaining general purpose inputs logic block. Each logic block contains combinatorial logic, flip flops. combinatorial section contains flexible building blocks optimized high utilization. Structures like multiplexers, AND/OR gates, comparators arithmetic functions automatically mapped these resources DynaChip Development System. multiplexer allows outputs combinatorial logic exit block directly serve inputs flip flops.
Local, Global Quadrant Clock Local Global Set/Rst
AND/OR ARITHMETIC 32-bit
COMB
Figure Logic Block
Figure shows detailed diagram logic block DL6000. logic block contains sections that optimized AND/OR logic, multiplexers, arithmetic logic RAM. logic block inputs have polarity control allowing signals inverted they enter block. Each logic block contains storage elements that configured D-type (toggle) flip flops. flip flops share common clock that driven
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
device's global quadrant clocks local interconnect. clock input each logic block polarity control allowing flip flops triggered from either clock edge. flip flops also share common set/reset signal that driven device's global set/reset local interconnect. Each flip flop configured have either reset capability. set/reset input each logic block polarity control allowing active high active operation. Each logic block outputs that driven combinatorial logic, flip flops.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Global
GCLK GCLK GCLK GCLK
MUX3
Clock Enable
LCLK
MUX5
AND/OR Logic
MUX11
MUX17
MUX24
OR23
Multiplexer Logic
MUX28
Arithmetic Logic
Logic
A0(0) A0(1) A0(2) A0(3) A1(0) A1(1) A1(2) A1(3) A4/W
SRAM
(Rout1)
Polarity Control
(Rout0)
Programmable Point
64,65,66
Figure Logic Block Resources
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Each logic block DL6000 family devices contain 32-bit fully synchronous configurable RAM. configured 32x1 dual port RAM, 32x1 single port 16x1 RAMs with independent data addresses. "self-timed" which makes both read write operations fully synchronous. user only needs concerned with maintaining setup hold times inputs with respect clock. This includes data address inputs. There need standard timing parameters such pulse width', `write cycle' `read cycle'. From timing standpoint, treated just like flip-flop. includes clock generator cell latches data inputs outputs. Upon receipt LOW-to-HIGH transition clock input, clock generator creates internal signals RAM. During write cycle, clock generator creates pulse latch write enable, data address inputs. During read cycle pulse generated latch addressed data output latches. Both read write operations completed upon single low-to-high transition clock. This true both single dual port modes. Timing diagrams operations shown figure
Write Cycle Addresses Data
Read Cycle Addresses tROS Output
Figure Read/Write Cycle Timing
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
CLOCK GENERATOR
A[0:3]
Figure 32x1 Single Port
Figure shows configuration 32x1 Single Port RAM. There bits address A4), data input (D), write enable (WE) clock input. inputs totally synchronous clock. Just like edge triggered flip flop, only timing requirement that setup hold times must obeyed. When HIGH, write mode. Data presented input will written location specified addresses During write cycle, output unknown state. When LOW, read mode. data stored location specified appears output after rising edge clock. This single clock operation. setup before rising edge clock data stored appears after rising edge clock.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
CLOCK GENERATOR
A1[0:3]
A0[0:3]
Figure Dual 16X1 Single Port
Figure shows configuration dual 16X1 single port RAM. cell contains separate 16X1 RAMs where each their address data pins. dual inputs. There bits address (A00 A03) data input (D0) separate bits address (A10 A13) separate data input (D1) Both RAMs share same write enable (WE) clock input. inputs totally synchronous clock. Just like edge triggered flip flop, only timing requirement that setup hold times obeyed. Operation RAMs identical that 32X1 single port. When HIGH, RAMs write mode. Data presented input will written location specified addresses while data presented input will written location specified addresses A13. During write cycle, outputs RAMs unknown state. When LOW, RAMs read mode. After rising edge clock, data stored location specified appears output data stored location specified appears output This single clock operation.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
CLOCK GENERATOR
AW[0:3]
AR[0:3]
Figure 32x1 Dual Port
Figure shows configuration 32x1 Dual Port RAM. This true dual port with separate read write addresses. bits read address (A0R A4R), bits write address (A0W A4W), data input (D), write enable (WE) clock input. inputs totally synchronous clock. Just like edge triggered flip flop, only timing requirement that setup hold times obeyed. operation dual port slightly different than that single port RAMs. When HIGH, write mode. Data presented input will written location specified addresses A4W. dual port always read mode. state unimportant thus either "1". data stored location specified will appear output after rising edge clock. This single clock operation. There exception rule that always read mode. read write addresses equal HIGH, write function takes precedence over read. result, when reading writing same location, only write function enabled output will unknown state. Note that LOW, dual port read mode there will never conflict when read write addresses identical.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Clock Distribution
DL6000 family devices have low-skew clock distribution networks. These networks driven dedicated pins device, internal logic internal PLLs. clock networks global clocks that drive every flip flop device. Eight networks quadrant clocks. quadrant clocks drive logic block flip flops quarter device flip flops adjacent these logic blocks. When driven input pins, each clocks programmable LV-TTL, LV-PECL interface levels. When LV-PECL, clock inputs single-ended differential. used drive clock signal device elsewhere system.
Phase Lock Loops
Devices DL6000 family contain analog phase lock loop (PLL) circuits that used clock multiplication, division phase locking. output clock from duty cycle lock time shown figure output each drive global clock quadrant clock trees. multipliers dividers each quadrant independently. This allows each generate derivative frequencies from incoming clock.
FGCLK
Phase Detector
FQCLK1 FQCLK2 FQCLK3 FQCLK4
Figure
Frequencies quadrant clock outputs divided multiplied according following formula. fQCLKx fin*n kx*m Frequencies global clock outputs multiplied according following formula. fGCLK fin*n
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Values programmed shown table Variable Allowable Values 2,3,4,6 2,3,4,6
Table Variables
following tables show available multipliers dividers different frequencies. 14.4 20.6 GCLK Multiplier QCLK Multiplier (Lock) (Lock) (Lock) (Lock) (Lock) QCLK Dividers
19.2
27.5
(Lock)
28.8
41.3
(Lock) (Lock) (Lock)
3/16
38.3
55.0
57.5
82.5
76.7
110.0
(Lock)
115.0
200.0
(Lock)
Table Multipliers Dividers PLL1 Notes: PLL1 located left corner drives GCLK1, QCLK1TL, QCLK1TR, QCLK1BL, QCLK1BR. Some frequencies require external resistor connected PLL1REST pin.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
10.3
14.4
GCLK Multiplier
13.8
19.2
20.6
28.8
(Lock) (Lock) (Lock)
27.5
38.3
QCLK Multiplier (Lock) (Lock) (Lock) (Lock) (Lock)
QCLK Dividers
3/16
41.3
57.5
55.0
76.7
(Lock)
82.5
115.0
(Lock)
Table Multipliers Dividers PLL2 Notes: PLL2 located right corner drives GCLK2, QCLK2TL, QCLK2TR, QCLK2BL, QCLK2BR. Some frequencies require external resistor connected PLL2REST pin.
GCLK Frequency
Jitter clock period
Table Jitter Note: Requires input clock jitter
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Power Consumption
Power consumption specific design implemented DL6000 family device depends following factors. Number logic blocks used Operating frequency Number outputs used interface level setting (TTL GTL) Output slew rate selection Number global quadrant clocks used Operating supply voltage following table shows typical power consumption various components DL6035 operating MHz. DL6035 Component Logic Block (including interconnect) Block mode (excluding off-chip current) Block mode (excluding off-chip current) Each Global Clock Each Quadrant Clock Typical Power Consumption
Table Typical Power Consumption
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Configuration
Memory cells DynaChip FPGAs store configuration bits that control programmable elements device. These configuration bits called bitstream they loaded automatically from PROM power-up under user control through microprocessor. Systems that contain more than DynaChip device programming chain simplify connections.
Configuration Modes
DL6000 supports configuration modes. Five loading bitstream into device reading bitstream programmed device. state three special pins called mode pins sets configuration mode DL6000 device.
Serial Configuration Modes
There serial configuration modes described table Serial Configuration Mode Serial Internal Last Description This mode used situations. program single device from serial PROM. this mode, DL6000 generates clock signal drive serial PROM. last device programming chain that uses serial PROM. this mode, DL6000 generates clock signal drive serial PROM other DynaChip devices chain. Serial External Last This mode used each device except last device programming chain that uses serial PROM. This mode used program single device using serial bitstream user supplied clock. also used last device programming chain that programmed using serial bitstream user supplied clock.
Table Serial Configuration Modes
Serial External Last
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Microprocessor Configuration Modes
There microprocessor configuration modes described table Microprocessor Configuration Mode Microprocessor Last Description This mode used situations. program single device from microprocessor. last device programming chain that uses microprocessor. Microprocessor Last This mode used each device except last device programming chain that uses microprocessor.
Table Microprocessor Configuration Modes
Dynamic Reconfiguration Using Full Chip Reset
Full Chip Reset enables user completely reset device without turning power. typically used prepare device complete reconfiguration after initial configuration. When full chip reset asserted, configuration bits flip flops device reset. This similar internal reset that occurs when device first powered-up. Full chip reset activated setting mode pins `111' then asserting RESET (active low) minimum mode pins must before reset asserted. reprogram device after full chip reset, mode pins their appropriate values (refer table page apply another RESET pulse least alternative using full chip reset, device reprogrammed using complete bitstream that programs every element. Contact factory availability complete bitstream.
Partial Reprogramming
After device been powered-up programmed, user reprogram portion device without affecting existing application. dynamically reprogram portion device, mode pins their appropriate value (refer table10, page20), then assert RESET (active low). mode pins must before RESET asserted. portion device that affected partial reprogramming operates normally during reconfiguration. Special bitstreams must used partial reconfiguration insure that unused logic interconnect from previous function deleted. Contact factory more information availability these special bitstreams.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Some non-dedicated configuration function user during dynamic reprogramming indicated below: Serial Mode: Pins become dedicated programming. DONE becomes dedicated programming when device used programming chain. DOUT becomes dedicated programming readback required. rest I/O's remain operational. Processor Mode: Pins D1-D7, become dedicated programming. DONE becomes dedicated programming when device used programming chain. DOUT becomes dedicated programming readback required. rest I/O's remain operational.
Readback
Once device been programmed, configuration mode called readback used read program bitstream device determine loaded properly.
Configuration Clock Frequencies
Serial Internal Last mode, DL6000 generates clock that used drive serial PROM. Serial External Last mode, external clock supplied DL6000.
Mode Settings
state three pins DL6000 device named determine loading mode. settings each mode shown table Configuration Mode Serial Internal Last Serial External Last Serial External Last Microprocessor Last Microprocessor Last Readback Full Chip Reset
Table Mode Settings Note: mode pins connected, they pulled down logic '0'.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Flip Flop Initialization
After configuration, flip flops unknown state. flip flops initialized applying global reset signal device. Upon assertion global reset, logic block flip flops either reset depending their definition design.
Configuration Schematics
following schematics show typical connections DL6000 each loading mode.
Serial PROM Configuration Mode
serial PROM configuration mode, device automatically loads itself from serial PROM when system powered PROM provides serial data responds clock signal generated DL6000 device. Systems using this loading mode should connected shown figure
Serial Data Memory Reset/OE
DL6000
PCLK SYSDONE STRPGM
Reset
Reset
Figure Serial PROM Configuration Schematic
Microprocessor Configuration Mode
microprocessor configuration mode, device loaded under user control from microprocessor interface. Data loaded into DL6000 device byte-wide response rising edge write enable signal. DL6000 device generates ready signal that indicates ready next byte data. Systems using microprocessor configuration mode should connected shown figure
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Data
D[7:1] DL6000 STRTPGM SYSDONE Reset
Figure Microprocessor Configuration
microprocessor also used load DL6000 family device serial external mode. this configuration, microprocessor supplies clock serial data DL6000 family device.
Programming Chains
Programming chains simplify connections systems that more than DL6000 family device. Using programming chains, DL6000, called last device, connects source configuration data. remaining DL6000 devices connect chain using their serial configuration pins. Systems using programming chains with serial PROM should connected shown figure Systems using programming chains with microprocessor should connected shown figure
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Most Positive Voltage
DL6000
Done PCLK Reset
DL6000
Done PCLK Reset
DL6000
Reset
STPGM Done
STPGM Done
STPGM PCLK Done
Serial Memory
Reset/OE
Data Reset
Most Negaitive Voltage
Figure Programming Chain Using Serial Memory
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Most Positive Voltage
DL6000
Done
DL6000
Done
DL6000
Reset Reset Reset
Processor
STPGM D[7:1] Done
STPGM D[7:1] Done
STPGM D[7:1] Done
D[7:0]
Most Negaitive Voltage
Figure Programming Chain Using Microprocessor
Bitstream Size
size programming bitstream DL6000 family device depends number logic blocks that used design. following table shows maximum number programming bits each device DL6000 family. Device DL6009 DL6020 DL6035 DL6055 DL6080 DL6105 Maximum Number Programming Bits 140,000 270,000 450,000 670,000 940,000 1,300,000
Table Maximum Number Programming Bits
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Configuration Pins
types pins used configuration process. Permanently dedicated pins always dedicated configuration functions. User pins that have special functions become user pins after device configuration PCKI/ PCKO Dedicated Function This different functions depending programming mode. device only device programmed last programming chain external clock being used, this output that sends master clock other devices serial PROM. device programming chain last device, this input that receives master clock from last device. external, user supplied clock controls configuration process, this input that clock. When programming, this defaults input. STRPGM RESET This should connected shown configuration schematics. This reset used dynamic reprogramming. asserted setting mode pins value except `111' asserting RESET (active low) minimum Note that mode pins must before RESET asserted. non-dedicated configuration I/O's assume states based function defined programming mode. dynamic reprogramming required, RESET should connected shown configuration schematics. DONE This output dedicated programming. Once configuration been completed, this goes from high stays high until either power turned reset signal applied. device last only device programmed, this signals device that configuration been completed start normal operation. Also, device last programming chain, this signals other devices that programming been completed return normal operation. This signal also controls enabling disabling serial PROM(s). These pins inputs during programming. They used tell device(s) which mode will used configuration. list settings each configuration mode shown table These pins become I/O's during normal operation. mode pins connected, they pulled down logic `0'.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
DONE
Dedicated
Function This input during programming that only used multiple device configuration mode. device last, DONE tied SYSDONE last device. high this signals that programming been completed device begins normal operation. This used during normal operation. This input during programming. accepts serial data from memory source another device. also accept from byte wide memory source microprocessor configuration mode. This used during normal operation. These data input pins microprocessor configuration mode. They only activated after reset signal been applied. They accepts bits data loaded from parallel source. used I/Os during normal operation. This input during microprocessor configuration mode. only activated after reset signal been applied. This used processor signal DL6000 that 8-bits have been placed D[7:0] pins loading. This becomes during normal operation. This output microprocessor configuration mode. signals external processor that bits have been loaded device ready receive next bits. This used during normal operation. This outputs supplies bitstream during readback mode. This used during normal operation.
DOUT
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
JTAG
devices DL60000 family provide JTAG Boundary Scan. Completely compatible with IEEE specifications, this feature simplifies testing boards with surface mount packages closely spaced pins. Four JTAG instructions supported shown table JTAG Instructions SAMPL/PRE EXTEST BYPASS IDCODE Register BYPASS
Table JTAG Instructions
Opcode 1000 0000 1111 1101
JTAG register read when DL6000 reset when Opcode 1101 loaded. power-up, opcode defaults 1101. Internal pull-up resistors provided pins. DL6000 JEDEC number 331-300-6100-0.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Product Specifications
Maximum Ratings
Symbol TSTORE Description Potential Input Voltage Voltage applied 3-state output Storage temperature Junction Temperature Value -0.5 +5.0 -0.5 -0.5 +150 +150 Unit
Table Absolute Maximum Rating Note: Permanent damage device occur Absolute Maximum ratings exceeded. This stress rating only. Functional operation device these other conditions other than those listed under Recommended Operating Conditions implied. Exposure Absolute Maximum Ratings conditions extended periods time affect device reliability.
Operating Conditions
Symbol VCC(1) Description Supply voltage relative Commercial junction Industrial junction terminating voltage relative Commercial junction Industrial junction 1.14 1.08 1.26 1.32 3.14 3.47 Unit
Table Recommended Operating Conditions Notes: 0.25µ devices require core supply voltage 2.5V supply voltage 3.3V junction temperatures above those listed Operating conditions illegal.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Characteristics Over Operating Conditions
Symbol VIMAX
Parameter Max. voltage applied input Max. voltage applied clock inputs High-level Input Voltage Low-level input voltage High-level Input Voltage Low-level input voltage High-level Input Voltage Low-level input voltage High-level input voltage Low-level input voltage High level output voltage level output voltage (1,2) High level output voltage (3,4) level output voltage Quiescent current Leakage Current Input capacitance
0.7VCC VREF 2.135 1.490
3.63 0.3VCC VREF 2.420 1.825
Units
Test Conditions
VCMAX(6) VIH(TTL) VIL(TTL) VIH(CMOS) VIL(CMOS) VIH(GTL) VIL(GTL) VIH(LVPECL) VIL(LVPECL) (TTL) VOL(TTL) VOH(GTL) VOL(GTL)
When 3.3V When 3.3V min, note min, note
MAX; I/O's open
Table Electrical Characteristics Notes: With outputs simultaneously sinking each. Sink/Source current mode varies with slew rate setting: Fast slew rate: sink/source current min) Medium slew rate: sink/source current min) Slow slew rate: sink/source current min) Sink current mode Source current provided external pull-up resistor. VREF pins except clock inputs volt tolerant. maximum voltage applied following clock input pins should exceed this value, even they used non-clock I/O. QCLK1TL, QCLK1TLN, QCLK2TL, QCKL2TLN, QCLK1BL, QCKL1BLN, QCLK2BL, QCKL2BLN, QCLK1BR, QCLK1BRN, QCLK2BR, QCKL2BRN, QCLK1TR, QCKL1TRN, QCLK2TR, QCKL2TRN, GCLK1, GCLK1N, GCLK2, GCLK2N, PLLIREST, PLL2REST
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Clock Set/Reset Buffer Switching Characteristics
Speed Grade Description Symbol Clock buffer delay with Global clock delay without Global clock skew Quadrant clock delay without PLL(1) Quadrant clock skew Clock pulse width high Clock pulse width Global Set/Reset delay TCPLL TGCKD TGCKS TQCKD TQCKS TMPH TMPL TGSR Units
Table Clock Buffer Characteristics (Input TTL) Notes: Global quadrant clock delays measured from input device flip flop clock input. delays specified over commercial voltage temperature range. Clock delays also referred latency.
Speed Grade Description Symbol Clock buffer delay with Global clock delay without Global clock skew Quadrant clock delay without PLL(1) Quadrant clock skew Clock pulse width high Clock pulse width Global Set/Reset delay TCPLL TGCKD TGCKS TQCKD TQCKS TMPH TMPL TGSR Units
Table Clock Buffer Characteristics (Input GTL) Notes: Global quadrant clock delays measured from input device flip flop clock input. delays specified over commercial voltage temperature range. Clock delays also referred latency.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Speed Grade Description Symbol Clock buffer delay with Global clock delay without Global clock skew Quadrant clock delay without PLL(1) Quadrant clock skew Clock pulse width high Clock pulse width Global Set/Reset delay TCPLL TGCKD TGCKS TQCKD TQCKS TMPH TMPL TGSR Units
Table Clock Buffer Characteristics (Input LV-PECL) Notes: Global quadrant clock delays measured from input device flip flop clock input. delays specified over commercial voltage temperature range. Clock delays also referred latency.
Speed Grade Description Symbol Clock buffer delay with Global clock delay without Global clock skew Quadrant clock delay without PLL(1) Quadrant clock skew Clock pulse width high Clock pulse width Global Set/Reset delay TCPLL TGCKD TGCKS TQCKD TQCKS TMPH TMPL TGSR Units
Table Clock Buffer Characteristics (Input Differential LV-PECL) Notes: Global quadrant clock delays measured from input device flip flop clock input. delays specified over commercial voltage temperature range. Clock delays also referred latency. operation, clock pulse width high table
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Input Output Block Switching Characteristics
Speed Grade Description Input buffer combinatorial delay Input Register Set-up Time (global clock) Input Register Hold Time (global clock) Input Register Clock Output (global clock) Output buffer combinatorial delay load)(2,3) Symbol TINPD TINIS1 TINIH1 TINCO1 TOUTIS1 TOUTIS2 TOUTIH1 TOUTCO1 TCES1 TCEH1 TGSRI TGSRO TGSRIS1 TGSROS1 Units
Output Register Set-up Time (global clock) Output Register Hold Time (global clock) Output Register Clock Output (global clock, load) (2,3) Register Clock Enable Setup Time Register Clock Enable Hold Time Input Register set/reset delays Output Register set/reset delays Input Register set/reset setup time Output Register set/reset setup time
Table Input Output Buffer Parameters (I/O TTL) Notes: delays specified over commercial voltage temperature range. Output delays specified with load. following delays adjust loading. Fast Slew Rate: ps/pf Medium Slew Rate: ps/pf Slow Slew Rate: ps/pf maximum loading outputs switching same time same direction shown below. Significant ground bounce occur these guidelines violated. Fast Slew Rate: between each power/ground pair Medium Slew Rate: between each power/ground pair Slow Slew Rate: between each power/ground pair Each output individual slew rate control.
Three-state Buffer Characteristics
Speed Grade Description Symbol 3-state Active load)(2,3) 3-state Hi-Z load) (2,3) T3SOE TINIS1 Units
Table Three-state Buffer Delays Notes: delays specified over commercial voltage temperature range. Output delays specified with load. following delays adjust loading. Fast Slew Rate: ps/pf Medium Slew Rate: ps/pf Slow Slew Rate: ps/pf Each output individual slew rate control.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Speed Grade Description Symbol Output buffer combinatorial delay load)(2) Output Register Set-up Time (global clock) Output Register Hold Time (global clock) Output Register Clock Output (global clock, load) Register Clock Enable Setup Time Register Clock Enable Hold Time Input Register set/reset delays Output Register set/reset delays Input Register set/reset setup time Output Register set/reset setup time TCES1 TCEH1 TGSRI TGSRO TGSRIS1 TGSROS1 TOUTIS1 TOUTIS2 TOUTIH1 TOUTCO1 Units
Table Input Output Buffer Parameters (I/O GTL) Notes: delays specified over commercial voltage temperature range. Output delays specified with load. following delays adjust loading. GTL: ps/pf
Speed Grade Description Symbol Input buffer combinatorial delay Input Register Set-up Time (global clock) Input Register Hold Time (global clock) Input Register Clock Output (global clock) TINPD TINIS1 TINIH1 TINCO1 Units
Table Input Output Buffer Parameters (I/O LV-PECL/LVDS)
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Logic Block Switching Characteristics
Speed Grade Description Symbol 3-input AND/OR flip-flop delay 6-input AND/OR flip-flop delay 9-input AND/OR flip-flop delay Multiplexer data flip-flop Multiplexer select flip-flop Adder/multiplier flip-flop (sum) 3-input AND/OR combinatorial delay 6-input AND/OR combinatorial delay 9-input AND/OR combinatorial delay Adder/Multiplier delay (sum) Multiplexer data delay Multiplexer select delay Flip-flop setup time Flip-flop setup time Flip-flop clock (GCLK QCLK) Flip-flop clock (LCK2) set/reset flip-flop set/reset delay Logic Block Pass Through TANDR3 TANDR6 TANDR9 TMUXR TMUXSR TADDCR TANDC3 TANDC6 TANDC9 TADDC TMUXC TMUXS TSUT TCOG TCOL TGSRFF TLSR TLBPT Units
Table Logic Block Switching Parameters (Includes Routing Delays Within Routing Region(6)) Notes: delays specified over commercial voltage temperature range. Industrial speed grade delays higher. Refer figure picture logic paths described above table. AND/OR combinatorial delay, adder/multiplier delay multiplexer delay include complete path through logic block from inputs through outputs, connection buffers routing next logic block active repeater. AND/OR flip flop, multiplexer data flip-flop, multiplexer select flipflop adder/multiplier flip flop delay includes elements from inputs input either flip flop. Logic block delays shown table include connection buffer routing delays within block routing region. Additional delays incurred only when must through active repeater reach block another routing region. table active repeater delays.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Logic Block Logic Block
Logic Block
Logic Block
Logic Block Connection Buffer Input Connection Routing
Logic Block
Logic Block
Logic Block
delay through these elements included logic block delays table
Logic Block
Logic Block
Logic Block
Figure Logic Block Delays Includes Routing Within Region
Switching Characteristics
Speed Grade Description Symbol Read/Write Operation Address setup time before clock Address hold time after clock setup time before clock hold time after clock setup time before clock hold time after clock Clock pulse width high Read Cycle Output data valid after clock TROS TMPH 10.0 Units
Table Switching Parameters Dual Port Mode Notes: delays specified over commercial voltage temperature range. Applies operation only. table clock pulse width high other operating modes.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Speed Grade Description Symbol Read/Write Operation Address setup time before clock Address hold time after clock setup time before clock hold time after clock setup time before clock hold time after clock Read Cycle Output data valid after clock TROS 11.0 10.0 Units
Table Switching Parameters Single Port Mode Note: delays specified over commercial voltage temperature range.
Programmable Interconnect Characteristics
Speed Grade Description Symbol Horizontal Active Repeater Delay Vertical Active Repeater Delay Vertical Horizontal Active Repeater Delay Horizontal Vertical Active Repeater Delay THRPT TVRPT TVHRPT THVRPT Units
Table Active Repeater Switching Parameters Note: delays specified over commercial voltage temperature range.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Description
352-pin SBGA DL6035
Description RESET STRPGM PCKI/PCKO SYSDONE PLL1REST PLL2REST IO_2 IO_3 IO_4 IO_5 IO_6 IO_7 IO_8 IO_9 IO_10 IO_11 IO_12 IO_13 IO_14/QCLK1TLN IO_15/QCLK1TL IO_16 IO_17 IO_18/QCLK2TLN IO_19/QCLK2TL IO_20 IO_21 IO_22 IO_23 IO_24 IO_25 IO_26 IO_27 IO_28 IO_29 IO_30/GCLK1N IO_31/GCLK1 IO_32 IO_33 IO_34 IO_35 IO_36 IO_37/WE IO_38 IO_39/RDY IO_40 IO_41/DI(7) IO_42 IO_43/DI(6) IO_44 IO_45 SBGA Ball AE25 AE24 AD22 Description IO_46/QCLK1BLN IO_47/QCLK1BL IO_48 IO_49/DI(5) IO_50/QCLK2BLN IO_51/QCLK2BL IO_52 IO_53/DI(4) IO_54 IO_55/DI(3) IO_56 IO_57/DI(2) IO_58 IO_59/DI(1) IO_60 IO_61/DI(0) IO_62/TDO IO_63 IO_64 IO_65 IO_66 IO_67/M0 IO_68 IO_69 IO_70/M1 IO_71 IO_72/M2 IO_73 IO_74/DONE IO_75 IO_76/DOUT IO_77 IO_78 IO_79 IO_80 IO_81 IO_82 IO_83 IO_84 IO_85 IO_86 IO_87 IO_88 IO_89 IO_90 IO_91 IO_92 IO_93 IO_94 IO_95 SBGA Ball AA25 AB25 AA24 AA23 AC26 AB24 AC25 AD25 AB23 AD24 AC24 AD23 AF25 AC22 AE23 AE22 AC21 AF22 AD21 AC20 AE21 AD20 AE20 AE19 AD19 AE18 AC18 AD18 AF18 AC17 AE17 AE16 AD17 AF16 AC16 AD16 AE15 AC15 AE14 AF13 AD15 AE13
Table DL6035/352 Description
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Description IO_96 IO_97 IO_98 IO_99 IO_100 IO_101 IO_102 IO_103 IO_104 IO_105 IO_106 IO_107 IO_108 IO_109 IO_110 IO_111 IO_112 IO_113 IO_114 IO_115 IO_116 IO_117 IO_118 IO_119 IO_120 IO_121 IO_122 IO_123 IO_124 IO_125 IO_126 IO_127/TMS IO_128/TCK IO_129/TDI IO_130 IO_131 IO_132 IO_133 IO_134 IO_135 IO_136 IO_137 IO_138 IO_139 IO_140 IO_141 IO_142 IO_143 IO_144/QCLK2BR IO_145/QCKL2BRN IO_146 IO_147 IO_148/QCLK1BR
SBGA Ball AD14 AE12 AD13 AD12 AC13 AC12 AF11 AD11 AE11 AE10 AC11 AD10
Description IO_149/QCLK1BRN IO_150 IO_151 IO_152 IO_153 IO_154 IO_155 IO_156 IO_157 IO_158 IO_159 IO_160/GSR IO_161 IO_162 IO_163 IO_164/GCLK2 IO_165/GCLK2N IO_166 IO_167 IO_168 IO_169 IO_170 IO_171 IO_172 IO_173 IO_174 IO_175 IO_176/QCLK2TR IO_177/QCLK2TRN IO_178 IO_179 IO_180/QCLK1TR IO_181/QCLK1TRN IO_182 IO_183 IO_184 IO_185 IO_186 IO_187 IO_188 IO_189 IO_190 IO_191 IO_193 IO_194 IO_195 IO_196 IO_197 IO_198 IO_199 IO_200 IO_201 IO_202
SBGA Ball
Table DL6035/352 Description
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Description IO_203 IO_204 IO_205 IO_206 IO_207 IO_208 IO_209 IO_210 IO_211 IO_212 IO_213 IO_214 IO_215 IO_216 IO_217 IO_218 IO_219 IO_220 IO_221 IO_222 IO_223 IO_224 IO_225 IO_226 IO_227 IO_228 IO_229 IO_230 IO_231 IO_232 IO_233 IO_234 IO_235 IO_236 IO_237 IO_238 IO_239 IO_240 IO_241 IO_242 IO_243 IO_244 IO_245 IO_246 IO_247 IO_248 IO_249 IO_250 IO_251 IO_252 IO_253 IO_254 IO_255
SBGA Ball
Description IO_256 VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_PLL VCC_PLL GND_IO GND_IO GND_IO GND_IO
SBGA Ball AF12 AF17 AF20 AF23 AD26 AF15 AF21 AF24 AE26 AB26
Table DL6035/352 Description
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Description GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_CORE/CLK
SBGA Ball AC10 AC14 AC19 AC23
Description GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_PLL GND_PLL
SBGA Ball AF10 AF14 AF19 AF26 AA26
Table DL6035/352 Description Notes: IO_1 available PLL1REST. IO_192 available PLL2REST.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
208-pin DL6035
Description VCC_PLL GND_CK VCC_CK GND_INT PLL2REST IO_190 VCC_INT IO_187 GND_IO IO_184 VCC_IO IO_181 QCLK1TRN IO_180 QCLK1TR IO_177 QCLK2TRN SUBN-GND IO_176 QCLK2TR IO_172 IO_171 GND_IO GND_INT VCC_IO IO_166 IO_165 GCLK2N IO_164 GCLK2 IO_163 GND_IO IO_161 VCC_CK GND_CK IO_160 IO_159 VCC_IO IO_157 IO_156 IO_155 GND_IO IO_153 IO_152 VCC_IO IO_149 QCLK1BRN IO_148 QCLK1BR IO_145 QCKL2BRN IO_144 QCLK2BR GND_INT GND_IO VCC_INT IO_136 VCC_IO 6035 IO_131 6035X GTL_REF_EXT IO_129 Blank GND_CK Description VCC_CK IO_128 IO_127 SYSDONE IO_124 IO_123 GND_IO GND_INT IO_120 IO_119 VCC_IO VCC_INT IO_116 IO_115 IO_112 IO_111 IO_108 IO_107 GND_IO GND_INT IO_104 VCC_IO VCC_INT IO_99 IO_96 IO_93 IO_92 IO_91 GND_IO IO_89 VCC_INT IO_88 IO_87 VCC_IO GND_INT IO_84 IO_83 IO_80 IO_79 IO_76 DOUT GND_IO IO_74 DONE VCC_INT IO_72 VCC_IO IO_70 PCKI/PCKO IO_68 IO_67 STRPGM VCC_CK GND_INT
Table DL6035/208 Description
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Description GND_CK RESET IO_62 IO_61 DI(0) VCC_INT IO_59 DI(1) GND_IO IO_57 DI(2) GND_INT IO_55 DI(3) VCC_IO IO_53 DI(4) IO_51 QCLK2BL IO_50 QCLK2BLN IO_49 DI(5) IO_47 QCLK1BL IO_46 QCLK1BLN IO_43 DI(6) GND_IO IO_42 IO_41 DI(7) IO_39 VCC_IO IO_37 IO_35 IO_34 GND_CK VCC_CK IO_31 GCLK1 IO_30 GCLK1N IO_28 GND_IO IO_23 VCC_IO IO_19 QCLK2TL IO_18 QCLK2TLN IO_15 QCLK1TL IO_14 QCLK1TN IO_11 GND_IO IO_8 IO_7 VCC_IO IO_5 GND_INT IO_4 IO_3 PLL1REST VCC_INT VCC_CK GND_CK VCC_PLL
Description GND_PLL IO_256 IO_255 VCC_IO IO_254 IO_253 VCC_INT GND_IO IO_250 GND_INT IO_246 IO_245 IO_242 IO_241 VCC_IO IO_238 VCC_INT GND_IO IO_234 GND_INT IO_231 IO_230 IO_227 GND_IO IO_226 IO_224 IO_223 VCC_IO IO_222 IO_221 IO_220 IO_219 GND_IO IO_218 IO_217 VCC_IO IO_214 IO_213 IO_210 IO_209 IO_206 IO_205 GND_INT GND_IO IO_202 IO_201 VCC_INT VCC_IO IO_198 IO_194 IO_193 GND_PLL
Table DL6035/208 Description
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
352-pin SBGA DL6020
Description RESET STRPGM PCKI/PCKO SYSDONE PLL1REST PLL2REST IO_2 IO_3 IO_4 IO_5 IO_6 IO_7 IO_8 IO_9 IO_10 IO_11 IO_12 IO_13 IO_14/QCLK1TLN IO_15/QCLK1TL IO_17 IO_18/QCLK2TLN IO_19/QCLK2TL IO_20 IO_22 IO_24 IO_25 IO_26 IO_28 IO_30/GCLK1N IO_31/GCLK1 IO_32 IO_33 IO_34 IO_35 IO_36 IO_37/WE IO_39/RDY IO_41/DI(7) IO_43/DI(6) IO_44 IO_46/QCLK1BLN IO_47/QCLK1BL IO_49/DI(5) IO_50/QCLK2BLN IO_51/QCLK2BL IO_53/DI(4) IO_55/DI(3) IO_57/DI(2) IO_58 SBGA Ball AE25 AE24 AD22 AA25 AB25 AA23 AC26 Description IO_59/DI(1) IO_61/DI(0) IO_62/TDO IO_63 IO_64 IO_65 IO_66 IO_67/M0 IO_68 IO_69 IO_70/M1 IO_72/M2 IO_74/DONE IO_76/DOUT IO_77 IO_78 IO_79 IO_81 IO_82 IO_83 IO_85 IO_87 IO_88 IO_89 IO_91 IO_93 IO_94 IO_95 IO_96 IO_98 IO_99 IO_100 IO_101 IO_102 IO_103 IO_105 IO_106 IO_108 IO_110 IO_112 IO_113 IO_115 IO_117 IO_118 IO_119 IO_120 IO_122 IO_123 IO_124 IO_125 SBGA Ball AB24 AD25 AB23 AD24 AC24 AD23 AF25 AC22 AE23 AE22 AC21 AD21 AE21 AE20 AE19 AD19 AE18 AD18 AF18 AC17 AE16 AF16 AC16 AD16 AC15 AF13 AD15 AE13 AD14 AD13 AD12 AC13 AC12 AF11 AD11 AE10 AC11 AD10
Table DL6020 Description
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Description IO_126 IO_127/TMS IO_128/TCK IO_129/TDI IO_130 IO_131 IO_132 IO_133 IO_134 IO_135 IO_137 IO_138 IO_139 IO_140 IO_142 IO_143 IO_144/QCLK2BR IO_145/QCKL2BRN IO_146 IO_148/QCLK1BR IO_149/QCLK1BRN IO_151 IO_152 IO_154 IO_156 IO_158 IO_159 IO_160/GSR IO_162 IO_164/GCLK2 IO_165/GCLK2N IO_167 IO_168 IO_170 IO_171 IO_173 IO_174 IO_176/QCLK2TR IO_177/QCLK2TRN IO_178 IO_180/QCLK1TR IO_181/QCLK1TRN IO_183 IO_185 IO_186 IO_187 IO_188 IO_189 IO_190 IO_191 IO_193 IO_194 IO_195
SBGA Ball
Description IO_196 IO_197 IO_198 IO_199 IO_201 IO_202 IO_204 IO_205 IO_207 IO_208 IO_210 IO_212 IO_213 IO_215 IO_216 IO_217 IO_219 IO_221 IO_222 IO_223 IO_224 IO_225 IO_226 IO_227 IO_229 IO_230 IO_232 IO_233 IO_235 IO_237 IO_238 IO_240 IO_242 IO_243 IO_245 IO_247 IO_248 IO_249 IO_250 IO_251 IO_252 IO_253 IO_254 IO_255 IO_256 VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO
SBGA Ball
Table DL6020 Description
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Description VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_PLL VCC_PLL GND_IO GND_IO
SBGA Ball AF12 AF17 AF20 AF23 AD26 AF15 AF21 AF24 AE26 AB26
Description GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_PLL GND_PLL
SBGA Ball AC10 AC14 AC19 AC23 AF10 AF14 AF19 AF26 AA26
Table DL6020 Description Note: Pins that shown should left disconnected board.
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
352-pin SBGA DL6009
Description RESET STRPGM PCKI/PCKO SYSDONE PLL1REST PLL2REST IO_3 IO_5 IO_7 IO_9 IO_11 IO_14/QCLK1TLN IO_15/QCLK1TL IO_18/QCLK2TLN IO_19/QCLK2TL IO_22 IO_26 IO_30/GCLK1N IO_31/GCLK1 IO_33 IO_35 IO_37/WE IO_39/RDY IO_41/DI(7) IO_43/DI(6) IO_46/QCLK1BLN IO_47/QCLK1BL IO_49/DI(5) IO_50/QCLK2BLN IO_51/QCLK2BL IO_53/DI(4) IO_55/DI(3) IO_57/DI(2) IO_59/DI(1) IO_61/DI(0) IO_62/TDO IO_64 IO_65 IO_67/M0 IO_68 IO_70/M1 IO_72/M2 IO_74/DONE IO_76/DOUT IO_79 IO_82 IO_85 IO_88 IO_89 IO_91 SBGA Ball AE25 AE24 AD22 AA25 AB25 AA23 AB24 AD25 AB23 AC24 AD23 AC22 AE23 AC21 AD21 AE21 AE20 AE18 AF18 AE16 AC16 AD16 AC15 Description IO_93 IO_94 IO_96 IO_98 IO_101 IO_103 IO_105 IO_106 IO_108 IO_110 IO_112 IO_115 IO_117 IO_120 IO_122 IO_123 IO_125 IO_127/TMS IO_128/TCK IO_129/TDI IO_132 IO_135 IO_137 IO_138 IO_140 IO_142 IO_144/QCLK2BR IO_145/QCKL2BRN IO_148/QCLK1BR IO_149/QCLK1BRN IO_151 IO_154 IO_156 IO_158 IO_159 IO_160/GSR IO_162 IO_164/GCLK2 IO_165/GCLK2N IO_167 IO_170 IO_173 IO_176/QCLK2TR IO_177/QCLK2TRN IO_180/QCLK1TR IO_181/QCLK1TRN IO_183 IO_185 IO_188 IO_189 SBGA Ball AF13 AD15 AD14 AD13 AC12 AD11 AE10 AC11 AD10
Table DL6009 Description
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Description IO_194 IO_196 IO_198 IO_199 IO_201 IO_202 IO_204 IO_205 IO_207 IO_210 IO_212 IO_213 IO_216 IO_219 IO_222 IO_223 IO_226 IO_229 IO_232 IO_233 IO_235 IO_237 IO_240 IO_242 IO_245 IO_247 IO_249 IO_251 IO_252 IO_253 IO_255 IO_256 VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO VCC_IO
SBGA Ball AF12 AF17 AF20 AF23 AD26
Description VCC_IO VCC_IO VCC_IO VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_CORE/CLK VCC_PLL VCC_PLL GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_IO GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK
SBGA Ball AF15 AF21 AF24 AE26 AB26 AC10 AC14 AC19 AC23
Table DL6009 Description
DynaChip
Page
DL6000 Fast Field Programmable Gate Array
Description GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK
SBGA Ball AF10 AF14 AF19 AF26 AA26
Description GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_CORE/CLK GND_PLL GND_PLL
SBGA Ball
Table DL6009 Description Note: Pins that shown should left disconnected board.
Page
DynaChip
DL6000 Fast Field Programmable Gate Array
Package Drawings
352-pin SBGA
BALL CORNER
1.27 TYP.
1.625
UNIT SHOWN FROM BALL ARRAY SIDE (Dimensions
0.91 1.54
0.63
SIDE VIEW Figure Package Drawing 352-pin SBGA
DynaChip
1.625
Page
DL6000 Fast Field Programmable Gate Array
208-pin Thermal Enhanced PQFP (PQ208)
28.00
View
Dimension Millimeters Lead Pitch 0.50
Stand-Off 0.25
Metal Heat Sink
Side View
0.13 0.27
Figure Package Drawing 208-pin PQFP
Page
DynaChip
30.4 31.2
DL6000 Fast Field Programmable Gate Array
Ordering Information
Order codes shown below.
DL6009BG352FC
Prefix Prefix Device 6009 6020 6035 6055 6080 6105
9,000 Gate Device 20,000 Gate Device 35,000 Gate Device 55,000 Gate Device 80,000 Gate Device 105,000 Gate Device
Package Type Ball Grid Array Quad Flat Pack Grid Array Count Speed Grade Product Specifications Temperature Range Commercial Industrial
DynaChip, DL6000, DL5000, FFPGA DynaTool registered trademarks DynaChip. These products covered following U.S. patents: 5355035, 5397943, 5504440, 4497108, 5614844, 5570059, 5406133, 5654665.
DynaChip 1255 Oakmead Pkwy. Sunnyvale, 94086 Phone: 408-481-3100 Fax: 408-481-3136 Email: support@dyna.com http://www.dyna.com
information contained this document subject change without notice.
DynaChip
Page
Sales Representatives
International
Actron Technology (China/Hong Kong) 26/F., Lever Centre 69-71 King Street Kwun Tong, Kowloon, Hong Kong 852-2727-3978 FAX: 852-2727-4330 Ambar Components, Ltd. (U.K. Eire) Rabans Close Aylesbury Bucks. HP19 3RS, England, U.K. 1296 397396 FAX: 1296 397439 Design Automation Pvt. Ltd. (India) Greater Kailash Delhi India 6477085 FAX: 6213498 Dasko, Ltd. (Korea) #3808, KWTC 159-1, Samsung-dong, Kangnam-ku Seoul 135-729 Korea 82-2-551-3143 FAX: 82-2-551-6411 El-Gev Electronics Ltd. (Israel) Ha'Avoda Street Rosh Ha'Ayin 48101 Israel Shipping office Donna Court Lynbrook, 11563 (516) 599-4399 (516) 599-4920 JEPICO Corp. (Japan) Shinjuku Dai-ichi Seimei Building Nishi-Shinjuku 2-7-1 Shinjuku-ku, Tokyo 163-0729, Japan (03) 3348-0611 FAX: (03) 3348-0623
http://www.dyna.com
Sales Representatives
North America (cont.)
InTelaTech Inc. (Vancouver) 3665 Kingsway Suite Vancouver, B.C. (604) 434-5699, ext. FAX: (604) 434-5655 InTelaTech Inc. (Calgary) 140, 6815 Street N.E. Calgary, (403) 686-2268 FAX: (403) 686-6926 J-Square Marketing Inc. (CT, Jericho, 11753-0103 (516) 935-3200 FAX: (516) 935-0029 Ship 161C Levittown Parkway Hicksville, 11801 James Zimmerman Sales Marsh Road Pittsford, 14534 (716) 381-3186 FAX: (716) 385-2103 Sales Company (IL) 1040 Arlington Heights Arlington Heights, 60005 (847) 398-5300 FAX: (847) 398-5708 Sales Company (WI) 2433 North Mayfair Road Suite Milwaukee, 53226-1406 (414) 259-1771 FAX: (414) 259-0246 Millennium Sales, Inc. (No. 1701 North Greenville #1107 Richardson, 75081 (972) 235-5990 FAX: (972) 618-4163 Millennium Sales, Inc. (Austin Antonio, Texas) 12343 Hymeadow Drive Suite Austin, 78750 (512) 335-2375 FAX: (512) 335-2376 Millennium Sales, Inc. (Houston South Texas) 14714 Bluff Court Houston, 77070 (281) 655-9688 FAX: (281) 655-9703 Mission Technology (Orange County) 24422 Avenida Carlotta Suite Laguna Hills, 92653 (714) 951-3696 FAX: (714) 951-3874 Mission Technology (San Diego) 16466 Bernardo Center Drive Suite Diego, 92128 (619) 674-6191 FAX: (619) 674-6196 Mission Technology (Los Angeles) 6345 Balboa Boulevard Suite Encino, 91316 (818) 342-3141 FAX: (818) 342-9564 NELCO Electronics (Denver, Utah, Mexico) 9725 Hampden Avenue Suite Denver, 80231 (303) 671-7677 FAX: (303) 671-7994 Oasis Sales (Minnesota, Western Wisconsin, Dakota, Dakota) 4620 West 77th Street Suite Edina, 55435 (612) 841-1088 FAX: (612) 841-1103 Premier Technical Sales, Inc. (Bay Area) 3235 Kifer Road Suite Santa Clara, 95051 (408) 736-2260 FAX: (408) 736-2826 ProComp Assoc., Inc. (MA, 1049 East Street Tewksbury, 01876 (978) 858-0100 FAX: (978) 858-0110 SierraTek Marketing (Sacramento, 11531 Valley Road Truckee, 96161 (916) 587-8360 FAX: (916) 587-8361 Thompson Associates, Inc. (Southern Ohio) 1025 Centerville-Station Road Centerville, 45459 (937) 435-7733 FAX: (937) 435-1898 Thompson Associates, Inc. (Northern Ohio) 23240 Chagrin Boulevard Suite Beachwood, 44122 (216) 831-6277 FAX: (216) 831-2553 Thompson Assoc., Inc. (Columbus, 5321 Grosbeak Glen Orient, 43146 (614) 877-4304 FAX: (614) 877-0872 Thompson Associates Inc. (West 1311 Laclair Street Pittsburgh, 15218 (412) 244-0317 FAX: (412) 244-0318 Thompson Associates, Inc. (Eastern Michigan) 26105 Orchard Lake Road Suite Farmington Hills, 48334 (248) 476-0505 FAX: (248) 476-0156 Thompson Associates, Inc. (Western Michigan) 3116 Chamberlain Grand Rapids, 49508 (616) 247-6574 FAX: (616) 247-1211 Trinity Technologies, Inc. (Northwest) 6443 Beaverton-Hillsdale Highway Suite Portland, 97221 (503) 291-1333 FAX: (503) 291-2529 Trinity Technologies, Inc. (Northwest) 10710 Avenue Seattle, 98177 (206) 440-3059 FAX: (206) 364-6739 Tusar (Southwest) 12460 Scottsdale, 85267-2460 (602) 998-3688 FAX: (602) 991-0468 Ship 6016 Larkspur Scottsdale, 85254
http://www.dyna.com
Sales Representatives
North America
Apollo Technical Sales (East Coast) 1275 Patrick Drive Suite Satellite Beach, 32937 (407) 777-7511 (407) 777-5251 Apollo Technical Sales (Central Florida) 1703 Magnolia Avenue #C13 South Daytona, 32119 (904) 304-3225 Fax: (904) 304-3221 Apollo Technical Sales (So. Florida) 1251 Federal Highway Suite E-120 Boca Raton, 33432-7352 (561) 347-1500 Fax: (561) 750-9127 Apollo Technical Sales (West Coast Florida) Leeward Island Clearwater, 33767 (813) 445-1640 FAX: (813) 468-9496 BGR-WYCK (Chesapeake) 11350 Random Hills Road Suite Fairfax, 22030 (703) 934-6053 FAX: (703) 648-0231 BGR-WYCK (So. Virginia) 3701 Church Road Laurel, 08054 (609) 727-1070 FAX: (609) 727-9633 InTelaTech Inc. (Montreal) 1755 Regis Street Suite DDO, Quebec (514) 421-5833 FAX: (514) 421-4105 InTelaTech Inc. (Ottawa) Hearst Suite Kanata, (613) 599-7330 FAX: (613) 599-7329 InTelaTech Inc. (Toronto) 5225 Orbitor Drive Suite Mississauga, (905) 629-0082 FAX: (905) 629-1795
http://www.dyna.com

Other recent searches


W474GC - W474GC   W474GC Datasheet
VIP0100THJ - VIP0100THJ   VIP0100THJ Datasheet
SPS-7111WG - SPS-7111WG   SPS-7111WG Datasheet
OXUF934DSb - OXUF934DSb   OXUF934DSb Datasheet
NJM2870 - NJM2870   NJM2870 Datasheet
NJM2870F - NJM2870F   NJM2870F Datasheet
C67076-A2505-A17 - C67076-A2505-A17   C67076-A2505-A17 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive