MICRO-DAC DAC1208 DAC1209 DAC1210 DAC1230 DAC1231 DAC1232 12-Bit Compa
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MICRO-DAC DAC1208 DAC1209 DAC1210 DAC1230 DAC1231 DAC1232 12-Bit Compatible Double-Buffered Converters
MICRO-DAC DAC1208 DAC1209 DAC1210 DAC1230 DAC1231 DAC1232 12-Bit Compatible Double-Buffered Converters
DAC1208 DAC1230 series 12-bit multiplying converters designed interface directly with wide variety microprocessors (8080 8048 8085 Z-80 Double buffering input registers associated control lines allow these DACs appear two-byte ``stack'' system's memory space with additional interfacing logic required DAC1208 series provides input lines allow single buffering maximum throughput when used with 16-bit processors These input lines also externally configured permit 8-bit data interface DAC1230 series used with 8-bit data directly internally formulates 12-bit data from input lines these DACs accept left-justified data from processor analog section precision silicon-chromium (Si-Cr) R-2R ladder network twelve CMOS current switches inverted R-2R ladder structure used with binary weighted currents switched between IOUT1 IOUT2 maintaining constant current each ladder independent switch state Special circuitry provides logic input voltage level compatibility DAC1208 series DAC1230 series 12-bit members family microprocessor compatible DACs (MICRO-DACs) applications requiring other resolutions DAC1000 series 10-bit DAC0830 series 8-bit available alternatives
Features
Linearity specified with zero full-scale adjust only Direct interface popular microprocessors Double-buffered single-buffered flow through digital data inputs Logic inputs which meet voltage level specs logic threshold) Works with reference full 4-quadrant multiplication Operates stand-alone (without desired parts guaranteed 12-bit monotonic DAC1230 series compatible with DAC0830 series 8-bit MICRO-DACs
Specifications
Current Settling Time Resolution Linearity (Guaranteed over temperature) Gain Tempco Power Dissipation Single Power Supply
Bits Bits
Typical Application
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TRI-STATE registered trademark National Semiconductor Corp MICRO-DACis trademark National Semiconductor Corp C1995 National Semiconductor Corporation
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RRD-B30M115 Printed
Absolute Maximum Ratings
Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications (Notes Supply Voltage (VCC) Voltage Digital Input Voltage VREF Input Storage Temperature Range Package Dissipation (Note Voltage Applied IOUT1 IOUT2 (Note Susceptability
Operating Conditions
Lead Temperature (Soldering Temperature Range TMIN TMAX DAC1208LCJ DAC1209LCJ DAC1210LCJ DAC1230LCJ DAC1231LCJ DAC1232LCJ DAC1231LIN DAC1232LIN DAC1208LCJ-1 DAC1210LCJ-1 DAC1230LCJ-1 DAC1231LCJ-1 DAC1232LCJ-1 DAC1231LCN DAC1232LCN DAC1231LCWM DAC1232LCWM Range Voltage Digital Input
800V
Electrical Characteristics
VREF unless otherwise noted Boldface limits apply from TMIN TMAX (see Note other limits Parameter Resolution Linearity Error (End Point Linearity) Zero Full-Scale Adjusted DAC1208 DAC1230 DAC1209 DAC1231 DAC1210 DAC1232 Zero Full-Scale Adjusted DAC1208 DAC1230 DAC1209 DAC1231 DAC1210 DAC1232 Using Internal Vref
Conditions
Notes
(Note
Tested Limit (Note
Design Limit (Note
Units Bits
Differential Non-Linearity
Bits
Monotonicity Gain Error (Min) Gain Error (Max) Gain Error Tempco Power Supply Rejection Reference Input Resistance (Min) Reference Input Resistance (Max) Output Feedthrough Error VREF Vp-p Data Inputs Latched Output Capacitance Data Inputs IOUT1 Latched High IOUT2 Data Inputs IOUT1 Latched IOUT2 Digital Inputs Latched High
mVp-p
mADC mADC
Supply Current Drain Output Leakage Current IOUT1 IOUT2 Digital Input Threshold Digital Input Currents Data Inputs Latched Data Inputs Latched High Threshold High Threshold Digital Inputs Digital Inputs
Electrical Characteristics (Continued) VREF unless otherwise noted Boldface limits apply from TMIN TMAX (see Note other limits
Symbol Parameter Conditions Note (Note Tested Limit (Note Design Limit (Note Units
CHARACTERISTICS Current Setting Time Write XFER Pulse Width Data Setup Time Data Hold Time Control Setup Time Control Hold Time
Note Absolute Maximum Ratings indicate limits beyond which damage device occur electrical specifications apply when operating device beyond specified operating conditions Note voltages measured with respect unless otherwise specified Note This specification applies packages intrinsic power dissipation this part (and fact that there significantly modify power dissipation) removes concern heat sinking Note Both IOUT1 IOUT2 must ground virtual ground operational amplifier linearity error degraded approximately VREF example VREF then offset IOUT1 IOUT2 will introduce additional linearity error Note Tested guaranteed National's AOQL (Average Outgoing Quality Level) Note Design limits guaranteed 100% tested These limits used calculate outgoing quality levels Guaranteed VREF Note unit stands full-scale range Linearity Error Power Supply Rejection specs based this unit eliminate dependence particular VREF value indicate true performance part Linearity Error specification DAC1208 012% FSR(max) This guarantees that after performing zero full-scale adjustment plot 4096 analog voltage outputs will each within 012% VREF straight line which passes through zero full-scale unit FSR(parts million full-scale range) FS(parts million full-scale) used convenience define specs very small percentage values typical higher accuracy converters this instance VREF conversion factor provide actual output voltage quantity example gain error tempco spec represents worst-case full-scale gain error change with temperature from (6)(VREF 106)(125 (10b3) VREF which 075% VREF Note This spec implies that parts guaranteed operate with write pulse transfer pulse width (tW) typical part will operate with only entire write pulse must occur within valid data interval specified apply Note achieve this feedthrough package user must ground metal left floating feedthrough typically Note Typicals represent most likely parametric norm Note leakage current with VREF corresponds zero error 10b9c 103) 100% 002% Note Human body model discharged through resistor Note Tested limit suffix parts applies only
Connection Diagrams
Dual-In-Line Package Dual-In-Line Package
5690
Ordering Information
Switching Waveforms
5690
Typical Performance Characteristics
Digital Input Threshold Digital Input Threshold Temperature Gain Linearity Error Variation Temperature
Gain Linearity Error Variation Supply Voltage
Control Set-Up Time
Data Hold Time
Write Pulse Width
Data Set-Up Time
5690
Definition Package Pinouts
CONTROL SIGNALS (all control signals level actuated) Chip Select (active low) will enable Write active used load digital data bits (DI) into input latch data input latch latched when high 12-bit input latch split into latches holds first bits while other holds bits Byte Byte control used select both latches when Byte Byte high overwrite 4-bit input latch when state Byte Byte Byte Sequence Control When this control high locations input latch enabled When only four least significant locations input latch enabled Write (active low) will enable XFER XFER Transfer Control Signal (active low) This signal combination with causes 12-bit data which available input latches transfer register DI11 Digital Inputs least significant digital input (LSB) DI11 most significant digital input (MSB) IOUT1 Current Output IOUT1 maximum digital code register zero register IOUT2 Current Output IOUT2 constant minus IOUT1 IOUT1 IOUT2 constant (for fixed reference voltage) This constant current 4096 divided reference input resistance Feedback Resistor feedback resistor provided chip shunt feedback resistor external which used provide output voltage This on-chip resistor should always used (not external resistor) since matches resistors on-chip R-2R ladder tracks these resistors over temperature VREF Reference Voltage Input This input connects external precision voltage source internal R-2R ladder VREF selected over range b10V This also analog voltage input 4-quadrant multiplying application Digital Supply Voltage This power supply part from Operation optimum VREF
DAC1230 DAC1231 DAC1232 must connected ground important that IOUT1 IOUT2 ground potential current switching applications difference potential (VOS these pins) will result linearity change VREF example VREF these ground pins offset from IOUT1 IOUT2 linearity change will
Definition Terms
Resolution Resolution defined reciprocal number discrete steps output directly related number switches bits within example DAC1208 4096 steps therefore 12-bit resolution Linearity Error Linearity error maximum deviation from straight line passing through endpoints transfer characteristic measured after adjusting zero full-scale Linearity error parameter intrinsic device cannot externally adjusted National's linearity test best straight line test used other suppliers illustrated below best straight line requires special zero adjustment each part which almost impossible user determine point test uses standard zero adjustment procedure much more stringent test linearity Power Supply Sensitivity Power supply sensitivity measure effect power supply changes full-scale output Settling Time Full-scale current settling time requires zero full-scale full-scale zero output change Settling time time required from code transition until output reaches within final output value Full-Scale Error Full-scale error measure output error between ideal actual device output Ideally DAC1208 DAC1230 series full-scale VREFb1 VREF unipolar operation VFULL-SCALE 0000Vb2 9976V Full-scale error adjustable zero Differential Non-Linearity difference between consecutive codes transfer curve from theoretical differential non-linearity Monotonic output increases increasing digital input code then monotonic 12-bit which monotonic bits simply means that input increasing digital input codes will produce increasing analog output
Pins DAC1208 DAC1209 DAC1210 must connected ground Pins
5690
Point Test After Zero Adjust
Shifting Adjust Pass Best Straight Line Test
Application Hints
DIGITAL INTERFACE These DACs designed provide necessary digital input circuitry permit direct interface wide variety microprocessor systems timing logic level convention input control signals allow DACs treated typical memory device peripheral with external logic required most systems Essentially these DACs mapped two-byte stack memory space) receive their bits input data successive 8-bit data writing sequences DAC1230 series intended systems with 8-bit data DAC1208 series provides digital input lines which externally configured controlled from 8-bit driven directly from 16-bit data
digital inputs these DACs contain unique threshold regulator circuit maintain voltage level compatibility independent applied input also driven from higher voltage CMOS logic levels non-microprocessor based systems prevent damage chip from static discharge unused digital inputs should tied ground troubleshooting digital input inadvertently left floating will interpret logic ``1'' Double buffered digital inputs allow internally format 12-bit word used current switching ladder network (see section from 8-bit data write cycles Figures show internal data registers their controlling logic circuitry timing diagrams updating output shown sections three possible control modes method used depends strictly upon particular application
FIGURE DAC1208 DAC1209 DAC1210 Functional Diagram
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FIGURE DAC1230 DAC1231 DAC1232 Functional Diagram
Application Hints (Continued)
Automatic Transfer 12-bit word automatically transferred register R-2R ladder when second write (the LSBs data) occurs
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Independent Processor Transfer Control this case separate address decoded provide XFER signal This allows processor load next required word change analog output until some time later most useful simultaneous updating several DACs system where their XFER lines would tied together
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Transfer External Strobe This method basically same previous operation except XFER signal provided device other than processor This allows hold code conditional analog output signal which will required demand from external monitoring device analog voltage comparator instance)
tied logic (0V)
5690
Application Hints (Continued)
Left-Justified Data Format important realize that input registers these DACs arranged accept left-justified data word from microprocessor with most significant bits coming first (Byte lower bits second Left justification simply means that binary point assumed located left most significant Figure shows bits data should arranged 8-bit registers 8-bit processor before being written 16-Bit Data Interface DAC1208 series provides digital input lines permit direct parallel interface 16-bit data this instance double buffering always necessary (unless simultaneous updating several DACs data transfer external strobe desired) 12-bit register wired flow-through whereby outputs always reflect state inputs external connections required timing diagram this single buffered application shown Figure Note that either left rightjustified data from processor accommodated with 16-bit data Flow-Through Operation Through primarily designed provide microprocessor interface compatibility MICRO-DACs easily configured allow analog output continuously reflect state applied digital input This most useful appli-
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don't care
FIGURE Left-Justified Data Format Interface Timing
5690-11
XFER grounded Byte Byte tied
FIGURE 16-Bit Data Interface DAC1208 Series
Application Hints (Continued)
cations where used continuous feedback control loop driven binary down counter function generation circuits where continuously providing data Only DAC1208 DAC1209 DAC1210 devices have inputs flow-through Simply grounding XFER tying Byte Byte high allows both internal registers follow applied digital inputs (flow-through) directly affect analog output Address Decoding Tips possible MICRO-DACs into system space allow more efficient existing address decoding hardware effect share same addresses number locations outputs will only enabled READ address (gated system READ strobe) will only accept data that written same address (gated system WRITE strobe) Byte Byte control function easily generated processor's least significant address (A0) placing consecutive address locations utilizing double-byte WRITE instructions which automatically increment decrement address XFER signals then decoded from remaining address bits Care must taken selecting actual address used Byte prevent carry result Write Cycle First (Byte Second (Byte incrementing address Byte from propagating through address word changing bits decoded XFER Figure shows prevent this effect same problem occur from borrow when autodecremented address used only processor's address outputs inverted before being decoded Control Signal Timing When interfacing these MICRO-DACs microprocessor there important time relationships that must considered insure proper operation first minimum strobe pulse width which specified operation over temperature typically pulse width only adequate second consideration that guaranteed minimum data hold time should erroneous data latched This hold time defined length time data must held valid digital inputs after qualified (via strobe makes high transition latch applied data controlling device system does inherently meet these timing specs treated slow memory peripheral utilize technique extend write strobe simple extension write time adding wait state simultaneously hold write strobe active data valid satisfy minimum pulse Address Bits Decoded
Address
Starting with prevents carry address incrementing Used Byte Byte2 Control
FIGURE
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FIGURE Accommodating High Speed System
Application Hints (Continued)
width this does provide sufficient data hold time write cycle negative edge triggered oneshot included between system write strobe This illustrated Figure exemplary system which provides strobe time with data hold time only proper data set-up time prior latching edge (low high transition) strobe insured pulse width within spec data valid duration strobe Digital Signal Feedthrough typical microprocessor tremendous potential source high frequency noise which coupled sensitive analog circuitry fast edges data address signals generate frequency components 10's megahertz cause fast transients appear output even when data latched internally frequency applications pass filtering reduce magnitude fast transients This most easily accomplished over-compensating output amplifier increasing value feedback capacitor applications requiring fast output response from filtering feasible this event digital signals completely isolated from circuitry DM74LS374 latch until valid signal applied update This shown Figure single TRI-STATE data buffer such DM81LS95 used isolate number DACs system Figure shows this isolating circuitry decoding hardware multiple analog output card Pull-up resistors used buffer outputs limit impedance digital inputs when card selected unique feature this card that XFER strobes controlled data This allows very flexible update combination analog outputs transfer word which would contain zero position assigned DACs required change output value
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FIGURE Isolating Data from Circuitry Eliminate Digital Noise Coupling
Application Hints (Continued)
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FIGURE TRI-STATE Buffers Isolate Data Control Lines from DACs Transfer Word Provides Flexible Update
Application Hints (Continued)
ANALOG APPLICATIONS analog output signal these DACs derived from conventional R-2R current switching ladder network detailed description this network found DAC1000 series data sheet Basically output IOUT1 provides current directly proportional product applied reference voltage digital input word second output IOUT2 will current proportional complement digital input Specifically VREF IOUT1 4096 VREF 4095 IOUT2 4096 where decimal equivalent applied 12-bit binary word (ranging from 4095) VREF voltage applied VREF terminal internal resistance R-2R ladder nominally Obtaining Unipolar Output Voltage maintain linearity output current with changes applied digital code important that voltages both current output pins near ground potential VDC) possible With VREF every millivolt appearing either IOUT1 IOUT2 will cause linearity error most applications this output current converted voltage using shown Figure inverting input virtual ground created feedback from output through internal resistor output current (determined digital input reference voltage) will flow through output amplifier Two-quadrant operation obtained reversing polarity VREF thus causing IOUT1 flow into sourced from output amplifier output voltage either case always equal IOUT1 opposite polarity reference voltage reference either stable voltage source signal anywhere range from b10V thought digitally controlled attenuator output voltage always less than applied reference voltage VREF terminal device presents nominal impedance ground external circuitry Always internal resistor create output voltage since this resistor matches (and tracks with temperature) value resistors used generate output current (IOUT1) selected should have value input bias current possible product bias current times feedback resistance creates output voltage error which significant reference voltage applications BI-FETop amps highly recommended with these DACs because their very input current
5690
VOUT (IOUT1 RFb)
VREF(D)
4096 4095
FIGURE Unipolar Output Configuration
BI-FETis trademark National Semiconductor Corp
Application Hints (Continued)
Transient response settling time important fast data throughput applications largest stability problem feedback pole created feedback resistance output capacitance This appears from output input includes stray capacitance this node Addition lead capacitance Figure greatly reduces overshoot ringing output step change output current Zero Full-Scale Adjustments accurate conversions input offset voltage output amplifier must always nulled Amplifier offset errors create overall degradation linearity fundamental purpose zeroing make voltage appearing outputs near possible This accomplished shorting amplifier feedback resistor adjusting nulling potentiometer until output reads zero volts This done course with applied digital code zeros IOUT1 driving (all ones IOUT2) short around then removed converter zero adjusted unique feature this series DACs that full-scale gain error guaranteed negative gain error specification measure close value internal feedback resistor matches R-2R ladder resistors negative gain error indicates that smaller resistance value than should adjust this gain error some resistance must always added series with potentiometer shown sufficient adjust worst-case gain error these devices Bipolar Output Voltage from Fixed Reference addition second unipolar circuit generate bipolar output voltage from fixed reference voltage This effect gives sign significance digital input word allow quadrant multiplication reference voltage polarity reference also reversed realize full 4-quadrant multiplication This circuit shown Figure This configuration features several improvements over existing circuits bipolar output shown with other multiplying DACs Only offset voltage amplifier affects linearity offset voltage error second (although constant output error) effect linearity addition this configuration offers non-interactive positive negative full-scale calibration procedure
VOUT VREF
4095
2048 5690-16 2048
lVREFl
2048
Input Code 111111111111 110000000000 100000000000 011111111111 001111111111 000000000000
Ideal VOUT
VREF VREF VREF VREF
VREF VREF
lVREFl
VREF
VREF
FIGURE Bipolar Output Voltage Configuration
Application Hints (Continued)
Zero Full-Scale Adjustments calibrate bipolar output circuit three adjustments required first step digital inputs force IOUT1 then null amplifier setting voltage inverting input (pin zero volts Next with code zeros still applied adjust ``bfullscale adjust'' reference voltage VOUT lVREF ideall polarity output voltage this time will opposite that applied reference Finally digital inputs HIGH adjust full-scale adjust'' 2047 VOUT VREF 2048 polarity output will same that reference voltage APPLICATION IDEAS this section digital input word represented letter equal decimal equivalent 12-bit binary input Hence integer value between 4095
Composite Amplifier Good Characteristics Fast Output Response
Combines
drift bias current LM11 with fast response LF351
Settling time
zero fullscale transition
High Voltage Power
VOUT
VREFD
4096
5690
Application Hints (Continued)
High Current Controller
Amp(D) 4096
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8-Bit Course 4-Bit Vernier
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Ordering Information
Part Number DAC1208LCJ DAC1208LCJ-1 DAC1209LCJ DAC1210LCJ DAC1210LCJ-1 DAC1230LCJ DAC1230LCJ-1 DAC1231LCJ DAC1231LCJ-1 DAC1231LCN DAC1231LCWM DAC1231LIN DAC1232LCJ DAC1232LCJ-1 DAC1232LCN DAC1232LCWM DAC1232LIN Non-Linearity 018% 018% 024% 050% 050% 018% 018% 024% 024% 024% 024% 024% 050% 050% 050% 050% 050% Package J24A Cerdip J24A Cerdip J24A Cerdip J24A Cerdip J24A Cerdip J20A Cerdip J20A Cerdip J20A Cerdip J20A Cerdip N20A Plastic M20B N20A Plastic J20A Cerdip J20A Cerdip N20A Plastic M20B N20A Plastic Temperature Range
Physical Dimensions inches (millimeters)
20-Lead Ceramic Dual-In-Line Package Order Number DAC1230LCJ DAC1230LCJ-1 DAC1231LCJ DAC1231LCJ-1 DAC1232LCJ DAC1232LCJ-1 Package Number J20A
24-Lead Ceramic Dual-In-Line Package Order Number DAC1208LCJ DAC1208LCJ-1 DAC1209LCJ DAC1210LCJ DAC1210LCJ-1 Package Number J24A
MICRO-DAC DAC1208 DAC1209 DAC1210 DAC1230 DAC1231 DAC1232 12-Bit Compatible Double-Buffered Converters
Physical Dimensions inches (millimeters) (Continued)
20-Lead Molded Small Outline Package Order Number DAC1231LCWM DAC1232LCWM Package Number M20B
20-Lead Molded Dual-In-Line Package Order Number DAC1231LCN DAC1231LIN DAC1232LCN DAC1232LIN Package Number N20A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
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