DAC1020 DAC1021 DAC1022 10-Bit Binary Multiplying Converter DAC1220 DA
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DAC1020 DAC1021 DAC1022 10-Bit Binary Multiplying Converter DAC1220 DAC1222 12-Bit Binary Multiplying Converter
DAC1020 DAC1021 DAC1022 10-Bit Binary Multiplying Converter DAC1220 DAC1222 12-Bit Binary Multiplying Converter
DAC1020 DAC1220 respectively 12-bit binary multiplying digital-to-analog converters deposited thin film R-2R resistor ladder divides reference current provides circuit with excellent temperature tracking characteristics 0002% linearity error temperature coefficient maximum) circuit uses CMOS current switches drive circuitry achieve power consumption max) output leakages (200 max) digital inputs compatible with logic levels well full CMOS logic level swings This part combined with external amplifier voltage reference used standard converter however also very attractive multiplying applications (such digitally controlled gain blocks) since linearity error essentially independent voltage reference inputs protected from damage static discharge diode clamps ground This part available with 10-bit 05%) 9-bit 10%) 8-bit 20%) non-linearity guaranteed over temperature (note electrical characteristics) DAC1020 DAC1021 DAC1022 direct replacements 10bit resolution AD7520 AD7530 equivalent AD7533 family DAC1220 DAC1222 direct replacements 12-bit resolution AD7521 AD7531 family
Features
Linearity specified with zero full-scale adjust only Non-linearity guaranteed over temperature Integrated thin film CMOS structure 10-bit 12-bit resolution power dissipation Accepts variable fixed reference b25VsVREFs25V 4-quadrant multiplying capability Interfaces directly with CMOS Fast settling time feedthrough error
Equivalent Circuit
Note Switches shown digital high state
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Ordering Information
Temperature Range NonLinearity Package Outline Temperature Range NonLinearity DAC1220LCN DAC1222LCN DAC1020LCN DAC1021LCN DAC1022LCN
10-BIT CONVERTERS AD7520LN AD7530LN AD7520KN AD7530KN AD7520JN AD7530JN N16A 12-BIT CONVERTERS AD7521LN AD7531LN AD7521JN AD7531JN N18A
DAC1020LCV
DAC1020LIV
V20A
DAC1220LCJ DAC1222LCJ
AD7521LD AD7531LD AD7521JD AD7531JD J18A
Package Outline
Note Devices ordered either part number
C1996 National Semiconductor Corporation
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RRD-B30M96 Printed
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Absolute Maximum Ratings (Note
Military Aerospace specified devices required please contact National Semiconductor Sales Office Distributors availability specifications
VREF Digital Input Voltage Range Voltage (Note Storage Temperature Range Lead Temperature (Soldering Dual-In-Line Package (plastic) Dual-In-Line Package (ceramic)
Operating Ratings
Temperature (TA) DAC1020LIV DAC1220LCJ DAC1222LCJ DAC1020LCN DAC1020LCV DAC1021LCN DAC1022LCN DAC1220LCN DAC1222LCN Units
Susceptibility (Note
800V VREF 000V unless otherwise specified) DAC1020 DAC1021 DAC1022 DAC1220 DAC1222 Bits Units
Electrical Characteristics
Parameter Conditions
Resolution Linearity Error TMINkTAkTMAX VREF (Note Point Adjustment Only (See Linearity Error Definition Terms) DAC1020 DAC1220 DAC1021 DAC1022 DAC1222
VREF (Notes VREF (Notes
10-Bit Parts 9-Bit Parts 8-Bit Parts Linearity Error Tempco Full-Scale Error Full-Scale Error Tempco Output Leakage Current IOUT IOUT Power Supply Sensitivity
0002
0002
TMINkTAkTMAX (Note TMINsTAsTMAX Digital Inputs Digital Inputs High Digital Inputs High 14VsV s16V (Note (Figure 100X from Digital Inputs Switched Simultaneously Digital Inputs VREF Vp-p Package (Note Package Digital Inputs Digital Inputs High Digital Inputs Digital Inputs High
VREF Input Resistance Full-Scale Current Settling Time
mVp-p mVp-p mVp-p
VREF Feedthrough
Output Capacitance IOUT IOUT
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Electrical Characteristics
Parameter
VREF 000V unless otherwise specified) (Continued) DAC1020 DAC1021 DAC1022
Conditions
DAC1220 DAC1222
Units
Digital Input Threshold High Threshold Digital Input Current
(Figure TMINkTAkTMAX TMINkTAkTMAX
TMINsTAsTMAX Digital Input High Digital Input Digital Inputs High Digital Inputs
Supply Current Operating Power Supply Range
(Figures
Note VREF VREF linearity error temperature coefficient 0002% rise only guarantees 009% maximum change linearity error instance linearity error 045% could increase 054% will longer 10-bit part Note however that linearity error specified over device full temperature range which more stringent specification since includes linearity error temperature coefficient Note Using internal feedback resistor shown Figure Note Both IOUT IOUT must ground virtual ground operational amplifier VREF every millivolt offset between IOUT IOUT 005% linearity error will introduced Note Human body model discharged through resistor Note Absolute Maximum Ratings indicate limits beyond which damage device occur electrical specifications apply when operating device beyond specified operating conditions Note maximum power dissipation must derated elevated temperatures dictated TJMAX ambient temepature maximum allowable power dissipation temperature (TJMAX number given Absolute Maximum Ratings whichever lower this device TJMAX typical junction-to-ambient thermal resistance package when board mounted package this number this number
Typical Performance Characteristics
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FIGURE Digital Input Threshold Ambient Temperature
FIGURE Gain Error Variation
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Typical Applications
following applications also valid 12-bit systems using DAC1220 additional digital inputs Operational Amplifier Bias Current (Figure bias current flows through internal feedback resistor BI-FET amps have therefore error they introduce negligible they strongly recommended DAC1020 applications Considerations output impedance ROUT modulated digital input code which causes modulation operational amplifier output offset therefore recommended adjust ROUT more than digital inputs high ROUT single digital input high ROUT approaches infinity inputs Operational Amplifier Adjust (Figure Connect digital inputs ground adjust potentiometer bring VOUT within from ground potential VREF less than finer adjustment required helpful increase resolution adjust procedure connecting resistor between inverting input ground After been adjusted remove Full-Scale Adjust (Figure Switch high digital inputs measure output voltage 500X potentiometer shown bring VOUT voltage equal VREF 1023 1024
SELECTING COMPENSATING OPERATIONAL AMPLIFIER Family LF357 LF356 LF351 LM741 Circuit Settling Time Circuit Small Signal
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VOUT VREF
VREF
1024
VOUT
1023 VREF 1024
where digital input high digital input
FIGURE Basic Connection Unipolar 2-Quadrant Multiplying Configuration (Digital Attenuator)
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Typical Applications (Continued)
FIGURE Full-Scale Adjust
FIGURE Alternate Full-Scale Adjust (Allows Increasing Decreasing Gain)
VOUT VREF VOUT2 VREF
where VREF signal
1024
1024
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1024
FIGURE Precision Analog-to-Digital Multiplier
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Typical Applications (Continued)
COMPLEMENTARY OFFSET BINARY (BIPOLAR) OPERATION DIGITAL INPUT VOUT
VREF VREF 1022 1024 VREF 1024 bVREF 1024 bVREF (1022 1024)
Note that VREF 1023 RLADDER 1024 doubling output range half resolution
IOUT IOUT
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VOUT VREF
where input high input
1024 1024
resistor adds ``thump''
allow full offset binary operation where output reaches zero half-scale code symmetrical output excursions required omit resistor
FIGURE Bipolar 4-Quadrant Multiplying Configuration Operational Amplifiers Adjust (Figure Switch digital inputs high adjust potentiometer bring output value equal tob(VREF 1024) Switch high remaining digital inputs Adjust potentiometer bring output value within from ground potential VREF finer adjust necessary already mentioned previous application Gain Adjust (Full-Scale Adjust) Assuming that external resistors matched better than gain adjust circuit same with previously discussed
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TRUE OFFSET BINARY OPERATION DIGITAL INPUT VOUT VREF 1022 1024 VREF
(2AVb
VOUT(PEAK) VREF Example VREF VOUT (swing) Then then
LM336 voltage reference
FIGURE Bipolar Configuration with Increased Output Swing
FIGURE Bipolar Configuration with Single
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Typical Applications
(Continued)
VOUT
VREF
1024
where VREF signal connecting feedback loop operational amplifier linear digitally control gain block realized
Note that with digital inputs gain amplifier
infinity that will saturate other words cannot divide VREF zero FIGURE Analog-to-Digital Divider Digitally Gain Controlled Amplifier)
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VOUT VREF
1024 1024
VOUT VREF
1023
where 1023 zeros A1-A9
1023
FIGURE Digitally controlled Amplifier-Attenuator
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Typical Applications (Continued)
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Output frequency fMAX Output voltage range peak
Excellent amplitude frequency stability with temperature pass filter shown corner (for output frequencies below
filter corner should reduced)
periodic function implemented modifying contents look
table
start problems
FIGURE Precision Frequency Sine Wave Oscillator Using Sine Look-Up
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Typical Applications (Continued)
MM74C00 MM74C32 MM74C74 MM74C193
NAND gates gates flip-flop Binary down counters
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Binary down counter digitally ``ramps''
output
stop counting desired 10-bit input code Senses down count overflow automatically
reverses direction count FIGURE Useful Digital Input Code Generator Attenuator Amplifier Circuits
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Definition Terms
Resolution Resolution defined reciprocal number discrete steps output directly related number switches bits within example DAC1020 1024 steps while DAC1220 4096 steps Therefore DAC1020 10-bit resolution while DAC1220 12-bit resolution Linearity Error Linearity error maximum deviation from straight line passing through endpoints transfer characteristic measured after calibrating zero (see adjust typical applications) fullscale Linearity error design parameter intrinsic device cannot externally adjusted Power Supply Sensitivity Power supply sensitivity measure effect power supply changes full-scale output Settling Time Full-scale settling time requires zero fullscale full-scale zero output change Settling time time required from code transition until output reaches within final output value Full-Scale Error Full-scale error measure output error between ideal actual device output Ideally DAC1020 full-scale VREFb1 VREF unipolar operation VFULL-SCALE 0000V 9902V Full-scale error adjustable zero shown Figure
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point test after zero full-scale adjust linearity error
shifting full-scale calibration Figure (b1) could pass ``best straight line'' (b2) test meet linearity error specification
Note (b1) (b2) above illustrate difference between ``end point'' National's linearity test ``best straight line'' test Note that both devices (b2) meet linearity error specification point test more ``real life'' characterizing
Connection Diagrams
DAC102X Dual-In-Line Package DAC1020 PLCC Package DAC122X Dual-In-Line Package
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Physical Dimensions inches (millimeters) unless otherwise noted
Cavity Dual-In-Line Package Order Number DAC1220LCJ DAC1222LCJ Package Number J18A
Molded Dual-In-Line Package Order Number DAC1020LCN DAC1021LCN DAC1022LCN Package Number N16A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package Order Number DAC1220LCN DAC1221LCN DAC1222LCN Package Number N18A
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DAC1020 DAC1021 DAC1022 10-Bit Binary Multiplying Converter DAC1220 DAC1222 12-Bit Binary Multiplying Converter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Plastic Leaded Chip Carrier Order Number DAC1020LCV DAC1020LIV Package Number V20A
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
National Semiconductor Corporation 1111 West Bardin Road Arlington 76017 1(800) 272-9959 1(800) 737-7018
critical component component life support device system whose failure perform reasonably expected cause failure life support device system affect safety effectiveness
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National Semiconductor Japan 81-043-299-2308 81-043-299-2408
National does assume responsibility circuitry described circuit patent licenses implied National reserves right time without notice change said circuitry specifications
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