CY3120/CY3125/CY3120J Warp2® VHDL Compiler CPLDs VHDL (IEEE

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CY3120/CY3125/CY3120J Warp2® VHDL Compiler CPLDs VHDL (IEEE

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CY3120/CY3125/CY3120J
Warp2® VHDL Compiler CPLDs
VHDL (IEEE 1076 1164) high-level language compiler Facilitates device-independent design Designs portable across multiple devices and/or environments Facilitates industry-standard simulation synthesis tools board system-level design Supports functions libraries facilitating modular design methodology Warp2® provides synthesis IEEE Standard 1076 1164 VHDL including: enumerated types operator overloading generate statements integers Several design entry methods support high low-level design descriptions: Behavioral VHDL (IF.THEN.ELSE; CASE.) Boolean Aldec Active-HDLFSM graphical Finite State Machine editor only) Structural VHDL (RTL) Designs include multiple VHDL entry methods single design State-of-the-art optimizations reduction algorithms Automatic selection optimal flip-flop type type/T type) Automatic assignment UltraGenSynthesis Technology Infers "modules" like adders, comparators, etc., from behavioral descriptions Replaces operator internally with architecture specific circuit based target device User selectable speed and/or area optimization block-by-block basis Supports Cypress Programmable Logic Devices Ultra37000CPLDs FLASH370iCPLDs MAX340CPLDs Industry standard PLDs (16V8, 20V8, 22V10) VHDL Verilog timing model output with third-party simulators
VERFICA TION VHDL, Verilog &Third-Party
Simulation Models
Timing simulation provided with Active-HDLSim from Aldec only): Graphical waveform simulator Entry modification on-screen waveforms Ability probe internal nodes Display inputs, outputs, High Impedance signals different colors Automatic clock pulse creation Support buses Support (Windows 95and Windows NT4.0) Support (Sun SolarisTM) On-line documentation help
Functional Description
Warp2 state-of-the-art compiler designing with Cypress Programmable Logic Devices. Warp2 utilizes subset IEEE 1076 1164 VHDL Hardware Description Language (HDL) design entry. Warp2 accepts VHDL, synthesizes optimizes entered design, outputs JEDEC file desired CPLD (see Figure Furthermore, Warp2 accepts VHDL produced Active-HDL graphical Finite State Machine editor only). simulation, Warp2 provides timing simulator only), well VHDL Verilog timing models with third party simulators.
DESIGN ENTRY
VHDL
State Machine
COMPILATION
UltraGen Synthesis
Automatic Fitting
JEDEC/Jam Programming File
Timing Simulator
Figure Warp2 VHDL Design Flow
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600 December 1998
CY3120/CY3125/CY3120J
VHDL Compiler VHDL (VHSIC [very high speed integrated circuit] Hardware Description Language) powerful language that standard behavioral design entry simulation, supported every major vendor tools. VHDL allows designers learn single language that useful facets design process. VHDL offers designers ability describe designs many different levels. highest level, designs entered description their behavior. This behavioral description tied specific target device. result, simulation done very early design verify correct functionality, which significantly speeds design process. Warp2's VHDL syntax also includes support intermediate level entry modes such state tables boolean entry. lowest level, designs described using gate-level (Register Transfer Language) descriptions. Warp2 gives designer flexibility intermix these entry modes. addition, VHDL allows design hierarchically, building entities terms other entities. This allows work either "top-down" (designing highest levels system interfaces first, then progressing greater greater detail) "bottom-up" (designing elementary building blocks system, then combining these build larger larger parts) with equal ease. Because VHDL IEEE standard, multiple vendors offer tools design entry simulation both high levels, synthesis designs different silicon targets. device-independent behavioral design entry gives users freedom easily migrate high volume technologies. wide availability VHDL tools provides complete vendor independence well. Designers begin their project using Warp2 Cypress CPLDs convert high volume gate arrays using same VHDL behavioral description with industry-standard synthesis tools. VHDL language allows users define their functions. User-defined functions allow users extend capabilities language build reusable libraries tested routines. result, user produce complex designs faster than with ordinary "flat" languages. VHDL also provides control over timing events processes. VHDL constructs that identify processes either sequential, concurrent, combination both. This essential when describing interaction complex state machines. VHDL rich programming language. flexibility reflects nature modern digital systems allows designers create accurate models digital designs. Because depth completeness, easy describe complex hardware system. addition, models created VHDL readily transported other Environments. Warp2 supports IEEE 1076 1164 VHDL including loops, generate statements, full hierarchical designs with packages, well synthesis enumerated types integers. part Warp2 description that specifies behavior structure design called entity/architecture pair. Entity/architecture pairs, their name implies, divided into parts: entity declaration, which declares design's interface signals (i.e., defines what external signals design has, what their directions types are), design architecture, which describes design's behavior structure. entity portion design file declaration what design presents outside world (the interface). each external signal, entity declaration specifies signal name, direction data type. addition, entity declaration specifies name which entity referenced design architecture. This section shows code segments from five sample design files. portion each example features entity declaration. Behavioral Description architecture portion design file specifies function design. shown Figure multiple design-entry methods supported Warp2. behavioral description VHDL often includes well known constructs such If.Then.Else, Case statements. Here code segment from simple state machine design (soda vending machine) that uses behavioral VHDL implement design: LIBRARY ieee; ieee.std_logic_1164.all; ENTITY drink PORT (nickel,dime,quarter,clock:#in std_logic; std_logic); drink;
ARCHITECTURE drink TYPE drinkState (zero,five,ten,fifteen, twenty,twentyfive,owedime); SIGNAL drinkstatus:drinkState; BEGIN PROCESS BEGIN WAIT UNTIL clock '1'; giveDrink '0'; returnDime '0'; returnNickel '0'; CASE drinkStatus WHEN zero (nickel '1') THEN drinkStatus five; ELSIF (dime '1') THEN drinkStatus Ten; ELSIF (quarter '1') THEN drinkStatus twentyfive; WHEN five
Designing with Warp2
Design Entry Warp2 descriptions specify: behavior structure design, mapping signals design pins PLD/CPLD (optional)
CY3120/CY3125/CY3120J
(nickel '1') THEN drinkStatus ten; ELSIF (dime '1') THEN drinkStatus fifteen; ELSIF (quarter '1') THEN giveDrink '1'; drinkStatus zero Several states omitted this example. omitted states ten, fifteen, twenty, twentyfive. WHEN owedime returnDime '1'; drinkStatus zero; when others This makes sure that state machine resets itself somehow gets into undefined state. drinkStatus zero; CASE; PROCESS; FSM; VHDL strongly typed language. comes with several predefined operators, such (add, not-equal-to). VHDL offers capability defining multiple meanings operators (such which results simplification code written. example, following code segment shows that "count count written such that count std_logic_vector, integer. LIBRARY ieee; ieee.std_logic_1164.all; work.std_arith.all; ENTITY sequence port (clk: std_logic; inout std_logic); sequence; ARCHITECTURE sequence SIGNAL count: std_logic_vector(3 downto BEGIN PROCESS BEGIN WAIT UNTIL '1'; CASE count WHEN x"0" x"1" '1'; count count WHEN x"4" x"5" '0'; count count WHEN x"8" x"9" '1'; count count WHEN others x"2" x"3" x"6" x"7" '0'; count (others '0'); CASE; PROCESS; FSM; this example, operator overloaded accept both integer std_logic arguments. Warp2 supports overloading operators. Functions major advantage VHDL ability implement functions. support functions allows designs reused simply specifying function passing appropriate parameters. Warp2 features some built-in functions such (truth-table function). function particularly useful state machine look-up table designs. following code describes seven-segment display decoder implemented with function: LIBRARY ieee; ieee.std_logic_1164.all; work.table_std.all; ENTITY seg7 PORT( inputs: STD_LOGIC_VECTOR outputs: STD_LOGIC_VECTOR SEG7; ARCHITECTURE mixed seg7 CONSTANT truthTable: ttf_table input& output -"0000"& "0111111", "0001"& "0000110", "0010"& "1011011", "0011"& "1001111", "0100"& "1100110", "0101"& "1101101", "0110"& "1111101", "0111"& "0000111", "1000"& "1111111", "1001"& "1101111", "101-"& "1111100", -creates pattern "111-"& "1111100" BEGIN outputs ttf(truthTable,inputs); mixed; Boolean Equations third design-entry method available Warp2 users Boolean equations. Figure displays schematic simple one-bit half adder. following code describes this one-bit half adder implemented Warp2 with Boolean equations:
CY3120/CY3125/CY3120J
carry
Figure One-Bit Half Adder LIBRARY ieee; ieee.std_logic_1164.all; -entity declaration ENTITY half_adder PORT std_logic; sum, carry std_logic); half_adder; -architecture body ARCHITECTURE behave half_adder BEGIN carry behave; Structural VHDL (RTL) While design methodologies described thus high-level entry methods, structural VHDL provides method designing very level. structural descriptions (also called RTL), designer simply lists components that make design specifies components wired together. Figure displays schematic simple 3-bit shift register following code shows this design described Warp2 using structural VHDL: LIBRARY ieee; ieee.std_logic_1164.all; work.rtlpkg.all; ENTITY shifter3 port STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC); shifter3; ARCHITECTURE struct shifter3 SIGNAL q0_temp, q1_temp, q2_temp STD_LOGIC; BEGIN PORT MAP(x,clk,q0_temp); PORT MAP(q0_temp,clk,q1_temp); PORT MAP(q1_temp,clk,q2_temp); q0_temp; q1_temp; q2_temp; struct;
Figure Three-Bit Shift Register Circuit Design design-entry methods described mixed desired. VHDL ability combine both high- low-level entry methods single file. flexibility power VHDL allows users Warp2 describe designs using whatever method appropriate their particular design.
Finite State Machine Editor only)
Aldec's Active-HDLFSM finite state machine editor, allows graphic design entry through graphical state diagrams. design represented graphically using state diagrams data flow logic. This tool will automatically generate code design.
Figure Active Finite State Machine Entry
Compilation
Once VHDL description design complete, compiled using Warp2. Although implementation with single command, compilation actually multistep process shown Figure first part compilation process same devices. input VHDL description synthesized logical representation design. Warp2 synthesis unique that input language (VHDL) supports device-independent design descriptions. Competing programmable logic compilers require very specific device-dependent information design description. Warp2 synthesis based UltraGen technology. This technology allows Warp2 infer "modules" like adders, multipliers, comparators, etc., from behavioral descriptions. Warp2 then replaces that operator internally with architecture specific
CY3120/CY3125/CY3120J
circuit based target device. This circuit "module" also pre-optimized either area speed, and,Warp2 uses appropriate implementation based user directives. second step compilation iterative process optimizing design fitting logic into targeted device. Logical optimization Warp2 accomplished using Espresso algorithms. optimized design automatically Warp2 fitter targeting CPLD. This fitter supports automatic manual placement assignments well automatic selection flip-flops. After optimization fitting, Warp2 creates JEDEC file specified CPLD. facilitate design conversion, JEDEC translator provided convert FLASH370i JEDEC files target Ultra37000 devices.
Product Ordering Information
Product Code CY3120R51 CY3125R51 CY3110JR51 Description Warp2 VHDL development system Warp2 VHDL development system Solaris Workstations Warp2 VHDL Japanese development system
Warp2 VHDL includes: CD-ROM with Warp2, Aldec Active-HDL FSM, on-line documentation (Getting Started Manual, User's Guide, Reference Manual) VHDL Programmable Logic Textbook Registration Card Release Notes Document 38-00218-I
Simulation only)
Warp2 includes post-synthesis timing simulator called Active-HDL Sim. Active-HDL features graphical waveform simulator that used simulate PLD/CPLD designs generated Warp2. simulator provides timing simulation PLDs/CPLDs features interactive waveform editing viewing. simulator also provides ability probe internal nodes, automatically generate clocks pulses. (Source level simulation support available with Warp3, [CY3130].) Warp2 will also output standard VHDL Verilog timing models. These models used with many third-party simulators perform functional timing verifications synthesized design.
Programming
result Warp2 compilation JEDEC file that implements input design targeted device. Using this file, Cypress devices programmed qualified third-party programmer. Cypress's FLASH370i Ultra37000 In-System Reprogrammable(ISRTM) devices also programmed board with programmer. JEDEC files used program FLASH370i CPLDs converted files Cypress's software with Ultra37000 CPLDs. Once format, Ultra37000 CPLDs programmed using player with Cypress's software cable. more information Cypress's software Ultra37000 Programming (CY3700i) FLASH370i Programming (CY3600i) data sheet.
System Requirements
equivalent (486-66MHz higher recommended) Mbytes Mbytes recommended) Mbytes Disk Space CD-ROM drive Windows (including Japanese) Windows Workstations SPARC Solaris Mbytes Mbytes recommended) CD-ROM drive
Figure Warp2 Graphical User Interface VHDL Book Warp2 Warp3 registered trademarks UltraGen, Ultra37000, MAX340, Impulse3, ISR, System Reprogrammable, FLASH370i trademarks Cypress Semiconductor Corporation. Windows Windows trademarks Microsoft Corporation. Solaris trademark Microsystems Corporation. Active-HDL trademark Aldec Incorporated.
Cypress Semiconductor Corporation, 1998. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

CY3120/CY3125/CY3120J Warp2® VHDL Compiler CPLDs VHDL (IEEE

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