CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb 2-Word Burst SRAM with

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CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb 2-Word Burst SRAM with

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310V18
CY7C1310V18 CY7C1312V18 CY7C1314V18
18-Mb 2-Word Burst SRAM with QDRTM-II Architecture
Features
Separate Independent Read Write Data Ports Supports concurrent transactions Clock High Bandwidth 2-Word Burst accesses Double Data Rate (DDR) interfaces both Read Write Ports (data transferred MHz) @250 input clocks precise timing SRAM uses rising edges only output clocks accounts clock skew flight time mismatches Single multiplexed address input latches address inputs both Read Write ports Separate Port Selects depth expansion Synchronous internally self-timed writes Available x18, configurations 1.8V core power supply with HSTL Inputs Outputs 13x15 1.0-mm pitch fBGA package, ball (11x15 matrix) Variable drive HSTL output buffers Extended HSTL output voltage (1.4V-VDD) JTAG Interface
Functional Description
1.8V Synchronous Pipelined SRAMs, equipped with QDRTM-II architecture. QDR-II architecture consists separate ports access memory array. Read port dedicated Data Outputs support Read operations Write Port dedicated Data Inputs support Write operations. QDR-II architecture separate data inputs data outputs completely eliminate need "turn-around" data required with common devices. Access each port accomplished through common address bus. Read address latched rising edge clock Write address latched rising edge clock. Accesses QDR-II Read Write ports completely independent another. order maximize data throughput, both Read Write ports equipped with Double Data Rate (DDR) interfaces. Each address location associated with 8-bit words (CY7C1310V18) 18-bit words (CY7C1312V18) 36-bit words (CY7C1314V18) that burst sequentially into device. Since data transferred into device every rising edge both input clocks (K/K C/C), memory bandwidth maximized while simplifying system design eliminating "turn-arounds." Depth expansion accomplished with Port Selects each port. Port selects allow each port operate independently. synchronous inputs pass through input registers controlled input clocks. data outputs pass through output registers controlled single clock domain) input clocks. Writes conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1310V18 CY7C1312V18 CY7C1314V18 512K
Logic Block Diagram (CY7C1310V18)
D[7:0] Write Write Address Register
Read Add. Decode
Write Add. Decode
A(19:0)
Address Register
A(19:0)
Array
Array
Gen.
Control Logic
Read Data Reg. Control Logic Reg. Reg. Reg.
VREF BWS[1:0]
Q[7:0]
RAMs Quad Data Rate RAMs comprise family products developed Cypress, Hitachi, IDT, Micron, NEC, Samsung technology.
Cypress Semiconductor Corporation Document 38-05180 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised October 2001
CY7C1310V18 CY7C1312V18 CY7C1314V18
Logic Block Diagram (CY7C1312V18)
D[17:0]
Write Write Address Register
Read Add. Decode
Write Add. Decode
A(18:0)
Address Register
A(18:0)
512K Array
512K Array
Gen.
Control Logic
Read Data Reg. Control Logic Reg. Reg. Reg.
VREF BWS[1:0]
Q[17:0]
Logic Block Diagram (CY7C1314V18)
D[35:0]
Write Write Address Register
Read Add. Decode
Write Add. Decode
A(17:0)
Address Register
A(17:0)
256K Array
256K Array
Gen.
Control Logic
Read Data Reg. Control Logic Reg. Reg. Reg.
VREF BWS[3:0]
Q[35:0]
Document 38-05180 Rev.
Page
CY7C1310V18 CY7C1312V18 CY7C1314V18
Selection Guide
Maximum Operating Frequency (MHz) Maximum Operating Current (mA)
Configurations
CY7C1310V18
DOFF
GND/72M VREF
VDDQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
BWS1
BWS0
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDDQ
GND/36M VREF
Document 38-05180 Rev.
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Configurations (continued)
CY7C1312V18
CY7C1310V18 CY7C1312V18 CY7C1314V18
DOFF
VREF
VDDQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
BWS1
BWS0
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDDQ
GND/72M VREF
GND/144M NC/36M
CY7C1314V18 (512k
DOFF
VREF
VDDQ
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
BWS2 BWS3
BWS1 BWS0
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDDQ
VREF
GND/288M NC/72M
NC/36M GND/144M
Document 38-05180 Rev.
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Definitions
Name D[x:0] InputSynchronous Description
CY7C1310V18 CY7C1312V18 CY7C1314V18
Data input signals, sampled rising edge clocks during valid write operations. CY7C1310V18 D[7:0] CY7C1312V18 D[17:0] CY7C1314V18 D[35:0] Write Port Select, active LOW. Sampled rising edge clock. When asserted active, write operation initiated. Deasserting will deselect Write port. Deselecting Write port will cause D[x:0] ignored. Byte Write Select active LOW. Sampled rising edge clocks during write operations. Used select which byte written into device during current portion write operations. Bytes written remain unaltered. CY7C1310V18 BWS0 controls D[3:0] BWS1 controls D[7:4]. CY7C1312V18 BWS0 controls D[8:0] BWS1 controls D[17:9]. CY7C1314V18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] BWS3 controls D[35:27] byte writes sampled same edge data. Deselecting Byte Write Select will cause corresponding byte data ignored written into device. Address Inputs. Sampled rising edge clock during active read write operations. These address inputs multiplexed both Read Write operations. Internally, device organized arrays each CY7C1310V18, arrays each 512K CY7C1312V18 256K arrays each 256K CY7C1314V18. Therefore, only address inputs needed access entire memory array CY7C1310V18, address inputs CY7C1312V18 address inputs CY7C1314V18. These inputs ignored when appropriate port deselected. Data Output signals. These pins drive requested data during Read operation. Valid data driven rising edge both clocks during Read operations when single clock mode. When Read port deselected, Q[x:0] automatically three-stated. CY7C1310V18 Q[7:0] CY7C1312V18 Q[17:0] CY7C1314V18 Q[35:0] Read Port Select, active LOW. Sampled rising edge Positive Input Clock (K). When active, Read operation initiated. Deasserting will cause Read port deselected. When deselected, pending access allowed complete output drivers automatically three-stated following next rising edge clock. Each read access consists burst sequential transfers. Positive Output Clock Input. used conjunction with clock Read data from device. used together deskew flight times various devices board back controller. application example further details. Negative Output Clock Input. used conjunction with clock Read data from device. used together deskew flight times various devices board back controller. application example further details. Positive Input Clock Input. rising edge used capture synchronous inputs device drive data through Q[x:0] when single clock mode. accesses initiated rising edge Negative Input Clock Input. used capture synchronous inputs being presented device drive data through Q[x:0] when single clock mode. Output Impedance Matching Input. This input used tune device outputs system data impedance. Q[x:0] output impedance where resistor connected between ground. Alternately, this connected directly VDD, which enables minimum impedance mode. This cannot connected directly left unconnected. Turn Off. This input used turn inside device. timings turned operation will different from those listed this data sheet. More details this operation found application note, "DLL Operation QDR-II." Page
InputSynchronous InputSynchronous
BWS0, BWS1, BWS2, BWS3
InputSynchronous
Q[x:0]
OutputsSynchronous
InputSynchronous
Input-Clock
Input-Clock
Input-Clock
Input-Clock Input
DOFF
Input
Document 38-05180 Rev.
Definitions (continued)
Name NC/36M GND/72M GND/144M VREF VDDQ Output Input Input Input Input Input Input Input InputReference Power Supply Ground Power Supply JTAG. JTAG. JTAG. JTAG. Description
CY7C1310V18 CY7C1312V18 CY7C1314V18
connects inside package. tied voltage level. Address expansion 36M. This connected tied voltage level. Address expansion 72M. This should tied devices. Address expansion 144M. This should tied devices. Reference Voltage Input. Static input used reference level HSTL inputs Outputs well measurement points. Power supply inputs core device. Should connected 1.8V power supply. Ground device. Should connected ground system. Power supply inputs outputs device. Should connected 1.5V power supply. connect Read Operations CY7C1312V18 organized internally 512Kx36 SRAM. Accesses completed burst sequential 18-bit data words. Read operations initiated asserting active rising edge Positive Input Clock (K). address presented Address inputs stored Read address register. Following next clock rise corresponding lowest order 18-bit word data driven onto Q[17:0] using output timing reference. subsequent rising edge next 18-bit data word driven onto Q[17:0]. requested data will valid 0.35 from rising edge output clock (C/C, 250-MHz device). Synchronous internal circuitry will automatically three-state outputs following next rising edge Output Clocks (C/C). This will allow seamless transition between devices without insertion wait states depth expanded memory. Write Operations Write operations initiated asserting active rising edge Positive Input Clock (K). following clock rise, data presented D[17:0] latched stored into lower 18-bit Write Data register provided BWS[1:0] both asserted active. subsequent rising edge Negative Input Clock (K), information presented D[17:0] also stored into Write Data Register provided BWS[1:0] both asserted active. bits data then written into memory array specified location. When deselected, write port will ignore inputs after pending Write operations have been completed. Byte Write Operations Byte Write operations supported CY7C1312V18. write operation initiated described Write Operation section above. bytes that written determined BWS0 BWS1 which sampled with each 18-bit data word. Asserting appropriate Byte Write Select input Page
Introduction
Functional Overview synchronous pipelined Burst SRAMs equipped with both Read port Write port. Read port dedicated Read operations Write port dedicated Write operations. Data flows into SRAM through Write port through Read Port. These devices multiplex address inputs order minimize number address pins required. having separate Read Write ports, QDR-II completely eliminates need "turn-around" data avoids possible data contention, thereby simplifying system design. Each access consists 8-bit data transfers case CY7C1310V18, 18-bit data transfers case CY7C1312V18 36-bit data transfers case CY7C1314V18, clock cycles. Accesses both ports initiated rising edge positive Input Clock (K). synchronous input timings referenced from rising edge input clocks output timings referenced output clocks when single clock mode). synchronous data inputs (D[x:0]) inputs pass through input registers controlled input clocks synchronous data outputs (Q[x:0]) outputs pass through output registers controlled rising edge output clocks when single clock mode). synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled rising edge input clocks following descriptions take CY7C1312V18 example. However, same true other QDR-II SRAMs, CY7C1310V18 CY7C1314V18.
Document 38-05180 Rev.
during data portion write will allow data being presented latched written into device. Deasserting Byte Write Select input during data portion write will allow data stored device that byte remain unaltered. This feature used simplify Read/Modify/Write operations Byte Write operation. Single Clock Mode CY7C1312V18 used with single clock that controls both input output registers. this mode, device will recognize only single pair input clocks that control both input output registers. This operation identical operation device zero skew between clocks. timing parameters remain same this mode. this mode operation, user must HIGH power This function strap option alterable during device operation. Concurrent Transactions Read Write ports CY7C1312V18 operate completely independently another. Since each port latches address inputs different clock edges, user Read Write location, regardless transaction other port. Also, reads writes started same clock cycle. ports access same location same time, SRAM will deliver most recent information associated with specified address location. This includes forwarding data from Write cycle that initiated previous clock rise. Depth Expansion
CY7C1310V18 CY7C1312V18 CY7C1314V18
CY7C1312V18 Port Select input each port. This allows easy depth expansion. Both Port Selects sampled rising edge Positive Input Clock only (K). Each port select input deselect specified port. Deselecting port will affect other port. pending transactions (Read Write) will completed prior device being deselected. Programmable Impedance external resistor, must connected between SRAM allow SRAM adjust output driver impedance. value must value intended line impedance driven SRAM. allowable range guarantee impedance matching with tolerance ±10% between 350, with VDDQ 1.5V. output impedance adjusted every 1024 cycles adjust drifts supply voltage temperature. Echo Clocks Echo clocks provided QDR-II simplify data capture high-speed systems. echo clocks generated QDR-II. referenced with respect referenced with respect These free-running clocks synchronized output clock QDR-II. single clock mode, generated with respect generated with respect timings echo clocks shown Timing table.
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CY7C1310V18 CY7C1312V18 CY7C1314V18
Application Example[1]
VTERM=VDDQ/2
SRAM
SRAM
Cntr. Add.
Cntr. Add.
R=50
Memory Controller
Add. Cntr.
CLK/CLK (input) CLK/CLK (output)
R=50
VT=VDDQ/2
Truth Table[
Operation Write Cycle: Load address rising edge clock; input write data rising edges. Read Cycle: Load address rising edge clock; wait half cycle; read data rising edges. NOP: Operation Standby: Clock Stopped 00)at
Stopped
High-Z Previous State
High-Z Previous State
Notes: above application shows CY7C1312V18 being used. This holds true CY7C1310V18 CY7C1314V18 well. "Don't Care," Logic HIGH, Logic LOW, represents rising edge. Device will power-up deselected outputs three-state condition. represents address location latched devices when transaction initiated. A+00, A+01 represents internal address sequence burst. represents cycle which read/write operation started. first second clock cycles respectively succeeding clock cycle. Data inputs registered rising edges. Data outputs delivered rising edges, except when single clock mode. recommended that when clock stopped. This essential, permits most rapid restart overcoming transmission line charging symmetrically.
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Write Cycle Descriptions[2, 8](CY7C1310V18 CY7C1312V18)
BWS0 BWS1 Comments
CY7C1310V18 CY7C1312V18 CY7C1314V18
During Data portion Write sequence CY7C1310V18 both nibbles (D[7:0]) written into device, CY7C1312V18 both bytes (D[17:0]) written into device. During Data portion Write sequence CY7C1310V18 both nibbles (D[7:0]) written into device, CY7C1312V18 both bytes (D[17:0]) written into device. During Data portion Write sequence CY7C1310V18 only lower nibble (D[3:0]) written into device. D[7:4] will remain unaltered, CY7C1312V18 only lower byte (D[8:0]) written into device. D[17:9] will remain unaltered. During Data portion Write sequence CY7C1310V18 only lower nibble (D[3:0]) written into device. D[7:4] will remain unaltered, CY7C1312V18 only lower byte (D[8:0]) written into device. D[17:9] will remain unaltered. During Data portion Write sequence CY7C1310V18 only upper nibble (D[7:4]) written into device. D[3:0] will remain unaltered, CY7C1312V18 only upper byte (D17:9]) written into device. D[8:0] will remain unaltered. During Data portion Write sequence CY7C1310V18 only upper nibble (D[7:4]) written into device. D[3:0] will remain unaltered, CY7C1312V18 only upper byte (D17:9]) written into device. D[8:0] will remain unaltered. data written into devices during this portion write operation. data written into devices during this portion write operation.
Note: Assumes Write cycle initiated Write Port Cycle Description Truth Table. BWS0 BWS1 altered different portions write cycle, long set-up hold requirements achieved.
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Write Cycle Descriptions[2, 8](CY7C1314V18)
BWS0 BWS1 BWS2 BWS3
CY7C1310V18 CY7C1312V18 CY7C1314V18
Comments During Data portion Write sequence, four bytes (D[35:0]) written into device. During Data portion Write sequence, four bytes (D[35:0]) written into device. During Data portion Write sequence, only lower byte (D[8:0]) written into device. D[35:9] will remain unaltered. During Data portion Write sequence, only lower byte (D[8:0]) written into device. D[17:9] will remain unaltered. During Data portion Write sequence, only byte (D[17:9]) written into device. D[8:0] D[35:18] will remain unaltered. During Data portion Write sequence, only byte (D[17:9]) written into device. D[8:0] D[35:18] will remain unaltered. During Data portion Write sequence, only byte (D[26:18]) written into device. D[17:0] D[35:27] will remain unaltered. During Data portion Write sequence, only byte (D[26:18]) written into device. D[17:0] D[35:27] will remain unaltered. During Data portion Write sequence, only byte (D[35:27]) written into device. D[26:0] will remain unaltered.
During Data portion Write sequence, only byte (D[35:27]) written into device. D[26:0] will remain unaltered. data written into device during this portion write operation. data written into device during this portion write operation.
IEEE 1149.1 Serial Boundary Scan (JTAG)
QDR-II devices incorporate serial boundary scan test access port (TAP) FBGA package. This port operates accordance with IEEE Standard 1149.1-1900, does have functions required full 1149.1 compliance. These functions from IEEE specification excluded because their inclusion places added delay critical speed path SRAM. Note that controller functions manner that does conflict with operation other devices using 1149.1 fully compliant TAPs. operates using JEDEC standard 1.8V logic levels. Disabling JTAP Feature possible operate SRAM without using JTAG feature. disable controller, must tied (VSS) prevent clocking device. inDocument 38-05180 Rev.
ternally pulled unconnected. They alternately connected through pull-up resistor. should left unconnected. Upon power-up, device will come reset state which will interfere with operation device. Test Access Port (TAP) Test Clock test clock used only with controller. inputs captured rising edge TCK. outputs driven from falling edge TCK. Test Mode Select input used give commands controller sampled rising edge TCK. allowable leave this unconnected used. pulled internally, resulting logic HIGH level. Page
Test Data-In (TDI) used serially input information into registers connected input registers. register between chosen instruction that loaded into instruction register. information loading instruction register, Controller State Diagram. internally pulled unconnected unused application. connected most significant (MSB) register. Test Data (TDO) output used serially clock data-out from registers. output active depending upon current state state machine (see Instruction codes). output changes falling edge TCK. connected least significant (LSB) register. Performing Reset Reset performed forcing HIGH (VDD) five rising edges TCK. This RESET does affect operation SRAM performed while SRAM operating. power-up, reset internally ensure that comes high-Z state. Registers Registers connected between pins allow data scanned into SRAM test circuitry. Only register selected time through instruction registers. Data serially loaded into rising edge TCK. Data output falling edge TCK. Instruction Register Three-bit instructions serially loaded into instruction register. This register loaded when placed between pins shown Controller Block Diagram. Upon power-up, instruction register loaded with IDCODE instruction. also loaded with IDCODE instruction controller placed reset state described previous section. When controller Capture state, least significant bits loaded with binary "01" pattern allow fault isolation board level serial test path. Bypass Register save time when serially shifting data through registers, sometimes advantageous skip certain chips. bypass register single-bit register that placed between pins. This allows data shifted through SRAM with minimal delay. bypass register (VSS) when BYPASS instruction executed. Boundary Scan Register boundary scan register connected input output pins SRAM. Several connect (NC) pins also included scan register reserve pins higher density devices. boundary scan register loaded with contents Input Output ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. EXTEST, SAMPLE/PRELOAD SAMPLE instrucDocument 38-05180 Rev.
CY7C1310V18 CY7C1312V18 CY7C1314V18
tions used capture contents Input Output ring. Boundary Scan Order tables show order which bits connected. Each corresponds bumps SRAM package. register connected TDI, connected TDO. Identification (ID) Register register loaded with vendor-specific, 32-bit code during Capture-DR state when IDCODE command loaded instruction register. IDCODE hardwired into SRAM shifted when controller Shift-DR state. register vendor code other information described Identification Register Definitions table. Instruction Eight different instructions possible with three-bit instruction register. combinations listed Instruction Code table. Three these instructions listed RESERVED should used. other five instructions described detail below. controller used this SRAM fully compliant 1149.1 convention because some mandatory 1149.1 instructions fully implemented. controller cannot used load address, data control signals into SRAM cannot preload Input output buffers. SRAM does implement 1149.1 commands EXTEST INTEST PRELOAD portion SAMPLE/PRELOAD; rather performs capture Input Output ring when these instructions executed. Instructions loaded into controller during Shift-IR state when instruction register placed between TDO. During this state, instructions shifted through instruction register through pins. execute instruction once shifted controller needs moved into Update-IR state. EXTEST EXTEST mandatory 1149.1 instruction which executed whenever instruction register loaded with EXTEST implemented controller, therefore this device compliant 1149.1 standard. controller does recognize all-0 instruction. When EXTEST instruction loaded into instruction register, SRAM responds SAMPLE PRELOAD instruction been loaded. IDCODE IDCODE instruction causes vendor-specific, 32-bit code loaded into instruction register. also places instruction register between pins allows IDCODE shifted device when controller enters Shift-DR state. IDCODE instruction loaded into instruction register upon power-up whenever controller given test logic reset state. SAMPLE SAMPLE instruction causes boundary scan register connected between pins when controller Shift-DR state.
Page
SAMPLE/PRELOAD SAMPLE/PRELOAD 1149.1 mandatory instruction. PRELOAD portion this instruction implemented, controller fully 1149.1 compliant. When SAMPLE/PRELOAD instructions loaded into instruction register controller Capture-DR state, snapshot data inputs output pins captured boundary scan register. user must aware that controller clock only operate frequency MHz, while SRAM clock operates more than order magnitude faster. Because there large difference clock frequencies, possible that during Capture-DR state, input output will undergo transition. then capture signal while transition (metastable state). This will harm device, there guarantee value that will captured. Repeatable results possible. guarantee that boundary scan register will capture correct value signal, SRAM signal must stabilized long enough meet controller's capture set-up plus hold times (tCS tCH). SRAM clock inputs might captured correctly there design stop slow) clock during SAMPLE/PRELOAD instruction. this
CY7C1310V18 CY7C1312V18 CY7C1314V18
issue, still possible capture other signals simply ignore value captured boundary scan register. Once data captured, possible shift data putting into Shift-DR state. This places boundary scan register between pins. Note that since PRELOAD part command implemented, putting into Update Update-DR state while performing SAMPLE/PRELOAD instruction will have same effect Pause-DR command. Bypass When BYPASS instruction loaded instruction register placed Shift-DR state, bypass register placed between pins. advantage BYPASS instruction that shortens boundary scan path when multiple devices connected together board. Reserved These instructions implemented reserved future use. these instructions.
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Controller State Diagram
CY7C1310V18 CY7C1312V18 CY7C1314V18
TEST-LOGIC RESET
TEST-LOGIC/ IDLE SELECT DR-SCAN SELECT IR-SCAN
CAPTURE-DR
CAPTURE-IR
SHIFT-DR
SHIFT-IR
EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR
EXIT1-IR PAUSE-IR
EXIT2-IR
UPDATE-IR
Note: next each state represents value rising edge TCK.
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Controller Block Diagram
CY7C1310V18 CY7C1312V18 CY7C1314V18
Bypass Register Selection Circuitry Instruction Register Selection Circuitry
Identification Register
Boundary Scan Register
Controller
Electrical Characteristics Over Operating Range[9,
Parameter VOH1 VOH2 VOL1 VOL2 Description Output HIGH Voltage Output HIGH Voltage Output Voltage Output Voltage Input HIGH Voltage Input Voltage Input OutputLoad Current VDDQ Test Conditions -2.0 -100 0.65VDD -0.3 Min. 0.45 0.45 0.35VDD Max. Unit
Notes: Voltage referenced Ground. Overshoot: VIH(AC)<VDD 0.5V tTCYC/2, Undershoot VIL(AC)< 0.5V tTCYC/2; Power-up: VIH<1.8V VDD<1.8V VDDQ 1.4V These characteristic pertain inputs (TMS, TCK, TDO). Parallel load levels specified Electrical Characteristics Table. means core supply voltage.
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Switching Characteristics Over Operating Range[13,
Parameter tTCYC Clock Cycle Time Clock Frequency Clock HIGH Clock Description Min.
CY7C1310V18 CY7C1312V18 CY7C1314V18
Max.
Unit
Set-up Times tTMSS tTDIS Hold Times tTMSH tTDIH Hold after Clock Rise Hold after Clock Rise Capture Hold after Clock Rise Set-up Clock Rise Set-up Clock Rise Capture Set-up Rise
Output Times tTDOV tTDOX Clock Valid Clock Invalid
Notes: refer set-up hold time requirements latching data from boundary scan register. Test conditions specified using load test conditions. tR/tF
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Timing Test Conditions[14]
CY7C1310V18 CY7C1312V18 CY7C1314V18
0.9V INPUT PULSES 1.8V 0.9V
Test Clock
tTMSS tTMSH
tTCYC
Test Mode Select
tTDIS tTDIH
Test Data-In
Test Data-Out
tTDOX tTDOV
Document 38-05180 Rev.
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Identification Register Definitions Updated)
Value Instruction Field Revision Number (31:29) Cypress Device (28:12) Cypress JEDEC (11:1) Register Presence CY7C13XXV18 01011010011010110 00000110100
CY7C1310V18 CY7C1312V18 CY7C1314V18
Description Version number. Defines type SRAM. Allows unique identification SRAM vendor. Indicate presence register.
Scan Register Sizes Updated)
Register Name Instruction Bypass Boundary Scan Size
Instruction Codes
Instruction EXTEST Code Description Captures Input/Output ring contents. Places boundary scan register between TDO. This instruction 1149.1 compliant. EXTEST command implemented these devices will place output buffers into high-Z condition. output buffers need high-Z condition, this accomplished deselecting Read port. Loads register with vendor code places register between TDO. This operation does affect SRAM operation. Captures Input/Output contents. Places boundary scan register between TDO. SAMPLE command implemented these devices will place output buffers into high-Z condition. Use: This instruction reserved future use. Captures Input/Output ring contents. Places boundary scan register between TDO. Does affect SRAM operation. This instruction does implement 1149.1 preload function therefore 1149.1 compliant. Use: This instruction reserved future use. Use: This instruction reserved future use. Places bypass register between TDO. This operation does affect SRAM operation.
IDCODE SAMPLE
RESERVED SAMPLE/PRELOAD
RESERVED RESERVED BYPASS
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Boundary Scan Order Updated)
Reserved GND/72M NC/18M(1) BWS0 Signal Name (Don't Care) Bump
CY7C1310V18 CY7C1312V18 CY7C1314V18
Boundary Scan Order Updated)
BWS1 NC/36M(1) GND/144M Reserved Signal Name (Don't Care) Bump
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Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C +150°C Ambient Temperature with Power Applied. -55°C +125°C Supply Voltage Relative -0.5V +2.9V Voltage Applied Outputs High State[10] -0.5V VDDQ 0.5V Input Voltage[10] -0.5V VDDQ 0.5V
CY7C1310V18 CY7C1312V18 CY7C1314V18
Current into Outputs (LOW) Static Discharge Voltage >2001V (per MIL-STD-883, Method 3015) Latch-Up Current. >200
Operating Range
Range Com'l Ambient Temperature[15] +70°C VDDQ 1.4V
Electrical Characteristics Over Operating Range
Parameter VDDQ VREF Description Power Supply Voltage Supply Voltage Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input Load Current Output Leakage Current Input Reference Voltage[16] Operating Supply
[10]
Test Conditions
Min.
Typ.
Max. VDDQ VDDQ+0.3 VREF 0.95
Unit
-2.0 Nominal Impedance Nominal Impedance
VDDQ VDDQ VREF -0.3 VREF -0.3 0.75
[10]
VDDQ VDDQ, Output Disabled Typical Value 0.75V Max., IOUT fMAX 1/tCYC
0.68
Operating Supply
Max., IOUT fMAX 1/tCYC
ISB1
Automatic Power-Down Current,
Max. VDD, Both Ports Deselected, fMAX 1/tCYC, Inputs Static Max. VDD, Both Ports Deselected, fMAX 1/tCYC, Inputs Static
ISB1
Automatic Power-Down Current,
Notes: case temperature. VREF Min. 0.68V 0.46VDDQ, whichever larger, VREF Max. 0.95V 0.54VDDQ, whichever smaller.
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Switching Characteristics Over Operating Range[18]
Parameter tCYC tKHKH tKHCH Description Clock Clock Cycle Time Input Clock (K/K C/C) HIGH Input Clock (K/K C/C) Clock Rise Clock Rise Rise (rising edge rising edge) Clock Rise Clock Rise (rising edge rising edge) Min. Max. Min. Max. 2.75
CY7C1310V18 CY7C1312V18 CY7C1314V18
Min. Max. Unit
Set-up Times Hold Times Address Hold after Clock Rise Control Hold after Clock Rise (RPS, WPS, BWS0, BWS1) D[17:0] Hold after Clock Rise Address Set-up Clock Rise Control Set-up Clock Rise (RPS, WPS, BWS0, BWS1) D[17:0] Set-up Clock Rise
Output Times tDOH tCCQO tCQOH tCQD tCLZ tCHZ Timing lock Clock Phase Jitter Lock Time 1024 0.10 1024 0.13 1024 0.15 cycles Clock Rise Single Clock Mode) Data Valid[17] Data Output Hold after Output Clock Rise (Active Active) Clock Rise Echo Clock Valid Echo Clock Hold after Clock Rise Echo Clock High Data Change Clock Rise Low-Z[18, Clock Rise High-Z (Active High-Z)
[18,
-0.35 -0.33 -0.33 -0.35
0.35 0.33 0.35 0.35
-0.38 -0.36 -0.36 -0.38
0.38 0.36 0.38 0.38
-0.40 -0.38 -0.38 -0.40
0.40 0.38 0.40
Notes: Unless otherwise noted, test conditions assume signal transition time V/ns, timing reference levels 0.75V, VREF 0.75V, 250, VDDQ 1.5V, input pulse levels 0.25V 1.25V, output loading specified IOL/IOH load capacitance shown Test Loads. tCHZ, tCLZ, specified with load capacitance part Test Loads. Transition measured from steady-state voltage. given voltage temperature tCHZ less than tCLZ tCHZ less than tCO.
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Capacitance[20]
Parameter CCLK Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions 25°C, MHz, 1.8V VDDQ 1.5V Max.
CY7C1310V18 CY7C1312V18 CY7C1314V18
Unit
Note: Tested initially after design process change that affect these parameters.
Test Loads Waveforms
VDDQ/2
VREF OUTPUT Device Under Test VDDQ/2 VREF VDDQ/2 INPUT PULSES 1.25V 0.75V 0.25V
[17]
VREF 0.75V
OUTPUT Device Under Test
INCLUDING SCOPE
Document 38-05180 Rev.
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CY7C1310V18 CY7C1312V18 CY7C1314V18
Switching Waveforms
Read/Deselect Sequence
Read Read Deselect Read Deselect Deselect
tKHKH tKHKH
tCYC
Data
tKHCH tCLZ
Q(A)
Q(A+1)
Q(B)
Q(B+1)
Q(C)
Q(C+1)
tDOH tCHZ
tCQD tCQD
tKHKH
tKHCH
tCQOH tCCQO tCCQO tCQOH
DON'T CARE
UNDEFINED
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Switching Waveforms (continued)
Write/Deselect Sequence
CY7C1310V18 CY7C1312V18 CY7C1314V18
Write
Deselect
Write
Deselect
Deselect
Deselect
tCYC
BWSx
Data
D(A)
D(A+1)
D(B)
D(B+1)
reference Data Outputs affect Write operations. Activity Read Port unknown. BWSx LOW=Valid, Byte writes allowed, Byte write table details. DON'T CARE UNDEFINED
Document 38-05180 Rev.
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Switching Waveforms (continued)
Read/Write/Deselect Sequence
Read/Write Read/Write Read/Write Read Deselect
CY7C1310V18 CY7C1312V18 CY7C1314V18
Deselect
D[x:0] Q[x:0]
D(B)
D(B+1)
D(D)
D(D+1)
D(E)
D(E+1)
Q(A)
Q(A+1)
Q(C)
Q(C+1)
Q(E)
Q(G+1) Q(E+1)
Q(F)
Q(F+1)
DON'T CARE
UNDEFINED
Document 38-05180 Rev.
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Ordering Information
Speed (MHz) Ordering Code CY7C1310V18-250BZC CY7C1310V18-200BZC CY7C1310V18-167BZC CY7C1312V18-250BZC CY7C1312V18-200BZC CY7C1312V18-167BZC CY7C1314V18-250BZC CY7C1314V18-200BZC CY7C1314V18-167BZC BB165 FBGA BB165 FBGA Package Name BB165 Package Type FBGA
CY7C1310V18 CY7C1312V18 CY7C1314V18
Operating Range Commercial
Commercial
Commercial
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Package Diagram
165-Ball FBGA 1.35 BB165
CY7C1310V18 CY7C1312V18 CY7C1314V18
51-85122
Document 38-05180 Rev.
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Cypress Semiconductor Corporation, 2001. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
Revision History
CY7C1310V18 CY7C1312V18 CY7C1314V18
Document Title: 18-Mb 2-Word Burst SRAMs with QDR-II Architecture Document Number: 38-05180 REV. 110859 ISSUE DATE 11/09/01 ORIG. CHANGE DESCRIPTION CHANGE Data Sheet
Document 38-05180 Rev.
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CY7C1310V18 CY7C1312V18 CY7C1314V18 18-Mb 2-Word Burst SRAM with

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