CY3110/CY3115/CY3110J Warp2® Verilog Compiler CPLDs Verilog

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CY3110/CY3115/CY3110J Warp2® Verilog Compiler CPLDs Verilog

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CY3110/CY3115/CY3110J
Warp2® Verilog Compiler CPLDs
Verilog (IEEE 1364) high-level language compiler Facilitates device independent design Designs portable across multiple devices and/or environments Facilitates industry-standard simulation synthesis tools board system-level design Supports functions libraries facilitating modular design methodology Warp2® provides synthesis IEEE Standard 1364 Verilog including: reduction conditional operators blocking non-blocking procedural assignments while loop integers Several design entry methods support high low-level design descriptions: Behavioral Verilog (IF.ELSE; CASE.) Boolean Structural Verilog (RTL)
DESIGN ENTRY
Ability probe internal nodes Display inputs, outputs, High signals different colors Automatic clock pulse creation Support buses (Windows Windows 4.0) (Sun SolarisTM) On-line documentation help
Functional Description
Warp2 state-of-the-art compiler designing with Cypress Programmable Logic Devices. Warp2 utilizes subset IEEE 1364 Verilog Hardware Description Language (HDL) design entry. Another design entry method supported Warp2 through Aldec's Active-HDLgraphical Finite State Machine Editor only). Warp2 accepts Verilog, synthesizes optimizes entered design, outputs JEDEC desired CPLD (see Figure simulation, Warp2 provides timing simulator only), well VHDL Verilog models with third-party simulators.
Aldec Active-HDLFSM graphical Finite State Machine editor only) Designs include multiple Verilog entry methods single design State-of-the-art optimizations reduction algorithms Automatic selection optimal flip-flop type type/T type) Automatic assignment UltraGenSynthesis Technology Infers "modules" like adders, comparators, etc., from behavioral descriptions Replaces operator internally with architecture specific circuit based target device User selectable speed and/or area optimization block-by-block basis Supports Cypress Programmable Logic Devices Industry standard PLDs (16V8, 20V8, 22V10) MAX340CPLDs FLASH370iCPLDs Ultra37000CPLDs Verilog VHDL timing model output with third-party simulators Timing simulation provided with Active-HDLSim from Aldec only): Graphical waveform simulator Entry modification on-screen waveforms
Verilog
State Machine
UltraGen Synthesis COMPILATION
Automatic Fitting
VERFICA TION
JEDEC/Jam Programming File
Timing Simulator
VHDL, Verilog &Third-Party
Simulation Models
Figure Warp2 Verilog Design Flow
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600 October 1998
CY3110/CY3115/CY3110J
Verilog Compiler Verilog powerful, non-proprietary language that standard behavioral design entry simulation, supported major vendors tools. Verilog allows designers learn single language that useful facets design process. Verilog offers designers ability describe designs many different levels. highest level, designs entered description their behavior. This behavioral description tied specific target device. result, simulation done very early design verify correct functionality, which significantly speeds design process. Warp2's Verilog syntax also includes support intermediate level entry modes such state tables boolean entry. lowest level, designs described using gate-level (Register Transfer Language) descriptions. Warp2 gives designer flexibility intermix these entry modes. addition, Verilog allows design hierarchically, building entities terms other entities. This allows work either "top-down" (designing highest levels system interfaces first, then progressing greater greater detail) "bottom-up" (designing elementary building blocks system, then combining these build larger larger parts) with equal ease. Because Verilog IEEE standard, multiple vendors offer tools design entry simulation both high levels synthesis designs different silicon targets. device-independent behavioral design entry gives users freedom easily migrate high volume technologies. wide availability Verilog tools provides complete vendor independence well. Designers begin their project using Warp2 Cypress CPLDs convert high volume gate arrays using same Verilog behavioral description with industry-standard synthesis tools. Verilog language allows users define their functions. User-defined functions allow users extend capabilities language build reusable files tested routines. Verilog also provides control over timing events processes. Verilog constructs that identify processes either sequential, concurrent, combination both. This essential when describing interaction complex state machines. Verilog rich programming language. flexibility reflects nature modern digital systems allows designers create accurate models digital designs. Because verbose language easy learn compile hardware system. addition, models created Verilog readily transported other Environments. Warp2 supports IEEE 1364 Verilog including loops, reduction conditional operators, blocking non-blocking procedural assignments, well synthesis integers. part Warp2 description that specifies behavior structure design called module. module declares design's interface signals (i.e., defines what external signals design has, what their directions types are). module portion design file declaration what design presents outside world (the interface). each external signal, module specifies signal name, direction data type. addition, module declaration specifies name which entity referenced other modules. This section shows code segments from four sample design files. portion each example features module declaration. Behavioral Description module portion design file specifies function design. shown Figure multiple design-entry methods supported Warp2. behavioral description Verilog often includes well known constructs such If.Else, Case statements. Here code segment from simple state machine design (soda vending machine) that uses behavioral Verilog implement design: MODULE drink (nickel, dime, quarter, clock, returnDime, returnNickel, giveDrink); INPUT nickel, dime, quarter, clock; OUTPUT returnDime, returnNickel, giveDrink; PARAMETER zero five fifteen twenty twentyfive owedime REG[1:0] drinkStatus; ALWAYS@ (POSEDGE clock) BEGIN giveDrink returnDime returnNickel CASE(drinkStatus) zero: BEGIN (nickel) drinkStatus five; ELSE (dime) drinkStatus ten; ELSE (quarter) drinkStatus twentyfive; five: BEGIN (nickel) drinkStatus ten; ELSE (dime) drinkStatus fifteen; ELSE (quarter) BEGIN drinkStatus zero; giveDrink
Designing with Warp2
Design Entry Warp2 descriptions specify: behavior structure design, mapping signals design pins PLD/CPLD (optional)
CY3110/CY3115/CY3110J
Several states omitted this example. omitted states fifteen, twenty, twentyfive. owedime: BEGIN returnDime drinkStatus zero; default: BEGIN This makes sure that state machine resets itself somehow gets into undefined state. drinkStatus zero; ENDCASE ENDMODULE Verilog strongly typed language. simplicity readability following code increased CASEX. CASEX command accepts don't cares chooses branch depending value expression. MODULE sequence (clk, INPUT clk; INOUT WIRE temp; REG[3:0] count; ALWAYS@(POSEDGE clk) CASEX(count) 4'b00XX: BEGIN temp=1; count=count+1; 4'b01XX: BEGIN temp=0; count=count+1; 4'b100X: BEGIN temp=1; count=count+1; default: BEGIN temp=0; count=0; ENDCASE ASSIGN s=temp; ENDMODULE Boolean Equations second design-entry method available Warp2 Verilog users Boolean equations. Figure displays schematic simple one-bit half adder. following code describes this one-bit half adder implemented Warp2 with Boolean equations: MODULE half_adder(x, sum, carry); INPUT OUTPUT sum, carry; ASSIGN x^y; ASSIGN carry x&y; ENDMODULE
carry
Figure One-Bit Half Adder Structural Verilog (RTL) While design methodologies described thus high-level entry methods, structural Verilog provides method designing very level. structural descriptions (also called RTL), designer simply lists components that make design specifies components wired together. Figure displays schematic simple 3-bit shift register following code shows this design described Warp2 using structural Verilog. MODULE shifter3 (clk, q2); INPUT clk, OUTPUT WIRE q0_temp, q1_temp, q2_temp; d1(x,clk,q0_temp); d2(q0_temp,clk,q1_temp); d3(q1_temp,clk,q2_temp); ASSIGN q0_temp; ASSIGN q1_temp; ASSIGN q2_temp; ENDMODULE;
Figure Three-Bit Shift Register Circuit Design design-entry methods described mixed desired. Verilog ability combine both high- low-level entry methods single file. flexibility power Verilog allows users Warp2 describe designs using whatever method appropriate their particular design.
Finite State Machine Editor only)
Finite State Machine Editor, Active-HDLFSM, allows graphic design entry through graphical state diagrams. graphical state diagrams conjunction with data flow logic represent code.
CY3110/CY3115/CY3110J
Compilation
Once Verilog description design complete, compiled using Warp2. Although implementation with single command, compilation actually multistep process shown Figure first part compilation process same devices. input Verilog description synthesized logical representation design. Warp2 synthesis unique that input language (Verilog) supports device-independent design descriptions. Competing programmable logic compilers require very specific device-dependent information design description Warp2 synthesis based UltraGen technology. This technology allows Warp2 infer "modules" like adders, counters, comparators, etc., from behavioral descriptions. Warp2 then replaces that operator internally with architecture specific circuit based target device. This circuit "module" also pre-optimized either area speed, Warp2 uses appropriate implementation based user directives. second step compilation interactive process optimizing design fitting logic into targeted device. Logical optimization Warp2 accomplished using Espresso algorithms. optimized design automatically Warp2 fitter targeting CPLD. This fitter supports automatic manual placement assignments well automatic selection flip-flops. After optimization fitting, Warp2 creates JEDEC file specified CPLD.
System Requirements
equivalent (486-66MHz higher recommended) Mbytes Mbytes recommended) Mbytes Disk Space CD-ROM drive Two- three-button mouse Windows (including Japanese) Windows Workstations SPARC Solaris Mbytes Mbytes recommended) CD-ROM drive
Product Ordering Information
Product CY3110R50 CY3115R50 CY3110JR50 Code Description Warp2 Verilog development system Warp2 Verilog development system Solaris Workstations Warp2 Verilog Japanese development system
Simulation only)
Warp2 includes post-synthesis timing simulator called Active-HDLSim. Active-HDL features graphical waveform simulator that used simulate PLD/CPLD designs generated Warp2. simulator provides timing simulation PLDs/CPLDs features interactive waveform editing viewing. simulator also provides ability probe internal nodes automatically generate clocks pulses. Warp2 will also output standard Verilog VHDL timing models. These models used with many third-party simulators perform functional timing verifications synthesized design.
Warp2 Verilog includes: CD-ROM with Warp2, Aldec Active-HDL FSM, on-line documentation (Getting Started Manual, User's Guide, Reference Manual) Registration Card Release Notes Document 38-00734
Programming
result Warp2 compilation JEDEC file that implements input design targeted device. Using this file, Cypress devices programmed Cypress's Impulse3programmer qualified third-party programmer. Cypress's FLASH370i Ultra37000 In-System Reprogrammable(ISRTM) devices also programmed board with programmer. Warp2 outputs JEDEC programming files. These files converted files Cypress's software. Once format, device programed using player with Cypress's software cable. Figure Warp2 Graphic User Interface Warp2 Warp3 registered trademarks Cypress Semiconductor Corporation. UltraGen, Ultra37000, MAX340, Impulse3, FLASH370i, ISR, In-System Reprogrammable trademarks Cypress Semiconductor Corporation. Solaris trademark Microsystems Corporation. Active-HDL trademark Aldec Incorporated.
Cypress Semiconductor Corporation, 1998. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

CY3110/CY3115/CY3110J Warp2® Verilog Compiler CPLDs Verilog

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