3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS BUS-HOLD
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IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP, 0.40mm pitch TVSOP packages Extended commercial range 40°C 85°C 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Drive Features ALVCHR16601: Balanced Output Drivers: ±12mA switching noise
IDT74ALVCHR16601
CMOS technology. transceiver combines D-type latches D-type flip-flops allow data flow transparent, latched, clocked modes. Data flow each direction controlled output-enable (OEAB OEBA), latch-enable (LEAB LEBA), clock (CLKAB CLKBA) inputs. clock controlled clock-enable (CLKENAB CLKENBA) inputs. A-to-B data flow, device operates transparent mode when LEAB high. When LEAB low, data latched CLKAB held high logic level. LEAB low, data stored latch/flip-flop low-to-high transition CLKAB. Output enable OEAB active low. When OEAB low, outputs active. When OEAB high, outputs high-impedance state. Data flow similar that uses OEBA, LEBA, CLKBA CLKENBA. ALVCHR16601 series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been designed drive 12mA designated threshold levels. ALVCHR16601 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
DESCRIPTION:
This 18-bit universal transceiver built using advanced dual metal
Functional Block Diagram
OEAB
CLKENAB
CLKAB LEAB LEBA CLKBA CLKENBA OEBA
OTHER CHANNELS
1999 Integrated Device Technology, Inc.
JUNE 1999
DSC-4491/1
IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
CONFIGURATION
OEAB LEAB OEBA LEBA CLKENAB CLKAB CLKBA CLKENBA
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2)
Unit
NEW16link
VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Max. ±100
SO56-1 SO56-2 SO56-3
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NEW16link
NOTE: applicable device type.
FUNCTION TABLE(1,2)
CLKENAB OEAB Inputs LEAB CLKAB Outputs
SSOP/ TSSOP/TVSOP VIEW
NOTES: A-to-B data flow shown. B-to-A data flow similar uses OEBA, LEBA, CLKBA CLKENBA. HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established.
IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
DESCRIPTION
Names OEAB OEBA LEAB LEBA CLKAB CLKBA CLKENAB CLKENBA Description A-to-B Output Enable Inputs (Active LOW) B-to-A Output Enable Inputs (Active LOW) A-to-B Latch Enable Inputs B-to-A Latch Enable Inputs A-to-B Clock Inputs B-to-A Clock Inputs A-to-B Data Inputs B-to-A 3-State Outputs B-to-A Data Inputs A-to-B 3-State Outputs A-to-B Clock Enable Inputs (Active LOW) B-to-A Clock Enable Inputs (Active LOW)
NOTE: These pins have "Bus-Hold." other pins standard inputs, outputs, I/Os.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation 2.3V, 18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
NEW16link
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 2.7V 3.0V Output Voltage 2.3V 3.6V 2.3V 2.7V 3.0V 12mA 0.1mA 12mA Min. Max. 0.55 0.55
NEW16link
Unit
2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
SWITCHING CHARACTERISTICS
2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Propagation Delay Propagation Delay LEAB LEBA Propagation Delay CLKAB CLKBA Output Enable Time OEAB OEBA Output Disable Time OEAB OEBA Setup Time, data before Setup Time, data before HIGH Setup Time, data before Setup Time, CLKEN before Hold Time, data after Hold Time, data after HIGH Hold Time, data after Hold Time, CLKEN after Pulse Width, HIGH Pulse Width, HIGH Output Skew(2) Parameter Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
NEW16link
PHAS INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT ITCH NORM ALLY CLOSE tPZH OUTPUT ITCH NORM ALLY OPEN HIGH LOAD tPLZ DISABLE LOAD
Link
LOAD Open
D.U.T.
Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
NEW16link
Open
OUTPUT SKEW
INPUT tPLH1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT tPLH2
PLH2
Link
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCHR16601 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER
ORDERING INFORMATION
ALVC Device Type Package Range Bus-Hold
Shrink Small Outline Package (SO56-1) Thin Shrink Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 18-Bit Universal Transceiver with 3-State Outputs Double-Density with Resistors, ±12mA Bus-Hold -40°C +85°C
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