This document describes interface TTSI4K32T, TTSI2K32T, TTSI1K16T time

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This document describes interface TTSI4K32T, TTSI2K32T, TTSI1K16T time

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Interfacing TTSI4K32T, TTSI2K32T, TTSI1K16T Microprocessor
This document describes interface TTSI4K32T, TTSI2K32T, TTSI1K16T time-slot interchanger device asynchronous microprocessor, such Motorola MC68360 MC68302 synchronous microprocessor such Motorola MPC860 power QUICC. readability, this family three time-slot interchangers will referred TSI.
Asynchronous Motorola Microprocessor Interface Connections
SIZ[1-0] DSACK1 A[14-0] (TTSI4K32T, TTSI2K32T, TTSI1K16T) PCLK D[7-0] DSACK0 A[31-15] A[14-0] D[23-0] D[31-24] IRQX
5-7428(F)r.1
ASYNCHRONOUS MOTOROLA MICROPROCESOR (MC68360 MC68302)
Figure Glueless Asynchronous Motorola Microprocessor Interface microprocessor interface signals connected directly asynchronous Motorola microprocessor, Figure asynchronous mode selected tying low; consequently, PCLK input used thus should tied high left floating. least significant bits address used access registers memories. Note that D[7-0] connected D[31-24] MC68302/360.
Interfacing TTSI4K32T, TTSI2K32T, TTSI1K16T Microprocessor
Asynchronous Motorola Microprocessor Interface Connections (continued)
DSACK1 input microprocessor pulled high DSACK0 connected TSI's output, indicate byte transfer, whenever microprocessor accesses (reads writes) TSI. output driven high when detects access (i.e., inputs sensed low) within sensing access, asserts indicate completion access. Driving high will then cause high. However, driving high causes tristate. aligned, then will tristated before pulled high. then pull-up resistor pull before start next microprocessor access, which access access another device microprocessors address data buses. Figure such access.
ACCESS NEXT ACCESS
UNAMBIGUOUS LOGIC REACHED TIME NEXT MICROPROCESSOR ACCESS STARTS
5-7429(F)r.1
Figure Typical Access Asynchronous Microprocessor with Aligned
Interfacing Fast Asynchronous Microprocessor
system where fast microprocessor being used (typically MHz), time takes pull-up resistor pull unambiguous logic (~2.1 same order between consecutive microprocessor accesses (typically microprocessor clock cycle). next access start before been pulled high enough microprocessor sense logic Hence, next access terminate prematurely, microprocessor hang detected early microprocessor access. Figure
ACCESS
NEXT ACCESS TERMINATES PREMATURELY SINCE DETECTED MICROPROCESSOR
UNAMBIGUOUS LOGIC REACHED TIME NEXT MICROPROCESSOR ACCESS STARTS
5-7430(F)r.2
Figure Access Fast Asynchronous Microprocessor with Aligned
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Interfacing TTSI4K32T, TTSI2K32T, TTSI1K16T Microprocessor
Interfacing Fast Asynchronous Microprocessor (continued)
There several ways avoid this problem.
stronger (lower resistance) pull-up resistor thus decrease resistance capacitance (RC) delay rise time However, noise margin logic compromised strong pull competes with buffer device which tries pull low. Table trade-off between value pull-up resistor voltage logic (VOL) that results signal. from should wire-ORed with DTACK from other devices board, combined using gate. This should reduce delay since capacitance trace from gate will probably smaller than bused signal that goes over board. Delay going TSI, compared This already occurring external address decode being performed generate TSI. This delay needs minimum (timing parameter Figure Asynchronous Read Cycle Timing Using Handshake Figure Asynchronous Write Cycle Timing Using Handshake data sheets (TTSI2K32T 2048-Channel, 32-Highway Time-Slot Interchanger (DS99-045T1E1), TTSI1K16T 1024-Channel, 16-Highway Time-Slot Interchanger (DS99-177PDH), TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger (DS99-178PDH)). Figure below. Access using preprogrammed number wait-states microprocessor, rather than relying handshake signal. number wait states that need used calculated from fact that once access detected (i.e., inputs sensed low) will complete access drive within
Table Signal, Different Values Pull-Up Resistor Resistance (mV) (mV) 5.25 1.0k 1.5k 2.0k 2.2k 3.3k 4.7k
ACCESS
NEXT ACCESS
5-7431(F)
Figure Access Microprocessor with Delayed
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Interfacing TTSI4K32T, TTSI2K32T, TTSI1K16T Microprocessor
Synchronous Motorola Microprocessor Interface Connections
(TTSI4K32T, TTSI2K32T, TTSI1K16T) PCLK A[14-0] D[7-0] RD/WR CLKOUT A[0-15] A[16-31] D[8-31] D[0-7] IRQX
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SYNCHRONOUS MOTOROLA MICROPROCESOR (MPC860 POWER QUICC BIG-ENDIAN MODE)
Figure Glueless Asynchronous Motorola Microprocessor Interface Note that MPC860 microprocessor, least significant address A31. Hence, A[16-31] MPC860 should connected A[14-0], respectively, TSI. always carries most significant transfer data MPC860. least significant data MPC860 32-bit acceses, 16-bit acceses, byte accesses. Since 8-bit data bus, MPC860 should connected microprocessor TSI. This connection data also assumes that big-endian format MPC860 been selected, which default.
Motorola registered trademark Motorola, Inc.
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Union Boulevard, Room 30L-15P-BA, Allentown, 18109-3286 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, (44) 1344
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application.
Copyright 2001 Agere Systems Inc. Rights Reserved
April 1999 AP99-013T1E1

This document describes interface TTSI4K32T, TTSI2K32T, TTSI1K16T time

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