3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER, DUAL 3-STATE OU

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3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER, DUAL 3-STATE OU

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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP, 0.40mm pitch TVSOP packages Extended commercial range 40°C 85°C 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Drive Features ALVCH16903: High Output Drivers: ±24mA Suitable heavy loads
IDT74ALVCH16903
DESCRIPTION:
This 12-bit universal driver built using advanced dual metal CMOS technology. This device dual outputs operate buffer edge-triggered register. both modes, parity checked APAR, which arrives cycle after data which applies. YERR output, which produced cycle after APAR, open drain. MODE selects data paths. When MODE low, device operates edge-triggered register. positive transition clock (CLK) input when clock-enable (CLKEN) input low, data setup inputs stored internal registers. positive transition when CLKEN high, only data setup 9A-12A inputs stored their internal registers. When MODE high, device operates buffer data inputs passes directly outputs. 11A/YERREN serves dual purpose; acts normal data also enables YERR data clocked into YERR output register. When used single device, parity output enable (PAROE) must tied high; when parity input/output (PARI/O) low, even parity selected when PARI/O high, parity selected. When used pairs PAROE low, parity output PARI/O cascading second ALVCH16903. When used pairs PAROE high, PARI/O accepts partial parity from first ALVCH16903.
Unit
NEW16link
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Max. ±100
buffered output-enable (OE) input used place outputs YERR either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. ALVCH16903 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH16903 "bus-hold" which retains inputs' last state whenever input goes high-impedance. This prevents floating inputs eliminates need pull-up/down resistors.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
1999 Integrated Device Technology, Inc.
APRIL 1999
DSC-4911/-
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
FUNCTIONAL BLOCK DIAGRAM
(1A-11A/YERREN, PAR) 1A-12A, (1A-8A) (11A/YERREN) APAR Flip Flop (1A-10A) Parity Check APAR (1A-12A) 1Y2-12Y2 1Y1-12Y1
CLKEN (9A-12A, APAR)
Flip Flop
PARI/O
FUNCTION TABLES(1) FUNCTION
Inputs MODE CLKEN 1YX-18YX Outputs 9YX-12YX
PAROE
PARITY FUNCTION TABLE
Inputs 11A/YERREN
Output INPUTS 1A-10A= APAR YERR
PARI/O
NOTES: HIGH Voltage Level Voltage Level Level before indicated steady-state input conditions were established Don't Care High-Impedance LOW-to-HIGH Transition When used single device, PAROE must tied high Valid after appropriate number clock pulses have internal register
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
PARI/O FUNCTION TABLE(1)
Inputs PAROE INPUTS 1A-10A 8,10 APAR Output PARI/O
CONFIGURATION
11A/YERREN 11Y1 11Y2 12Y1 12Y2 APAR YERR MODE PARI/O CLKEN
NOTE: This table applies first device cascaded pair ALVCH16903 devices.
DESCRIPTION
Names 1A-12A 1Y1-12Y2 CLKEN MODE YERREN PAROE PARI/O YERR APAR Description Data Inputs 3-State Data Outputs Clock Input Clock Enable Input (active low) Select Error Signal Output Enable (active low) Parity Output Enable (active low) Parity Input/Output Error Signal (open drain) Output Enable Input (active low) Parity Input
SO56-1 SO56-2 SO56-3
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
10Y1 10Y2 PAROE
NEW16link
NOTE: applicable device type.
SSOP/ TSSOP/TVSOP VIEW
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: +85° Symbol IOZH IOZL IOZ(2) ICCL ICCH ICCZ Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation Control Inputs Data Inputs YERR Output Data Outputs PARI/O 3.3V 3.3V Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) YERR Output 3.6V 3.6V 2.3V, 18mA 3.3V 3.6V input 0.6V, other inputs 3.3V Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
NOTES: Typical values 3.3V, +25°C ambient. ports, parameter includes input leakage current.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
OUTPUT DRIVE CHARACTERISTICS PORTS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 2.3V High-Level Output Current 2.7V 2.3V 2.7V Low-Level Output Current PARI/O Port YERR Output PARI/O Port Port 12mA 24mA Port Max. 0.55 Unit
2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V
OUTPUT DRIVE CHARACTERISTICS YERR PARI/O
Symbol Parameter PARI/O PARI/O YERR Output only Test Conditions(1) 12mA
Min.
Max. 0.55
Unit
12mA 24mA
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
OPERATING CHARACTERISTICS BUFFER MODE, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz 17.5 Typical 57.5 3.3V 0.3V Typical Unit
OPERATING CHARACTERISTICS REGISTER MODE, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz 16.5 Typical 3.3V 0.3V Typical 87.5 Unit
SIMULTANEOUS SWITCHING CHARACTERISTICS
Parameter tPLH tPHL
NOTE: outputs switching.
From (Input)
(Output)
2.5V 0.2V Min. Max.
2.7V Min. Max.
3.3V 0.3V Min. Max. Unit
Register mode
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
SWITCHING CHARACTERISTICS
2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ Parameter Propagation Delay, Buffer Mode Propagation Delay, Both Modes YERR Propagation Delay, Both Modes PARI/O Propagation Delay, Both Modes PARI/O Propagation Delay, Both Modes Mode Propagation Delay, Register Mode Propagation Delay, Both Modes YERR Propagation Delay, Both Modes YERR Output Enable Time, Both Modes Output Enable Time, Both Modes PAROE PARI/O Output Disable Time, Both Modes Output Disable Time, Both Modes PAROE PARI/O Set-up Time, Register Mode 1A-12A before Set-up Time, Buffer Mode before Set-up Time, Register Mode APAR before Set-up Time, Buffer Mode APAR before Set-up Time, Both Modes PARI/O before Set-up Time, Buffer Mode 11A/YERREN before Set-up Time, Register Mode CLKEN before Hold Time, Register Mode 1A-12A after Hold Time, Buffer Mode 1A-10A after Hold Time, Register Mode APAR after Hold Time, Buffer Mode APAR after Hold Time, Register Mode PARI/O after Min. 0.25 0.25 0.25 Max. 2.7V Min. 0.25 0.25 0.25 0.25 Max. 3.3V 0.3V Min. 1.45 0.55 0.25 0.25 Max. Unit
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
SWITCHING CHARACTERISTICS (CONTINUED)
2.5V 0.2V Symbol tSK(O) Parameter Hold Time, Buffer Mode PARI/O after Hold Time, Buffer Mode 11A/YERREN after Hold Time, Register Mode CLKEN after Pulse Width, Output Skew Min. 0.25 0.25 0.25 Max. 2.7V Min. 0.25 0.25 Max. 3.3V 0.3V Min. Max. Unit
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
TEST CIRCUITS WAVEFORMS: TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
NEW16link ALVC Link
PROPAGATION DELAY
PHASE INPUT TRANSITION tPLH TPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL TPUT ITCH NORMALLY CLOSED tPZH TPUT ITCH NORMALLY OPEN HIGH LOAD/2 tPHZ tPLZ DISABLE LOAD/2
LOAD Open
D.U.T.
DEFINITIONS: Load capacitance: includes probe capacitance. ALVC Link Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
ALVC Link NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SWITCH POSITION:
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT
ALVC Link
Open
NEW16link
ASYNCHRON CONTROL SYNC HRON CONTROL
tREM
OUTPUT SKEW
INPUT TPUT TPUT tPLH2 tPHL2
ALVC Link
tPLH1
tPHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH -LOW -HIGH PULSE
ALVC Link
tPLH2 tPLH1 tPHL2 tPHL1
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
TEST CIRCUITS WAVEFORMS: TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD 2.5V± 0.2V
Unit
tPLH OPPOSITE PHASE INPUT TRANSITION tPHL SAME PHASE INPUT TRANSITION tPLH OUTPUT tPHL
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE DISABLE LOAD
LOAD Open CONTROL INPUT tPZL OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY HIGH LOAD tPHZ tPLZ
D.U.T.
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTE: Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES SWITCH POSITION:
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL
Open
NEW16link
SYNCHRONOUS CONTROL
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
PARAMETER MEASUREMENT INFORMATION 2.7V 3.3V 0.3V
From Output Under Test (see Note Open
TEST tPLZ/tPZL tPHZ/tPZH YERR
Open
LOAD CIRCUIT
INPUT 2.7V 1.5V
tPHL (see Note tPLH (see Note
DATA INPUT 1.5V
2.7V 1.5V INPUT 1.5V
2.7V 1.5V
VOLTAGE WAVEFORMS SETUP HOLD TIMES
VOLTAGE WAVEFORMS PULSE DURATION
OUTPUT CONTROL (low-level enabling) 2.7V Input Output 1.5V 1.5V 1.5V 1.5V OUTPUT AVEFORM (see Note OUTPUT AVEFORM (see Note tPZL
1.5V 2.7V 1.5V 1.5V 1.5V 0.3V tPHZ -0.3V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. tPHL measured 1.5V. tPLH measured +0.3V.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
LOAD CIRCUIT VOLTAGE WAVEFORMS 2.7V 3.3V 0.3V
2.7V 1.5V INPUT tPLH OUTPUT 1.5V 1.5V 1.5V
PARI/O LOAD CIRCUIT
From Output Under Test Test PARI/O Point (see Note
PARI/O second ALVCH16903 (see Note
NOTE: includes probe capacitance.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
PARAMETER MEASUREMENT INFORMATION 2.5V 0.2V
From Output Under Test (see Note Open
TEST tPLZ/tPZL tPHZ/tPZH YERR tPHL (see Note tPLH (see Note
Open
LOAD CIRCUIT
TIMING
CC/2 CC/2 CC/2 CC/2 CC/2
DATA
VOLTAGE WAVEFORMS SETUP HOLD TIMES
VOLTAGE WAVEFORMS PULSE DURATION
CONTROL (low-level enabling)
Input Output tPHL
OUTPUT AVEFORM 2xVcc (see Note OUTPUT AVEFORM (see Note
tPZL
tPLZ tPZH 0.15V tPHZ -0.15V
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. tPHL measured VCC/2. tPLH measured 0.15V.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
PARAMETER MEASUREMENT INFORMATION 2.5V 0.2V
From Output Under Test PARI/O
Test Point
(see Note
PARI/O second ALVCH16903 (see Note
LOAD CIRCUIT
Input utput
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
NOTES: includes probe capacitance. input pulses supplied generators having following characteristics: MHz, 2ns. tPLH tPHL same tpd.
From utput Under Test Test Point (see Note utput Input
LOAD CIRCUIT
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
NOTES: includes probe capacitance. input pulses supplied generators having following characteristics: MHz, 2ns.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER W/PARITY CHECKER
ORDERING INFORMATION
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3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER, DUAL 3-STATE OU

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