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LC2MOS 12-Bit, kHz/1 MHz, Sampling AD7886 VIN1 VIN2 +5REF 6.3k VR


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FEATURES kHz/1 Throughput Rate s/750 Conversion Time 12-Bit Missed Codes Over Temperature Input Frequency Power-250 Fast Access Time-57 APPLICATIONS Digital Signal Processing Speech Recognition Synthesis Spectrum Analysis Servo Control
LC2MOS 12-Bit, kHz/1 MHz, Sampling AD7886
VIN1 VIN2 +5REF 6.3k VREF 4096 RESISTOR AGND 3.5k CLOCK OSCILLATOR TIMER CONTROL TIMER BUSY CONVST
4-BIT LATCH COMPARATORS 4-BIT FLASH LOGIC DB11 4-BIT LATCH THREE STATE OUTPUTS
4-BIT LATCH SEGMENT SELECT
AD7886
DGND
GENERAL DESCRIPTION
AD7886 12-bit with sample-and-hold amplifier offering high speed performance combined with power dissipation. AD7886 triple pass flash that uses comparators 4-bit flash technique achieve 12-bit accuracy µs/750 conversion time. on-chip clock oscillator provides appropriate timing each three conversion stages, eliminating need external clocks. Acquisition time sample-and-hold amplifier gives resulting throughput rate kHz/1 MHz.* AD7886 operates from power supplies. Pin-strappable inputs offer choice three analog input ranges: addition traditional accuracy specifications such linearity, offset full-scale errors, AD7886 also specified dynamic performance parameters, including harmonic distortion signal-to-noise ratio. AD7886 high speed digital interface with three-state data outputs. Conversion control provided CONVST input. Data access controlled inputs, standard microprocessor signals. data access time less than means that AD7886 interface directly most modern microprocessors, including processors.
*Contact your local salesperson further information version.
AD7886 fabricated Analog Devices' Linear Compatible CMOS process, mixed technology process that combines precision bipolar circuits with power CMOS logic. AD7886 available both 28-pin 28-pin leaded chip carrier.
PRODUCT HIGHLIGHTS
Fast 1.33 µs/1 Throughput Time. Fast throughput time makes AD7886 suitable wide range data acquisition applications. Dynamic Specifications Users. AD7886 specified parameters, including signal-to-noise ratio, harmonic distortion intermodulation distortion. digital timing parameters also tested guaranteed over full operating temperature range. Fast Microprocessor Interface. Standard control signals, fast access times make AD7886 easy interface microprocessors. Power. LC2MOS fabrication process gives power dissipation
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
AD7886-SPECIFICATIONS otherwise noted. VSpecifications5%, A6ND DGND =version.) -3.5 connected shown Figure Specifications unless apply
Parameter DYNAMIC PERFORMANCE2 Signal-to-Noise Ratio3 (SNR) Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms ACCURACY Resolution Integral Linearity TMIN TMAX Minimum Resolution Which Missing Codes Guaranteed Unipolar Offset Error +25°C TMIN TMAX Bipolar Offset Error +25°C TMIN TMAX Unipolar Gain Error +25°C TMIN TMAX Bipolar Gain Error +25°C TMIN TMAX ANALOG INPUT Unipolar Input Current Bipolar Input Current REFERENCE INPUT VREF Input Reference Current Resistance Resistance R2/R1 Ratio
Version1
Versions1
Version1
Units
Test Conditions/Comments
Sine Wave, fSAMPLE Sine Wave, fSAMPLE Sine Wave, fSAMPLE kHz, kHz, fSAMPLE
0.75 -3.5
Bits Bits
0.75 -3.5
Input Range: Input Range: Input Range: Input Range:
0.75 -3.5
Input Ranges: Input Range: Specified Performance 0.1%
Volts
POWER SUPPLY REJECTION
Only, Change) Only, Change) LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, CIN4 LOGIC OUTPUTS DB11-DB0, BUSY Output High Voltage, Output Voltage, DB11-DB0 Floating-State Leakage Current Floating-State Output Capacitance4 POWER REQUIREMENTS Power Dissipation +4.75 +5.25 -4.75 -5.25
ISOURCE ISINK
Specified Performance Specified Performance Typically CONVST Typically CONVST CONVST
NOTES Temperature ranges follows: Versions: +70°C; Version: -40°C +85°C; Version: -55°C 125°C. Applies three input ranges, pk-to-pk calculation includes distortion noise components. Sample tested +25°C ensure compliance. Specifications subject change without notice.
REV.
AD7886 TIMING CHARACTERISTICS1
Parameter tCONV
AGND DGND
Limit Limit TMIN, TMAX TMIN, TMAX Versions) Version) 1.333 1000 1.333 1000
Limit TMIN, TMAX Version) 1.333 1000
Units
Conditions/Comments CONVST Pulse Width Setup Time Hold Time Pulse Width CONVST BUSY Propagation Delay, Data Access Time After Relinquish Time After Data Setup Time Prior BUSY, Data Setup Time Prior BUSY, Relinquish Time After CONVST High CONVST BUSY High BUSY High CONVST Low, Acquisition Time Sampling Interval Conversion Time
NOTES Timing specifications bold print 100% production tested. other times sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level measured with load circuit Figure defined time required output cross derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging load capacitor, This means that times, quoted timing characteristics true relinquish times part such independent external loading capacitances. Specifications subject change without notice.
OUTPUT
+2.1V
VIN1, VIN2, SUM, +5REF AGND VREF AGND -0.3 +0.3 Digital Inputs DGND CONVST -0.3 +0.3 Digital Outputs DGND DB11, BUSY -0.3 +0.3 Operating Temperature Range Commercial Versions) +70°C Industrial Version) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature Range .-65°C 150°C Lead Temperature (Soldering, secs) +300°C Power Dissipation (Any Package) +75°C 1000 Derates above +75°C mW/°C
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. open circuited with AGND applied, will pulled positive, exceeding Absolute Maximum Ratings. this possibility exists, Schottky diode from DGND (cathode GND) ensures that
Figure Load Circuit Access Relinquish Time
ABSOLUTE MAXIMUM RATINGS
(TA= +25°C unless otherwise noted) AGND -0.3 AGND +0.3 AGND DGND -0.3 +0.3
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7886 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7886
ORDERING GUIDE
Model1, AD7886JD AD7886KD AD7886JP AD7886KP AD7886BD AD7886TD
Temperature Range +70°C +70°C +70°C +70°C -40°C +85°C -55°C +125°C
(dBs)
Integral Nonlinearity (LSBs)
Package Option3 D-28 D-28 P-28A2 P-28A2 D-28 D-28
NOTES 1Contact your sales office availability AD7886BD, AD7886TD version. Analog Devices reserves right ship J-Leaded Ceramic Chip Carrier (JLCCC) lieu PLCC packages. Ceramic DIP; Plastic Leaded Chip Carrier.
FUNCTION DESCRIPTION
Number
Mnemonic
Description Positive Power Supply, Both pins must tied together. Negative Power Supply, Both pins must tied together. Analog Ground. Both AGND pins must tied together. Digital Ground.
Power Supply AGND DGND
Analog Reference Inputs Analog Inputs, VIN1 VIN2. part strapped three analog input ranges; Range +5REF VREF Strap Connect VIN2 VIN1 Connect VIN2 Connect VIN2 Signal Input VIN1 VIN2 VIN1 VIN1
Reference input. This input used conjunction with VREF inputs scale external reference -3.5 required reference part (see Figure Summing Point. This input used conjunction with +5REF VREF inputs scale external reference -3.5 required reference part (see Figure Voltage Reference Input. AD7886 specified with VREF -3.5 Three-state data outputs. These outputs controlled DB11 Most Significant (MSB). BUSY Output indicates converter status. BUSY during conversion. Chip Select Input. device selected when this input low. Read Input. This active signal, conjunction with used enable output data three-state drivers. Conversion Start Input. This input used start conversion.
Interface Control 1-4, DB7-DB4 6-9, DB3-DB0 25-28 DB11-DB8 BUSY CONVST
REV.
AD7886
CONFIGURATIONS
PLCC
DB10 DB11
DGND DB11
DB10
DGND
AD7886
VIEW (Not Scale)
AGND VREF +5REF VIN2 VIN1 AGND
AD7886
VIEW (Not Scale)
AGND VREF +5REF
BUSY
BUSY CONVST
CONVST
AGND
VIN1
VIN2
TERMINOLOGY
Unipolar Offset Error
ideal first code transition should occur when analog input above AGND. deviation actual transition from that point termed offset error.
Bipolar Zero Error
result. bits data then stored internally threestate output latch.
REFERENCE INPUT
ideal midscale transition (i.e., 0111 1111 1111 1000 0000 0000) range should occur when analog input zero volts. Bipolar zero error deviation actual transition from that point.
Gain Error
unipolar mode, gain error measured with respect first last code transition points. ideal difference between these points FS-2 LSBs. bipolar applications, gain error measured from midscale transition both first last code transitions. ideal difference this case FS/2-1 LSB. gain error defined deviation between ideal difference, given above, measured difference. bipolar case, there gain errors; figure specification page represents worst case. Ideal depends +5REF input; input, ideal +5REF ranges, ideal 5REF.
CONVERTER DETAILS
AD7886 operates from reference, which must provided VREF input. on-chip resistors with external amplifier used deriving from standard references. Figure shows example with AD586 which high performance voltage reference exhibiting excellent stability performance, ppm/°C max. external amplifier serves second function force/sensing VREF input. Force/sensing minimizes error contributions from
+VIN VOUT +5REF 6.3k VREF
AD586
AD7886*
AD707
-3.5V
AD7886 triple-pass flash that uses comparators 4-bit flash technique perform 12-bit conversion procedure. Each 4096 quantization levels realized internally with precision resistor DAC. fifteen comparators first compare analog input voltage VREF/16 voltages resistor array. This determines four most significant bits selects voltage segments. comparators then switched subvoltages that segment determine next four bits select voltage segments. further switching comparators another subvoltages produces complete 12-bit conversion REV.
10µF
AGND 0.1µF
*ADDITIONAL PINS OMITTED CLARITY
Figure Typical Reference Circuitry
AD7886
this amplifier typically which much greater than Nyquist limit ADC; result, used undersampling applications. track-and-hold amplifier acquires input signal 12-bit accuracy less than overall throughput time equal conversion time plus track/ hold amplifier acquisition time, which 1.333 AD7886.
VIN1
VIN2**
AGND
operation track/hold amplifier essentially transparent user. track-to-hold transition occurs start conversion falling edge CONVST. conversion procedure does start until rising edge CONVST. width CONVST pulse time determines track-to hold settling time. track/hold reverts back track mode conversion when BUSY returned high.
ANALOG INPUT RANGE 3.5k
+VIN VOUT
AD7886*
5REF
AD586
AD707
3.5V VREF
VIN1 VIN2
10µF 0.1µF
COMPARATORS
ANALOG INPUT RANGE 3.5k
*ADDITIONAL PINS OMITTED CLARITY RANGE: CONNECT VIN2 VIN1 RANGE: CONNECT VIN2 AGND
Figure Unipolar Operation
OUTPUT CODE
VIN1 VIN2
COMPARATORS
11.111 11.110
ANALOG INPUT RANGE 3.5k
11.101 11.100
VIN1 VIN2
00.011
1LSB
4096
COMPARATORS
00.010 00.001
Figure Analog Input Range Configurations
00.000
ANALOG INPUT RANGES
AD7886 three user selectable analog input ranges: Figure shows configure analog inputs (VIN1 VIN2) these ranges.
UNIPOLAR OPERATION
VIN, INPUT VOLTAGE (LSBS) 1LSB
Figure Ideal Input/Output Transfer Characteristic Unipolar Operation
Figure shows typical unipolar circuit AD7886. ideal input/output characteristic shown Figure designed code transitions occur integer multiples LSB. output code natural binary with FS/4096. either depending analog inputs configured.
REV.
AD7886
OFFSET GAIN ADJUSTMENT BIPOLAR OPERATION
most digital signal processing (DSP) applications, offset full-scale errors have little effect system performance. Offset error usually eliminated analog domain coupling. Full-scale errors cause problems long input signal within full dynamic range ADC. applications requiring that input signal range match full analog input dynamic range ADC, offset fullscale errors must adjusted zero.
UNIPOLAR OFFSET GAIN ERROR ADJUSTMENT
Bipolar operation achieved providing span VIN1 input while offsetting VIN2 input typical circuit shown Figure output code offset binary. ideal input/output transfer characteristic shown Figure size (10/4096) 2.44
absolute accuracy application requirement, offset gain adjusted zero. Offset error must adjusted before gain error. Zero offset achieved adjusting offset driving analog input (i.e., Figure zero offset error, apply voltage adjust offset until output code flickers between 0000 0000 0000 0000 0000 0001. Range: 1.22 Range: 2.44 zero gain, error apply analog input voltage equal FS-1 (last code transition) adjust until output code flickers between 1111 1111 1110 1111 1111 1111. Range: FS-1 4.99878 Range: FS-1 9.99756
+VIN VOUT VIN1 VIN2 AGND 5REF
AD586
AD707
3.5V
AD7886*
VREF
10µF
0.1µF
AD845
VIN1
VIN2**
OUTPUT CODE
*ADDITIONAL PINS OMITTED CLARITY
Figure Bipolar Operation
AGND +VIN VOUT 5REF
11.111 11.110 11.101 10.010 10.001 +1LSB
AD586
AD707
3.5V
-1LSB +1LSB 1LSB 1LSB 4096
10.000 01.111 01.110
AD7886*
10µF 0.1µF
01.101 00.001 00.000
*ADDITIONAL PINS OMITTED CLARITY RANGE: CONNECT VIN2 VIN1 RANGE: CONNECT VIN2 AGND
VIN, INPUT VOLTAGE LSBs
Figure Unipolar Operation with Gain Error Adjust
Figure Ideal Input/Output Characteristics Bipolar Operation
REV.
AD7886
BIPOLAR OFFSET GAIN ADJUSTMENT
applications where absolute accuracy important, offset gain error adjusted zero. Offset adjusted trimming voltage VIN1 VIN2 input when analog input zero volts. This achieved adjusting offset external amplifier used drive either these inputs (see Figure trim procedure follows: Apply zero volts adjust offset until output code flickers between 0111 1111 1111 1000 0000 0000. Gain error adjusted either first code transition (ADC negative full scale) last code transition (ADC positive full scale). Adjusting reference, Figure will trim positive gain error only. trim procedure follows: Apply voltage 4.99756 (FS/2-1 LSB) adjust until output code flickers between 1111 1111 1110 1111 11111111. first code transition needs adjusting, gain trim must included analog signal path. trim procedure will then consist applying analog signal -4.99756 (-FS/2+1 LSB) adjusting trim until output code flickers between 0000 0000 0000 0000 0000 0001.
Data read operations controlled inputs. These digital inputs, when low, enable AD7886's threestate output latches. Note, these latches cannot enabled during conversion. applications where tied permanently low, Figure data will into three-state condition start conversion return active state when conversion complete. Tying permanently useful when external latches used store conversion results. data becomes active before BUSY returns high conversion, that BUSY used clocking signal external latches. typical application would have timer connected CONVST input precise sampling intervals. BUSY would connected interrupt microprocessor that would asserted every conversion. microprocessor would then assert inputs read data from ADC. applications where both data reading conversion control need managed microprocessor, CONVST pulse decoded from address bus. decoding possibility that write instruction address starts conversion, read instruction reads conversion result.
TRACK-TO-HOLD TRANSITION
AD845
VIN1 VIN2
CONVST
CONVERSION START HOLD TRACK TRANSITION
AGND +VIN VOUT 5REF
CONV
DATA VALID
AD586
BUSY
AD707 3.5V VREF
DATA HIGH IMPEDANCE
AD7886*
10µF 0.1µF
Figure Conversion Start Data Read Timing Diagram
TRACK-TO-HOLD TRANSITION
*ADDITIONAL PINS OMITTED CLARITY
Figure Bipolar Operation with Gain Error Adjust
CONVST
CONVERSION START
TIMING CONTROL
Conversion start controlled CONVST input (see Figures 11). high going edge CONVST input puts track/hold amplifier into hold mode. conversion procedure does begin until rising CONVST pulse edge occurs. width CONVST pulse time determines track-to-hold settling time. BUSY output, which indicates status ADC, goes while conversion progress. conversion BUSY returns high, indicating that data available AD7886's output latches. track/hold amplifier returns track mode conversion remains there until next CONVST pulse. Conversion starts must attempted while conversion progress this will cause erroneous results.
BUSY
CONV
HOLD TRACK TRANSITION
DATA VALID
DATA
HIGH IMPEDANCE
Figure Conversion Start Data Read Timing Diagram,
REV.
AD7886
AD7886 DYNAMIC SPECIFICATIONS AD7886 specified dynamic performance specifications well traditional specifications such integral differential nonlinearity. These specifications required signal processing applications such speech recognition, spectrum analysis high speed modems. These applications require information ADC's effect spectral content input signal. Hence, parameters which AD7886 specified include SNR, harmonic distortion, intermodulation distortion peak harmonics. These terms discussed more detail following sections.
Signal-to-Noise Ratio (SNR)
Figure shows typical plot effective number bits versus frequency sampling frequency kHz. Input frequency range this particular graph limited test equipment FS/4. effective number bits typically falls between 10.9 11.2, corresponding figures 67.38 69.18
EFFECTIVE NUMBER BITS
11.5
measured signal-to-noise ratio output ADC. signal magnitude fundamental. Noise nonfundamental signals half sampling frequency (FS/2), excluding dependent upon number quantization levels used digitization process; more levels, smaller quantization noise. theoretical signal noise ratio sine wave input given (6.02N 1.76) where number bits. Thus, ideal 12-bit converter, output spectrum from evaluated applying sine wave signal very distortion input, which sampled sampling rate. Fast Fourier Transform (FFT) plot generated from which data obtained. Figure shows typical 2048 point plot with input signal sampling frequency kHz.
10.5 SAMPLING FREQUENCY 750kHz INPUT FREQUENCY FS/4
Figure Effective Number Bits Frequency
Total Harmonic Distortion (THD)
ratio harmonics fundamental. AD7886, defined
where amplitude fundamental amplitudes second through sixth harmonic. also derived from plot output spectrum.
Intermodulation Distortion (IMD)
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). Using CCIF standard, where input frequencies near input bandwidth used, second third order terms different significance. second order terms usually distanced frequency from original sine waves, while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental, expressed dBs. this case, input consists two, equal amplitude, distortion sine waves. Figure shows typical plot AD7886.
Peak Harmonic Spurious Noise
Figure AD7886 Plot
obtained from this graph should noted that harmonics taken into account when calculating SNR.
Effective Number Bits
formula given Equation relates number bits. Rewriting formula, Equation possible obtain measure performance expressed effective number bits (N).
-1.76 6.02
effective number bits device calculated directly from measured SNR. REV.
Peak harmonic spurious noise defined ratio value next largest component output spectrum FS/2 excluding value fundamental. Normally, value this specification will
AD7886
determined largest harmonic spectrum, parts where harmonics buried noise floor, peak will noise peak.
TIMER ADDRESS
ADDR ENCODE
CONVST
TMS320C10
AD7886*
BUSY DB11
DATA *ADDITIONAL PINS OMITTED CLARITY
Figure AD7886 Plot
MICROPROCESSOR INTERFACING
Figure AD7886-TMS320C10 Interface
AD7886 designed interface microprocessors memory mapped device. control inputs common memory peripheral interfacing. Figures demonstrate typical interfaces AD7886.
AD7886-TMS320C10/TMS32020
TIMER ADDRESS
Figures show typical interfaces TMS320C10 TMS32020 processors. external timer controls conversion start processor. each conversion, ADC's BUSY output interrupts microprocessor. conversion result then read from with following instruction: D,ADC (ADC address)
AD788S ADSP-2100/TMS320C25/DSP56000
ADDR ENCODE
CONVST
TMS32020
INTn STRB
AD7886*
BUSY DB11
Some faster processors have data access times outside capabilities AD7886. Interfacing such processors requires either single WAIT state external latches. Examples shown Figures single WAIT state TMS320C25 ADSP-2100 interfaces extends read instruction processor cycle. DSP56000 example, ADC's data first clocked into 74HC374 latches before being read processor. AD7886's inputs tied permanently low, rising edge BUSY updates latches conversion. Both methods overcoming very fast data access time required these processors interchangeable, i.e., WAIT state used DSP56000, eliminating need latches vice versa, other interfaces. three interfaces, external timer controls conversion start; processor interrupted each conversion ADC's BUSY output. following instruction then reads data from ADC: ADSP-2100 DM(ADC) TMS320C25 D,ADC DSP56000 MOVEP Y:ADC,XO Assuming memory mapped into locations memory space. (ADC address) -10-
DATA *ADDITIONAL PINS OMITTED CLARITY
Figure AD7886-TMS32020 Interface
REV.
AD7886
TIMER DMA13 DMA0 ADDR ENCODE DMACK CONVST ADDRESS
AD7886-MC68000
AD7886*
74HC74
BUSY DB11
ADSP-2100
IRQn DMRD
Applications requiring conversions initiated microprocessor rather than external timer decode CONVST signal from address bus. example given Figure with MC68000 processor. write instruction starts conversion while read instruction reads data when conversion complete. delay least long conversion time must allowed between initiating conversion reading data into processor. Figure BUSY used drive processor into WAIT state processor attempts read data before conversion complete. Conversion initiated with write instruction ADC: Move.W D0,ADC (ADC address) Data transferred processor with read instruction; BUSY will force processor WAIT conversion conversion progress. Move.W ADC,DO
DMD15 DATA DMD0 *ADDITIONAL PINS OMITTED CLARITY
(ADC address)
Figure AD7886-ADSP-2100 Interface
ADDRESS TIMER
ADDRESS ADDR ENCODE
TMS320C25
READY STRB
ADDR ENCODE
CONVST
CONVST
AD7886*
DTACK BUSY
BUSY DB11
DATA
AD7886* MC68000
DB11
DATA *ADDITIONAL PINS OMITTED CLARITY
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7886-TMS320C25 Interface
ADDRESS ADDR ENCODE CONVST TIMER
Figure AD7886-MC68000 Interface
AD7886-Z-80/8085A
8-bit processors, external latch required store four bits conversion result LSBs Figure 21). data then read bytes: read from second from latch. Figure shows typical interface suitable Z-80 8085A. shown Figure 8-bit latch needed demultiplex 8085A common address/data bus. following LOAD instruction reads conversion result into register pair: 8085A-LHLD Z-80-LDHL (ADC) (ADC address) (ADC) (ADC address)
BUSY
AD7886*
DB11
DSP56000
74HC374
DATA *ADDITIONAL PINS OMITTED CLARITY
This byte read instruction. first byte read high byte (DB11 DB4). first read operation, rising edge clocks LSBs into 74HC374 latches. second byte LSBs) then read from these latches.
Figure AD7886-DSP56000 Interface
REV.
-11-
AD7886
ADDRESS ADDR ENCODE MREQ BUSY
DATA ACQUISITION BOARD
TIMER
CONVST
Figure shows typical data acquisition circuit designed microprocessor environment. corresponding board layout silkscreen shown Figures analog input AD7886 buffered with AD845 amp. component grid provided near analog input board that used antialiasing filter other conditioning circuitry. facilitate this option, link (labeled LK4) required analog input. AD586 voltage reference AD707 provide appropriate reference biasing required AD7886. ADC's data outputs buffered with 74HC374 latches. These provide data isolation improve data access time. Data access time reduced under allowing interfacing virtually microprocessor, including high speed processors. Data format either complete parallel load 16-bit processors two-byte load 8-bit processors. INTERFACE CONNECTIONS There connectors labeled SKT3 SKT4. SKT3 96-contact (3-row) connector, which directly compatible with ADSP-2100 evaluation board prototype expansion connector. expansion connector ADSP-2100 board eight decoded chip enable outputs labeled ECE1 ECE8. ECE6 used select AD7886 data acquisition board. avoid selecting on-board sockets same time, ADSP-2100 board must removed. addition, ADSP-2100 expansion connector four interrupts labeled EIRQ0 EIRQ3. AD7886's BUSY output connects EIRQ0. SKT3 pinout shown Figure Data format ADSP-2100 connector left justified, i.e., DB11 conversion result connected DMD15 connector. DMD3 DMD0 always zero. SKT4 22-way row) pin-header connector. This connector contains signal contacts SKT3 with exception EDMACK trailing zeros 16-bit data word. Only 12-bit conversion results SKT4. pinout shown Figure
DB10 BUSY DB11 OUT1 OUT2 DGND
AD7886*
DB11
Z-80 8085A
74HC374
DATA
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7886-Z-80/8085A Interface
APPLICATION HINTS Good printed circuit (PC) board layout important circuit design itself achieving high speed performance. AD7886's comparators required make decisions size 1.22 achieve this, designer conscious noise both itself preceding analog circuitry. Switching mode power supplies recommended switching spikes will feed through comparator, causing noisy code transitions. Other causes concern ground loops digital feedthrough from microprocessors. These factors that influence ADC, proper board layout that minimizes these effects essential best performance.
LAYOUT HINTS
Ensure that layout printed circuit board digital analog signal lines separated much possible. Take care digital track alongside analog signal track. Guard (screen) analog input with AGND. Establish single point analog ground (star ground) separate from logic system ground AD7886 AGND close possible AD7886. Connect other grounds AD7886 DGND this single analog ground point. connect other digital grounds this analog ground point. Because impedance analog digital power supply common returns essential noise operation ADC, make foil width these tracks wide possible. ground planes minimizes impedance paths also guards analog circuitry from digital noise. circuit layout Figures have both analog digital ground planes that kept separated only joined together AD7886 AGND.
NOISE
Keep input signal leads signal return leads from AGND short possible minimize input noise coupling. applications where this possible, shielded cable between source ADC. Reduce ground circuit impedance much possible since potential difference grounds between signal source appears error voltage series with input signal. -12-
DGND
CONNECT
Figure SKT4 Pinout
REV.
AD7886
POWER SUPPLY CONNECTIONS
board requires analog power supplies digital supply. Connections analog supply made directly board shown silkscreen Figure connections labeled range both these supplies Connection digital supply made through either connectors (SKT3 SKT4). analog supplies required AD7886 generated from voltage regulators power supplies.
LINK OPTIONS
these latches required, they removed data digital paths shorted out, i.e., latch inputs shorted outputs using wire links latch sockets. When using latches, AD7886 control inputs, must tied links latches updated rising edge BUSY signal every conversion. Data then read asserting latch output enable signals. alternative remove latches assert ADC's control inputs from either connectors, SKT3 SKT4, outlined data sheet. Latches Included Insert Link Insert Link
Analog Input Option
There five link options, labeled LK5, which must before using board.
Input Range Select
Latches Removed Remove Link Remove Link
AD7886 accommodate three possible analog input ranges: link options follows: Link Link Link
connects analog input component grid buffer amplifier that drives input.
Control Input Options
evaluation board includes latches increase data access time when interfacing faster machines.
SKT3 96-WAY CONNECTOR DMD15 DMD8 ECE6 (OUT1) EDMACK 0.1µF 74HC374 10µF 78L05 DB11 VREF
Data format 16-bits parallel bytes 8-bit processors. There data enable controls 74HC374 latches, labeled OUT1 OUT2. OUT1 enables MSBs (IC8), OUT2 enables LSBs (IC9). Link options are: 16-bit format, include LK5, byte read format, remove LK5.
0.1µF
10µF 0.1µF
10µF VOUT AD707 +VIN 0.1µF 10µF
5REF
0.1µF 10µF 0.1µF 10µF
AD586
0.1µF
AD7886
VIN1
OUT2 DMD7 DMD0
74HC374
VIN2 DGND 0.1µF 10µF
BUSY
AGND AD845 0.1µF SKT2
A32/B32/
EIRQ0 CONVST
AGND C10/C18 0.1µF C9/C17 10µF
10µF
ANALOG INPUT
CONVST
DIGITAL
79L05
CONVST SKT1
Figure Data Acquisition Circuit Using AD7886
REV.
-13-
AD7886
COMPONENT LIST
IC8,
AD7886, 12-Bit Sampling AD845, AD586, Precision Voltage Reference AD707, MC78L05, Regulator MC79L05, Regulator 74HC04, Inverter 74HC374, Octal Latches with Three-State Outputs
C11, C13, C17, C19, C10, C12, C14, C16, C18, C20, C22, SKT1, SKT2 SKT3 SKT4
Capacitors
Capacitors Sockets 96-Contact Row) Eurocard Connector 22-Way Row) Header Socket
Figure Board Silkscreen Figure
-14-
REV.
AD7886
Figure Board Component Side Layout Figure
Figure Board Solder Side Layout Figure
REV.
-15-
AD7886
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Pin Ceramic (D-28)
C1485b-10-4/91
28-Pin PLCC (P-28A)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33)
IDENTIFIER
VIEW
(PINS DOWN)
0.050 (1.27)
0.032 (0.81) 0.026 (0.66)
0.430 (10.92) 0.390 (9.91)
0.020 (0.50)
0.456 (11.58) 0.450 (11.43) 0.495 (12.57) 0.485 (12.32)
0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
-16-
REV.
PRINTED U.S.A.

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