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LC2MOS 12-Bit, 750 kHz / 1 MHz, Sampling ADC AD7886

VDD R3 VIN1 10k R4 VIN2 10k +5REF R1 9k SUM R2 6.3k VREF 4096 RESISTOR DAC AGND ­ + T / H 3.5k R5 CLOCK OSCILLATOR AND TIMER CONTROL TIMER BUSY CS RD CONVST

FEATURES 750 kHz / 1 MHz Throughput Rate 1 s / 750 ns Conversion Time 12-Bit No Missed Codes Over Temperature 67 dB SNR at 100 kHz Input Frequency Low Power-250 mW typ Fast Bus Access Time-57 ns max APPLICATIONS Digital Signal Processing Speech Recognition and Synthesis Spectrum Analysis DSP Servo Control
LC2MOS 12-Bit, 750 kHz / 1 MHz, Sampling ADC AD7886
FUNCTIONAL BLOCK DIAGRAM
VDD R3 VIN1 10k R4 VIN2 10k +5REF R1 9k SUM R2 6.3k VREF 4096 RESISTOR DAC AGND - + T / H 3.5k R5 CLOCK OSCILLATOR AND TIMER CONTROL TIMER BUSY CS RD CONVST
4-BIT LATCH 15 COMPARATORS AND 4-BIT FLASH LOGIC DB11 4-BIT LATCH THREE STATE OUTPUTS DB0
4-BIT LATCH SEGMENT SELECT
AD7886
VSS DGND
GENERAL DESCRIPTION
Contact your local salesperson for further information on the 1 MHz version.
PRODUCT HIGHLIGHTS
1. Fast 1.33 µs / 1 µs Throughput Time. Fast throughput time makes the AD7886 suitable for a wide range of data acquisition applications. 2. Dynamic Specifications for DSP Users. The AD7886 is specified for ac parameters, including signal-to-noise ratio, harmonic distortion and intermodulation distortion. Key digital timing parameters are also tested and guaranteed over the full operating temperature range. 3. Fast Microprocessor Interface. Standard control signals, CS and RD, and fast bus access times make the AD7886 easy to interface to microprocessors. 4. Low Power. LC2MOS fabrication process gives low power dissipation of 250 mW.
REV. B
DD SS REF MIN MAX
Parameter DYNAMIC PERFORMANCE2 Signal-to-Noise Ratio3 (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms ACCURACY Resolution Integral Linearity TMIN to TMAX Minimum Resolution for Which No Missing Codes Are Guaranteed Unipolar Offset Error @ +25°C TMIN to TMAX Bipolar Offset Error @ +25°C TMIN to TMAX Unipolar Gain Error @ +25°C TMIN to TMAX Bipolar Gain Error @ +25°C TMIN to TMAX ANALOG INPUT Unipolar Input Current Bipolar Input Current REFERENCE INPUT VREF Input Reference Current R1, Resistance R2, Resistance R2 / R1 Ratio
J Version1
K, B Versions1
T Version1
Units
Test Conditions / Comments
dB min dB typ dB typ dB typ dB typ
Bits LSB max Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max
mA max mA max
Volts mA max k nom k nom nom
POWER SUPPLY REJECTION
V min V max µA max pF max
V min V max pA max pF max
V nom V nom mA max mA max mW typ mW max
REV. B
AD7886 TIMING CHARACTERISTICS1 (V
Parameter t1 t2 t3 t4 t5 t6 t7 3 t8 t9 3 t10 t11 t12 t13 tCONV
Limit at Limit at TMIN, TMAX TMIN, TMAX (J, K Versions) (B Version) 50 1 0 0 60 100 57 10 50 20 10 10 100 0 0 250 1.333 950 1000 50 1 0 0 60 100 57 10 50 20 10 10 100 0 0 250 1.333 950 1000
Limit at TMIN, TMAX (T Version) 50 1 0 0 75 100 70 10 60 14 0 10 100 0 0 250 1.333 950 1000
Units ns min Fs max ns min ns min ns min ns max ns max ns min ns max ns min ns min ns min ns max ns min ns min ns typ µs min ns typ ns max
TO OUTPUT PIN
+2.1V CL
VIN1, VIN2, SUM, +5REF to AGND . . . . . . -15 V to +15 V VREF to AGND . . . . . . . . . . . . . . . . VSS -0.3 V to VDD +0.3 V Digital Inputs to DGND CS, RD, CONVST . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Digital Outputs to DGND DB0 to DB11, BUSY . . . . . . . . . . . . . -0.3 V to VDD +0.3 V Operating Temperature Range Commercial (J, K Versions) . . . . . . . . . . . . . . 0°C to +70°C Industrial (B Version) . . . . . . . . . . . . . . . . -40°C to +85°C Extended (T Version) . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature Range . . . . . . . . . . . .-65°C to + 150°C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C Power Dissipation (Any Package) to +75°C . . . . . . 1000 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW / °C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 If VSS is open circuited with V DD and AGND applied, the V SS pin will be pulled positive, exceeding the Absolute Maximum Ratings. If this possibility exists, a Schottky diode from V SS to DGND (cathode end to GND) ensures that the
Figure 1. Load Circuit for Bus Access and Relinquish Time
ABSOLUTE MAXIMUM RATINGS 1, 2
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7886 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
REV. B
AD7886
ORDERING GUIDE
Model1, 2 AD7886JD AD7886KD AD7886JP AD7886KP AD7886BD AD7886TD
Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -55°C to +125°C
SNR (dBs) 65 67 65 67 67 65
Package Option3 D-28 D-28 P-28A2 P-28A2 D-28 D-28
PIN FUNCTION DESCRIPTION
DIP Pin Number
Mnemonic
Power Supply 10 & 19 VDD 15 & 24 VSS 16 & 23 AGND 5 DGND
Interface and Control 1-4, DB7-DB4 6-9, DB3-DB0 25-28 DB11-DB8 11 BUSY 12 CS 13 RD 14 CONVST
REV. B
AD7886
PIN CONFIGURATIONS DIP
DB4 DB5
28 DB8 27 DB9 26 DB10 25 DB11 24 VSS
DGND DB3 DB2 DB1 DB0 5 6 7 8 9 25 DB11 24 VSS
DB7 DB10 DB6 DB8 DB9
DB7 DB6 DB5 DB4 DGND DB3 DB2 DB1 DB0
AD7886
TOP VIEW (Not to Scale)
23 AGND 22 VREF 21 SUM 20 +5REF 19 VDD 18 VIN2 17 VIN1 16 AGND 15 VSS
AD7886
TOP VIEW (Not to Scale)
23 AGND 22 VREF 21 SUM 20 +5REF 19 VDD
VDD 10 BUSY 11
VDD 10 BUSY 11 CS 12 RD 13 CONVST 14
CONVST
TERMINOLOGY
Unipolar Offset Error
The ideal first code transition should occur when the analog input is 1 LSB above AGND. The deviation of the actual transition from that point is termed the offset error.
Bipolar Zero Error
result. The 12 bits of data are then stored internally in a threestate output latch.
REFERENCE INPUT
The ideal midscale transition (i.e., 0111 1111 1111 to 1000 0000 0000) for the +5 V range should occur when the analog input is at zero volts. Bipolar zero error is the deviation of the actual transition from that point.
Gain Error
CONVERTER DETAILS
The AD7886 operates from a 3.5 V reference, which must be provided at the VREF input. Two on-chip resistors for use with an external amplifier can be used for deriving 3.5 V from standard 5 V references. Figure 2 shows an example with the AD586 which a is a high performance voltage reference exhibiting excellent stability performance, 5 ppm / °C max. The external amplifier serves a second function of force / sensing the VREF input. Force / sensing minimizes error contributions from
+V +VIN VOUT +5V +5REF R1 9k SUM R2 6.3k VREF
AD586
AD7886
AD707 - +
-3.5V
The AD7886 is a triple-pass flash ADC that uses 15 comparators in a 4-bit flash technique to perform the 12-bit conversion procedure. Each of the 4096 quantization levels is realized internally with a precision resistor DAC. The fifteen comparators first compare the analog input voltage to the VREF / 16 voltages of the resistor array. This determines the four most significant bits and selects 1 out of 16 voltage segments. The comparators are then switched to 15 subvoltages on that segment to determine the next four bits and select 1 out of 256 voltage segments. A further switching of the comparators to another 15 subvoltages produces the complete 12-bit conversion REV. B -5-
C1 10µF
TO DAC AGND C2 0.1µF
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 2. Typical Reference Circuitry
AD7886
this amplifier typically by 20 MHz which is much greater than the Nyquist limit of the ADC as a result, it can be used for undersampling applications. The track-and-hold amplifier acquires the input signal to 12-bit accuracy in less than 333 ns. The overall throughput time is equal to the conversion time plus the track / hold amplifier acquisition time, which is 1.333 µs for the AD7886.
+V + 5V AIN VIN1 0 TO 5V OR 0 TO 10V VDD
The operation of the track / hold amplifier is essentially transparent to the user. The track-to-hold transition occurs at the start of conversion on the falling edge of CONVST. The conversion procedure does not start until the rising edge of CONVST. The width of the CONVST pulse low time determines the track-to hold settling time. The track / hold reverts back to the track mode at the end of conversion when BUSY has returned high.
0 TO 5V ANALOG INPUT RANGE 3.5k 10k
+VIN VOUT + 5V
AD7886
+ 5REF
AD586
GND SUM
AD707 - +
- 3.5V VREF
VIN1 VIN2 0 TO 5V
VSS C1 10µF C2 0.1µF - 5V
TO COMPARATORS
0 TO 10V ANALOG INPUT RANGE 3.5k 0 TO 10V 10k
ADDITIONAL PINS OMITTED FOR CLARITY 0 TO 5V RANGE: CONNECT VIN2 TO VIN1 0 TO 10V RANGE: CONNECT VIN2 TO AGND
Figure 4. Unipolar Operation
OUTPUT CODE
VIN1 VIN2
TO COMPARATORS
VIN1 VIN2
FS 4096
TO COMPARATORS
Figure 3. Analog Input Range Configurations
ANALOG INPUT RANGES
UNIPOLAR OPERATION
VIN, INPUT VOLTAGE (LSBS) FS - 1LSB
Figure 5. Ideal Input / Output Transfer Characteristic for Unipolar Operation
REV. B
AD7886
OFFSET AND GAIN ADJUSTMENT BIPOLAR OPERATION
In most digital signal processing (DSP) applications, offset and full-scale errors have little or no effect on system performance. Offset error can usually be eliminated in the analog domain by ac coupling. Full-scale errors do not cause problems as long as the input signal is within the full dynamic range of the ADC. For applications requiring that the input signal range match the full analog input dynamic range of the ADC, offset and fullscale errors must be adjusted to zero.
UNIPOLAR OFFSET AND GAIN ERROR ADJUSTMENT
AD586
GND SUM
AD707 - +
- 3.5V
AD7886
VREF VSS
C1 10µF
C2 0.1µF - 5V
AD845 +
A1 VIN1 VDD
OUTPUT CODE
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 7. Bipolar Operation
+V AGND +VIN VOUT + 5V + 5REF R1 82k SUM
11..111 11..110 11..101 10..010 10..001 - FS +1LSB 2
AD586
AD707
- 3.5V
AD7886
R2 56k C1 10µF C2 0.1µF VSS
- 5V ADDITIONAL PINS OMITTED FOR CLARITY 0 TO 5V RANGE: CONNECT VIN2 TO VIN1 0 TO 10V RANGE: CONNECT VIN2 TO AGND
VIN, INPUT VOLTAGE - LSBs
Figure 6. Unipolar Operation with Gain Error Adjust
Figure 8. Ideal Input / Output Characteristics for Bipolar Operation
REV. B
AD7886
BIPOLAR OFFSET AND GAIN ADJUSTMENT
In applications where absolute accuracy is important, offset and gain error can be adjusted to zero. Offset is adjusted by trimming the voltage at the VIN1 or VIN2 input when the analog input is at zero volts. This can be achieved by adjusting the offset of an external amplifier used to drive either of these inputs (see A1 in Figure 9). The trim procedure is as follows: Apply zero volts at AIN and adjust the offset of A1 until the ADC output code flickers between 0111 1111 1111 and 1000 0000 0000. Gain error can be adjusted at either the first code transition (ADC negative full scale) or the last code transition (ADC positive full scale). Adjusting the reference, as in Figure 9, will trim the positive gain error only. The trim procedure is as follows: Apply a voltage of 4.99756 V, (FS / 2-1 LSB) at AIN and adjust R3 until the output code flickers between 1111 1111 1110 and 1111 11111111. If the first code transition needs adjusting, a gain trim must be included in the analog signal path. The trim procedure will then consist of applying an analog signal of -4.99756 V (-FS / 2+1 LSB) and adjusting the trim until the output code flickers between 0000 0000 0000 and 0000 0000 0001.
TRACK-TO-HOLD TRANSITION
AD845 +
A1 VIN1 VIN2 VDD
CONVST
CONVERSION START HOLD TO TRACK TRANSITION
+V AGND +VIN VOUT + 5V + 5REF R1 82k R3 5k R2 56k SUM
t5 t CONV
t11 t7
DATA VALID
AD586
AD707 - 3.5V - VREF +
DATA HIGH IMPEDANCE
AD7886
C1 10µF C2 0.1µF VSS - 5V
Figure 10. Conversion Start and Data Read Timing Diagram
TRACK-TO-HOLD TRANSITION
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. Bipolar Operation with Gain Error Adjust
CONVST
CONVERSION START
TIMING AND CONTROL
HOLD TO TRACK TRANSITION
DATA VALID
HIGH IMPEDANCE
REV. B
AD7886
Signal-to-Noise Ratio (SNR)
Figure 13 shows a typical plot of effective number of bits versus frequency for a sampling frequency of 750 kHz. Input frequency range for this particular graph was limited by the test equipment to FS / 4. The effective number of bits typically falls between 10.9 and 11.2, corresponding to SNR figures of 67.38 dB and 69.18 dB.
EFFECTIVE NUMBER OF BITS
Figure 13. Effective Number of Bits vs. Frequency
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental. For the AD7886, THD is defined as
where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonic. The THD is also derived from the FFT plot of the ADC output spectrum.
Intermodulation Distortion (IMD)
Peak Harmonic or Spurious Noise
Figure 12. AD7886 FFT Plot
The SNR obtained from this graph is 68 dB. It should be noted that the harmonics are taken into account when calculating the SNR.
Effective Number of Bits
The formula given in Equation 1 relates the SNR to the number of bits. Rewriting the formula, as in Equation 2, it is possible to obtain a measure of performance expressed in effective number of bits (N).
The effective number of bits for a device can be calculated directly from its measured SNR. REV. B
Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to FS / 2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification will be
AD7886
determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, the peak will be a noise peak.
TIMER PA2 PA0 ADDRESS BUS
ADDR ENCODE MEN EN
CONVST CS
TMS320C10
INT DEN
AD7886
BUSY RD DB11 DB0
D15 D0 DATA BUS ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. AD7886 IMD Plot
MICROPROCESSOR INTERFACING
Figure 15. AD7886-TMS320C10 Interface
The AD7886 is designed to interface to microprocessors as a memory mapped device. Its CS and RD control inputs are common to all memory peripheral interfacing. Figures 15 to 21 demonstrate typical interfaces for the AD7886.
AD7886-TMS320C10 / TMS32020
TIMER A15 ADDRESS BUS A0
AD788S ADSP-2100 / TMS320C25 / DSP56000
ADDR ENCODE IS EN
CONVST CS
TMS32020
INTn STRB R / W
AD7886
BUSY RD DB11 DB0
D15 D0
DATA BUS ADDITIONAL PINS OMITTED FOR CLARITY
Figure 16. AD7886-TMS32020 Interface
REV. B
AD7886
TIMER CLK OUT DMA13 DMA0 ADDR ENCODE DMS DMACK EN + 5V Q CLR CONVST CS ADDRESS BUS
AD7886-MC68000
AD7886
74HC74 D
CLK BUSY RD DB11 DB0
ADSP-2100
IRQn DMRD
DMD15 DATA BUS DMD0 ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. AD7886-ADSP-2100 Interface
A15 A0 ADDRESS BUS TIMER
ADDRESS BUS A0 ADDR ENCODE AS EN CS
TMS320C25
IS READY MSC STRB R / W INT
ADDR ENCODE EN
CONVST CS
CONVST
AD7886
R / W DTACK RD BUSY
RD BUSY DB11 DB0
D11 DATA BUS D0
AD7886 MC68000
DB11 DB0
D15 D0 DATA BUS ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. AD7886-TMS320C25 Interface
A15 A0 X / Y DS ADDRESS BUS ADDR ENCODE CONVST CS RD TIMER
Figure 20. AD7886-MC68000 Interface
AD7886-Z-80 / 8085A
EN1 EN2
AD7886
RD OE Q11 CLK D11 D0 DB11 DB0
DSP56000
2X 74HC374
D23 DATA BUS D0 ADDITIONAL PINS OMITTED FOR CLARITY
This is a two byte read instruction. The first byte to be read has to be the high byte (DB11 to DB4). At the end of the first read operation, the rising edge of CS and RD clocks the 4 LSBs into 74HC374 latches. The second byte (4 LSBs) is then read from these latches.
Figure 19. AD7886-DSP56000 Interface
REV. B
AD7886
A15 A0 ADDRESS BUS ADDR ENCODE MREQ RD INT EN RD BUSY
DATA ACQUISITION BOARD
TIMER
CONVST CS
DB0 DB2 DB4 DB6 DB8 DB10 BUSY CS NC VCC 22 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 DB1 DB3 DB5 DB7 DB9 DB11 OUT1 OUT2 RD VCC DGND
CLK D3 D0
AD7886
DB3 DB0 DB11 DB4
Z-80 8085A
74HC374
D7 D0 DATA BUS
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7886-Z-80 / 8085A Interface
LAYOUT HINTS
Ensure that the layout for the printed circuit board has the digital and analog signal lines separated as much as possible. Take care not to run any digital track alongside an analog signal track. Guard (screen) the analog input with AGND. Establish a single point analog ground (star ground) separate from the logic system ground at the AD7886 AGND or as close as possible to the AD7886. Connect all other grounds and the AD7886 DGND to this single analog ground point. Do not connect any other digital grounds to this analog ground point. Because low impedance analog and digital power supply common returns are essential to low noise operation of the ADC, make the foil width for these tracks as wide as possible. The use of ground planes minimizes impedance paths and also guards the analog circuitry from digital noise. The circuit layout of Figures 25 and 26 have both analog and digital ground planes that are kept separated and only joined together at the AD7886 AGND.
NOISE
Keep the input signal leads to VIN and signal return leads from AGND as short as possible to minimize input noise coupling. In applications where this is not possible, use a shielded cable between the source and the ADC. Reduce the ground circuit impedance as much as possible since any potential difference in grounds between the signal source and the ADC appears as an error voltage in series with the input signal. -12-
Figure 22. SKT4 Pinout
REV. B
AD7886
POWER SUPPLY CONNECTIONS
The PC board requires two analog power supplies and one 5 V digital supply. Connections to the analog supply are made directly to the PC board as shown on the silkscreen in Figure 24. The connections are labeled V+ and V-, and the range for both of these supplies is 12 V to 15 V. Connection to the 5 V digital supply is made through either of the two connectors (SKT3 or SKT4). The +5 V analog supplies required by the AD7886 are generated from voltage regulators on the V- and V+ power supplies.
LINK OPTIONS
LK4 Analog Input Option
There are five link options, labeled LK1 to LK5, which must be set before using the board.
LK1 Input Range Select
Latches Removed Remove Link 2 Remove Link 3
LK4 connects the analog input to a component grid or to a buffer amplifier that drives the ADC input.
LK2 and LK3 Control Input Options
The evaluation board includes two latches to increase the data access time when interfacing to the faster DSP machines. If
SKT3 96-WAY CONNECTOR + 5V DMD15 DMD8 ECE6 (OUT1) O / P EDMACK B6 LK5 GND + 5V C20 0.1µF + 5V VCC Q7 74HC374 Q0 IC8 D7 D0 C19 10µF +V IN OUT 78L05 IC5 GND VDD DB11 DB4 VREF + 5V
Data format can be 16-bits parallel or two bytes for 8-bit processors. There are two data enable controls for the 74HC374 latches, labeled OUT1 and OUT2. OUT1 enables the 8 MSBs (IC8), and OUT2 enables the 4 LSBs (IC9). Link options are: for 16-bit format, include LK5, for a two byte read format, remove LK5.
C8 0.1µF
C7 10µF C14 0.1µF
+V C13 10µF VOUT IC4 AD707 +VIN +V C6 0.1µF C5 10µF
A31 B11 B18 C22
+ 5REF
SUM - + -V C10 0.1µF C11 10µF C16 0.1µF C15 10µF
AD586 IC3
CLK C23 0.1µF
IC1 AD7886
DB3 DB0 VIN1
C11 B20 B27
OUT2 DMD7 DMD0
VCC D7 74HC374 D4 IC9 D3 O / P D2 Q7 D1 D0 Q0 GND CLK
+V VIN2 A B DGND LK1 C4 0.1µF C3 10µF
C AGND - AD845 + -V C2 0.1µF IC2 LK4 SKT2
A9 C14 C13 C12 A32 / B32 / C32
EIRQ0 CS RD CONVST
CS RD AGND VSS - 5V C10 / C18 0.1µF C9 / C17 10µF
C1 10µF
ANALOG INPUT
CONVST VSS LK2 LK3 -V IN OUT
DIGITAL GND
79L05 IC6
GND CONVST SKT1
Figure 23. Data Acquisition Circuit Using the AD7886
REV. B
AD7886
COMPONENT LIST
IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8, IC9
AD7886, 12-Bit Sampling ADC AD845, Op Amp AD586, Precision Voltage Reference AD707, Op Amp MC78L05, + 5 V Regulator MC79L05, -5 V Regulator 74HC04, Hex Inverter 74HC374, Octal Latches with Three-State Outputs
C1, C3, C5, C7, C9, C11, C13, C15 C17, C19, C21 C2, C4, C6, C8, C10, C12, C14, C16, C18, C20, C22, C23 SKT1, SKT2 SKT3 SKT4
10 µF Capacitors
0.1 µF Capacitors BNC Sockets 96-Contact (3 Row) Eurocard Connector 22-Way (2 Row) Pin Header and Socket
Figure 24. PC Board Silkscreen for Figure 23
REV. B
AD7886
Figure 25. PC Board Component Side Layout for Figure 23
Figure 26. PC Board Solder Side Layout for Figure 23
REV. B
AD7886
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Ceramic DIP (D-28)
C1485b-10-4 / 91
28-Pin PLCC (P-28A)
4 5 PIN 1 IDENTIFIER
TOP VIEW
(PINS DOWN) 11 12 19 18
0.050 (1.27) BSC
0.020 (0.50) R
0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32)
REV. B
PRINTED IN U.S.A.