FEATURES Complete with Interface, Comprising: Track/Hold Amplifier wit

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LC2MOS Complete 12-Bit Sampling with Interface AD7878
FEATURES Complete with Interface, Comprising: Track/Hold Amplifier with Acquisition Time Converter Zener Reference 8-Word FIFO Interface Logic Input Frequency Interfaces High Speed Processors, e.g., ADSP-2100, TMS32010, TMS32020 Data Access Time Power, APPLICATIONS Digital Signal Processing Speech Recognition Synthesis Spectrum Analysis High Speed Modems Servo Control
GENERAL DESCRIPTION
AD7878 fast, complete, 12-bit converter with versatile interface consisting 8-word, first-in, first-out (FIFO) memory associated control logic. FIFO memory allows eight samples digitized before microprocessor required service converter. eight words then read FIFO maximum microprocessor speed. fast data access time allows direct interfacing processors high speed 16-bit microprocessors. on-chip status/control register allows user program effective length FIFO contains FIFO range, FIFO empty FIFO word count information. analog input AD7878 bipolar range AD7878 convert full power signals fully specified dynamic parameters such signal-to-noise ratio harmonic distortion. AD7878 fabricated Linear Compatible CMOS (LC2MOS), advanced, mixed technology process that combines precision bipolar circuits with power CMOS logic. part available four package styles, 28-pin plastic hermetic dual-in-line package (DIP), leadless ceramic chip carrier (LCCC) plastic leaded chip carrier (PLCC).
PRODUCT HIGHLIGHTS
Complete Function with Interface AD7878 provides complete function digitizing signals 12-bit accuracy. part features on-chip track/hold, on-chip reference 12-bit converter. additional feature 8-word FIFO reduces high software overheads associated with servicing interrupts processors. Dynamic Specifications Users AD7878 fully specified tested parameters, including signal-to-noise ratio, harmonic distortion intermodulation distortion. digital timing parameters also tested specified over full operating temperature range. Fast Microprocessor Interface Data access time fastest ever achieved monolithic converter, makes AD7878 compatible with modern 16-bit microprocessors digital signal processors.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
AD7878-SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)3 25°C TMIN TMAX Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Track/Hold Acquisition Time ACCURACY Resolution Minimum Resolution Which Missing Codes Guaranteed Relative Accuracy Differential Nonlinearity Bipolar Zero Error Positive Full-Scale Error4 Negative Full-Scale Error4 ANALOG INPUT Input Voltage Range Input Current REFERENCE OUTPUT5 Error 25°C TMIN TMAX Reference Load Sensitivity (REF OUT/I)
(VDD AGND DGND MHz. Specifications TMIN TMAX, unless otherwise noted.)
Units Test Conditions/Comments Sine Wave, fSAMPLE Typically 71.5 Sine Wave, fSAMPLE Typically kHz, fSAMPLE Typically kHz, kHz, fSAMPLE kHz, kHz, fSAMPLE Throughput Rate Section
Versions1 Versions Version
Bits Bits Volts
Reference Load Current Change µA-500 µA). Reference Load Should Changed During Conversion
LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, CIN6 LOGIC OUTPUTS Output High Voltage, Output Voltage, DB11-DB0 Floating State Leakage Current Floating State Output Capacitance6 CONVERSION TIME
+2.4 +0.8 +2.7 +0.4 7/7.125 7/9.250
+2.4 +0.8 +2.7 +0.4 7/7.125 7/9.250
+2.4 +0.8 +2.7 +0.4 7/7.125 7/9.250
min/µs min/µs
ISOURCE ISINK Assuming External Read/Write Operations Assuming External Read/Write Operations Internal Comparator Timing Section Specified Performance Specified Performance Specified Performance DMWR DMRD DMWR DMRD DMWR DMRD Typically
POWER REQUIREMENTS Power Dissipation
95.5
95.5
95.5
NOTES Temperature range follows: versions: +70°C; versions: -25°C +85°C; version: -55°C +125°C. Dynamic Specifications section. calculation includes distortion noise components. Measured with respect Internal Reference. capacitive loads greater than series resistor required (see Internal Reference section). Sample tested +25°C ensure compliance. Specifications subject change without notice.
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AD7878 TIMING CHARACTERISTICS1
Limit TMIN, TMAX Parameter Grade) t103 t142 tRESET Cycles Cycles
Units
Conditions/Comments BUSY Propagation Delay BUSY High Propagation Delay CONVST Pulse Width DMRD/REGISTER ENABLE Setup Time DMRD/ REGISTER ENABLE Hold Time DMRD Pulse Width ADD0 DMRD/REGISTER ENABLE Setup Time ADD0 DMRD/REGISTER ENABLE Hold Time Data Access Time after DMRD Relinquish Time REGISTER ENABLE Pulse Width Data Valid REGISTER ENABLE Setup Time Data Hold Time after REGISTER ENABLE Data Access Time after BUSY RESET Pulse Width
Limit TMIN, TMAX Grades) Cycles Cycles
Limit TMIN, TMAX Grade) Cycles Cycles
NOTES Timing Specifications bold print 100% production tested. other times sample tested ensure compliance. input signals specified with (10% timed from voltage level measured with load circuits Figure defined time required output cross defined time required data lines change when loaded with circuits Figure Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
+25°C unless otherwise stated)
High-Z
High-Z
Figure Load Circuits Access Time
High-Z
High-Z
DGND -0.3 DGND -0.3 DGND +0.3 -0.3 +0.3 AGND DGND -0.3 +0.3 AGND AGND Digital Inputs DGND DMWR, DMRD, RESET, CONVST, ADD0 -0.3 +0.3 Digital Outputs DGND ALFL, BUSY -0.3 +0.3 Data Pins DB11-DB0 -0.3 +0.3 Operating Temperature Range Versions +70°C Versions -25°C +85°C Version -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, sec) +300°C Power Dissipation (Any Package) +75°C 1000 Derates above +75°C mW/°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability
Figure Load Circuits Output Float Delay
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7878 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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AD7878
FUNCTION DESCRIPTION
Number Mnemonic ADD0 Function Address Input. This control input determines whether word placed output data during read operation data word from FIFO contents status/control register. logic accesses data word from Location FIFO while logic high selects contents register (see Status/Control Register section). Chip Select. Active logic input. device selected when this input active. Memory Write. Active logic input. DMWR used conjunction with ADD0 high write data status/control register. Corresponds DMWR (ADSP-2100), (MC68000, TMS32020), (TMS32010). Data Memory READ. Active logic input. DMRD used conjunction with enable three-state output buffers. Corresponds directly DMRD (ADSP-2100), (TMS32010). Active Logic Output. This output goes when receives CONVST pulse remains until track/hold gone into hold mode. three-state drivers AD7878 disabled while BUSY signal (see Extended READ/WRITE section). This achieved writing logic (DISO) status/control register. Writing logic status/control register allows data accessed from AD7878 while BUSY low. FIFO Almost Full. logic indicates that word count (i.e., number conversion results) FIFO memory reached programmed word count status/control register. ALFL updated each conversion. ALFL output reset logic high when word read from FIFO memory word count less than preprogrammed word count. also high writing logic (ENAF) status/control register. Digital Ground. Ground reference digital circuitry. Digital supply voltage, Positive supply voltage digital circuitry. Data (MSB). Three-state output. Coding data words FIFO twos complement. Data Data Three-state input/outputs. Data Data Three-state outputs. Data (LSB). Three-state output. Analog positive supply voltage, Analog Ground. Ground reference track/hold, reference DAC. Voltage Reference Output. internal analog reference provided this pin. external load capability reference Analog Input. Analog input range Analog negative supply voltage, Convert Start. Logic input. high transition this input puts track/hold into hold mode starts conversion. CONVST input asynchronous independent DMWR DMRD. Reset. Active logic input. logic sets words FIFO memory 1000 0000 0000 resets ALFL output status/control register. Clock Input. TTL-compatible logic input. Used clock source converter. mark-space ratio this clock vary from 35/65 65/35.
DMWR DMRD BUSY
ALFL
10-15 16-19
DGND DB11 DB10-DB5 DB4-DB1 AGND CONVST RESET
CONFIGURATIONS
PLCC
LCCC
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AD7878
ORDERING GUIDE
Temperature Range +70°C -25°C +85°C -55°C +125°C +70°C -25°C +85°C +70°C -55°C +125°C +70°C +70°C +70°C Signalto-Noise Ratio Data Access Time Package Options3 N-28 Q-28 Q-28 N-28 Q-28 N-28 E-28A P-28A P-28A P-28A
DB10-DB8 (AFC2-AFC0)
Model1, AD7878JN AD7878AQ AD7878SQ AD7878KN AD7878BQ AD7878LN AD7878SE4 AD7878JP AD7878KP AD7878LP
Almost Full Word Count, Read/Write. count value determines number words FIFO memory, which will cause ALFL set. When FIFO word count equals programmed count these three bits, both ALFL output DB11 status register logic low. example, when code written these bits, ALFL when Location through Location FIFO memory contains valid data. AFC2 most significant word count. count value read back required.
(ENAF)
Enable Almost Full, Read/Write. Writing this disables ALFL output status register DB11.
(FOVR/RESET)
NOTES order MIL-STD-883, Class processed parts, /883B part number. Contact local sales office military data sheet. Analog Devices reserves right ship either ceramic (D-28) packages cerdip (Q-28) hermetic packages. Leadless Ceramic Chip Carrier; Plastic DIP; Plastic Leaded Chip Carrier, Cerdip. Available /883B processing only.
FIFO Overrun/RESET, Read/Write. Reading from this indicates that least sample been discarded because FIFO memory full. When FIFO full (i.e., contains eight words) further conversion results will lost. Writing this causes system RESET RESET input (Pin 27).
(FOOR/DISO)
STATUS/CONTROL REGISTER
status/control register serves dual function providing control monitoring status FIFO memory. This register directly accessible through data (DB11-DB0) with read write operation while ADD0 high. write operation status/control register provides control ALFL output, interface FIFO counter reset. This normally done power-up initialization. FIFO memory address pointer incremented after each conversion compared with preprogrammed count status/control register. When this preprogrammed count reached, ALFL output asserted ENAF control zero. This ALFL used interrupt microprocessor after predetermined number conversions (between status address pointer along with sample overrange ALFL status accessed time reading status/ control register. Note: reading status/control register does cause internal data movement FIFO memory. Status information particular word should read from status register before data word read from FIFO memory.
STATUS/CONTROL REGISTER FUNCTION DESCRIPTION DB11 (ALFL)
FIFO RANGE/Disable Outputs, Read/Write. Reading from this indicates that least sample FIFO memory range. Writing this prevents data from becoming active while BUSY low, regardless state DMRD.
(FEMP)
FIFO Empty, Read Only. Reading indicates there samples FIFO memory. When FIFO empty internal ripple-down effects FIFO disabled further reads will continue access last valid data word Location
(SOOR)
Sample Range, Read Only. Reading indicates next sample read range, i.e., sample Location FIFO.
DB-DB0 (FCN2-FCN0)
Almost Full Flag, Read only. This same (ALFL output) status. logic indicates that word count FIFO memory reached preprogrammed count locations DB10-DB8. ALFL updated conversion.
FIFO Word Count, Read Only. value read from these bits indicates number samples FIFO memory. example, reading from these bits indicates that Location through Location contains valid data. Note: reading indicates there either word word FIFO memory; this case FIFO Empty determines there word memory. FCN2 most significant bit.
Table Status/Control Function Description
LOCATION STATUS INFORMATION (READ) CONTROL FUNCTION (WRITE) RESET STATUS
=DON'T CARE
DB11 ALFL
DB10 AFC2 AFC2
AFC1 AFC1
AFC0 AFC0
ENAF ENAF
FEMP
SOOR
FCN2
FCN1
FCN0
FOVR FOOR RESET DISO
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AD7878
INTERNAL FIFO MEMORY internal FIFO memory AD7878 consists eight memory locations. Each word memory contains bits information-12 bits data from conversion result additional which contains information whether 12bit result range not. block diagram AD7878 FIFO architecture shown Figure INTERNAL COMPARATOR TIMING clock, which applied controls successive approximation conversion process. This clock internally divided four yield trial cycle time (CLK clock). Each decision occurs after rising edge this divided clock. decision latched rising edge internal comparator strobe signal. There 12-bit decisions, normal successive approximation routine, extra decision that checks input sample range. normal successive approximation converter, reading data from device during conversion upset conversion progress. This on-chip transients, generated charging discharging databus, concurrent with decision. scheme outlined below shown Figure describes AD7878 overcomes this problem. internal comparator strobe AD7878 gated with both DMRD DMWR that read write operation occurs when decision about made, decision point deferred cycle. other words, DMRD DMWR goes (with low) time during time immediately prior comparator strobing edge (tLOW Figure trial suspended clock cycle. This makes sure that decision latched time when AD7878 attempting charge discharge data bus, thereby ensuring that spurious transients occur internally near decision point. decision point slippage mechanism shown Figure decision. Normally, decision occurs after fourth rising edge after CONVST goes high. However, timing diagram Figure DMRD DMWR time period tLOW prior decision point fourth rising edge. This causes internal comparator strobe slipped fifth rising clock edge. AD7878 will again check during period tLOW prior this fifth rising clock edge; DMRD DMWR still low, decision point will slipped further clock cycle. conversion time normally consists 13bit trials described above extra internal clock cycle during which data written from FIFO. input clock this results conversion time However, software routine servicing AD7878 potential read times from device during conversion-8 reads from FIFO reads from status/control register. also potential write once status/control register. these
Figure Internal FIFO Architecture
conversion result gathered successive approximation register (SAR) during conversion. conversion this result transferred FIFO memory. FIFO address pointer always points memory, which uppermost location containing valid data. pointer incremented after each conversion. read operation from FIFO memory accesses data from bottom FIFO, Location completion read operation, each data word moves down location address pointer decremented one. Therefore, each conversion result from enters memory, propagates down with successive reads until reaches Location from where accessed microprocessor read operation. transfer information from FIFO occurs synchronization with AD7878 input clock (CLK IN). propagation data words down FIFO also synchronous with this clock. result, read operation obtain data from FIFO must also synchronous with avoid Read/Write conflicts FIFO (i.e., reading from FIFO Location while being updated). This requires that microprocessor clock AD7878 derived from same source.
Figure Operational Timing Diagram
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AD7878
read plus write) operations occur during tLOW time periods, conversion time will slip cycles. Therefore, read write operations occur during tLOW periods, means that conversion time vary from 9.12 (assuming IN). This calculation assumes there slippage cycle each read write operation.
INITIATING CONVERSION
operation with ADD0 accesses data from FIFO while read with ADD0 high accesses data from status/ control register.
Conversion initiated AD7878 asserting CONVST input. This CONVST input asynchronous input independent either clocks. This essential applications where precise sampling time important. these applications signal sampling must occur exactly equal intervals minimize errors sampling uncertainty jitter. these cases CONVST input driven from tamer some precise clock source. receipt CONVST pulse, AD7878 acknowledges taking BUSY output low. This BUSY output used ensure activity while track/hold goes from track hold mode (see Extended Read/Write section). CONVST input must stay least periods. track/ hold amplifier switches from track hold mode rising edge CONVST conversion also initiated this point. BUSY output returns high after CONVST input goes high begins successive approximation routine. Once conversion been initiated another conversion start should attempted until full conversion cycle been completed. Figure shows taming diagram conversion start. applications where precise sampling critical, CONVST pulse generated from microprocessor line gated with decoded address (different from AD7878 address). Note that CONVST pulse width must minimum AD7878 cycles.
Figure Basic Read Operation
Basic Write Operation
basic write operation AD7878 status/control register consists bringing DMWR with ADD0 high. Internally these signals gated with provide internal REGISTER ENABLE signal (see Figure pulse width this REGISTER ENABLE signal effectively overlap between time DMWR pulse. This result shorter write pulse widths, data setup times data hold times than those given microprocessor. timing AD7878 timing diagram Figure therefore given with respect internal REGISTER ENABLE signal rather than DMWR signal.
Figure Conversion Start Timing Diagram
READ/WRITE OPERATIONS
AD7878 read/write operations consist reading from FIFO memory reading writing from status/control register. These operations controlled DMRD, DMWR ADD0 logic inputs. description these operations given following sections. addition basic read/write operations there extended read/write operation. This occur read/write operation occurs during CONVST pulse. This extended read/write intended with microprocessors that driven into WAIT state, scheme recommended applications where external timer controls CONVST input asynchronously microprocessor read/ write operations.
Basic Read Operation
Figure DMWR Internal Logic
Figure shows timing diagram basic read operation AD7878. DMRD going accesses data from either status/control register FIFO memory. read REV.
Figure Basic Write Operation
AD7878
Extended Read/Write Operation AD7878 DYNAMIC SPECIFICATIONS
described earlier, read/write operation AD7878 cause spurious on-chip transients. Should these transients occur while track/hold going from track hold mode, result incorrect value being held track/hold amplifier. Because CONVST input asynchronous capability, read/write operation could occur while CONVST low. AD7878 allows read/write operation occur facility disable three-state drivers that there data activity and, hence, transients while track/ hold goes from track hold. Writing logic (DISO) status/control register prevents output latches from being enabled while AD7878 BUSY signal low. microprocessor read/write operation occur during BUSY time, BUSY should gated with AD7878 this gated signal used stretch instruction cycle using DMACK (ADSP2100), READY (TMS32020) DTACK (68000). When CONVST goes low, AD7878 acknowledges bringing BUSY next rising edge With logic DB5, AD7878 data cannot enabled. read/write operation occurs, BUSY gated signal drives microprocessor into WAIT state, thereby extending read/write operation. BUSY goes high second rising edge after CONVST goes high. AD7878 data outputs enabled microprocessor released from WAIT state, allowing complete read/ write operation AD7878. microprocessor cycle time read/write operation extended CONVST pulse width plus periods worst case. This maximum length time which BUSY low. Assuming CONVST pulse width periods instruction cycle extended maximum. Figure shows timing diagram extended read operation. similar manner, write operation will extended occurs during CONVST pulse. processors that cannot forced into WAIT state, writing logic into status/control register allows output latches enabled while BUSY low. this case BUSY still goes before, would used stretch read/write cycle instruction cycle continues normal (see Figures
AD7878 specified 100% tested dynamic performance specifications rather than traditional specifications such Integral Differential Nonlinearity. These specifications provide information AD7878's effect spectral content input signal. Hence, parameters which AD7878 specified include SNR, Harmonic Distortion, intermodulation Distortion Peak Harmonics. These terms discussed more detail following sections.
Signal-to-Noise Ratio (SNR)
measured signal-to-noise ratio output ADC. signal magnitude fundamental. Noise nonfundamental signals (excluding half sampling frequency (fS/2). dependent upon number quantization levels used digitization process; more levels, smaller quantization noise. theoretical signal-to-noise ratio sine wave input given (6.02 1.76) where number bits. Thus ideal 12-bit converter, output spectrum from evaluated applying sine-wave signal very distortion input, which sampled sampling rate. Fast Fourier Transform (FFT) plot generated from which data obtained. Figure shows typical 2048 point plot AD7878KN with input signal sampling frequency kHz. obtained from this graph 72.6 should noted that harmonics included calculation.
Figure AD7878 Plot
Effective Number Bits
formula given relates number bits. Rewriting formula, (2), possible measure performance expressed effective number bits (N). effective number bits device calculated directly from measured SNR.
1.76 6.02
Figure Extended Read Operation
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AD7878
Figure shows typical plot effective number bits versus frequency AD7878KN with sampling frequency kHz. effective number bits typically falls between 11.7 11.85 corresponding figures 72.2 73.1
Figure Effective Number Bits Frequency
Harmonic Distortion
Figure AD7878 Plot
Histogram Plot
Harmonic Distortion ratio harmonics fundamental. AD7878, Total Harmonic Distortion (THD) defined
where amplitude fundamental amplitudes second sixth harmonic. also derived from plot output spectrum.
Intermodulation Distortion
When sine wave specified frequency applied input AD7878 several million samples taken, possible plot histogram showing frequency occurrence each 4096 codes. particular step wider than ideal width, then code associated with that step will accumulate more counts than code ideal step. Likewise, step narrower than ideal will have fewer counts. Missing codes easily seen histogram plot because missing code means zero counts particular code. Large spikes plot indicate large differential nonlinearity. Figure shows histogram plot AD7878KN with sampling frequency input frequency kHz. sine-wave input, perfect would produce cusp probability density function described equation:
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). Using CCIF standard, where input frequencies near input bandwidth used, second third order terms different significance. second order terms usually distanced frequency from original sine waves, while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental expressed dBs. Intermodulation distortion calculated using algorithm but, this case, input consists equal amplitude, distortion sine waves. Figure shows typical plot AD7878.
Peak Harmonic Spurious Noise
where peak amplitude sine wave probability occurrence voltage histogram plot Figure corresponds very well with this cusp shape. absence large spikes this plot indicates small dynamic differential nonlinearity (the largest spike plot represents less than error). AD7878 missing codes under these conditions since code records zero counts.
Peak harmonic spurious noise defined ratio value next largest component output spectrum FS/2 excluding value fundamental. Normally, value this specification will determined largest harmonic spectrum, parts where harmonics buried noise floor largest peak will noise peak. REV.
Figure AD7878 Histogram Plot
AD7878
CONVERSION TIMING ANALOG INPUT
track-and-hold AD7878 goes from track-to-hold mode rising edge CONVST, value this point value which will converted. However, conversion actually sorts next rising edge after CONVST goes high. CONVST goes high within approximately prior rising edge that edge will seen first edge conversion process, conversion will actually start until cycle later. result, conversion time (from CONVST FIFO update) will vary clock cycle depending relationship between CONVST conversion cycle normally consists cycles (assuming read/write operations) which corresponds conversion time. CONVST goes high within prior rising edge conversion time will consist cycles, i.e., 7.125 This effect does cause track/hold jitter.
INTERNAL REFERENCE
Figure shows AD7878 analog input. analog input range into input resistance typically designed code transitions occur midway between successive integer values (i.e., LSB, LSBs, LSBs FS-3/2 LSBs). output code complement binary with FS/4096 V/4096 1.46 ideal input/ output transfer function shown Figure
AD7878 on-chip temperature compensated buried Zener reference (see Figure that factory trimmed Internally, provides both reference bias required bipolar operation. reference output available (REF OUT) capable providing external load.
Figure AD7878 Analog Input
Figure Input/Output Transfer Function Figure AD7878 Reference Circuit
maximum recommended capacitance normal operation reference required external AD7878, should decoupled with resistor series with parallel combination tantalum capacitor ceramic capacitor. These decoupling components required remove voltage spikes caused internal operation AD7878.
TRACK-AND-HOLD AMPLIFIER
OFFSET FULL-SCALE ADJUSTMENT
most Digital Signal Processing (DSP) applications offset full-scale error have little effect system performance. Offset error always eliminated analog domain coupling. Full-scale error effect linear does cause problems long input signal within full dynamic range ADC. Some applications require that input signal span full analog input dynamic range and, accordingly, offset full-scale error will have adjusted zero. Where adjustment required, offset must adjusted before full-scale error. This achieved trimming offset driving analog input AD7878 while input voltage below ground. trim procedure follows: apply voltage -0.73 (-1/2 LSB) adjust offset voltage until output code flickers between 1111 1111 1111 0000 0000 0000. Gain error adjusted either first code transition (ADC negative full scale) last code transition (ADC positive full scale). trim procedures both cases follows:
track-and-hold amplifier analog input AD7878 allows accurately convert input sine wave peak-peak amplitude 12-bit accuracy. input bandwidth track/hold amplifier much greater than Nyquist rate even when operated minimum conversion time. cutoff frequency occurs typically kHz. track/hold amplifier acquires input signal 12-bit accuracy less than operation track/hold amplifier transparent user. track/hold amplifier goes from tracking mode hold mode start conversion rising edge CONVST returns track mode conversion.
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AD7878
Positive Full-Scale Adjust
Apply voltage 2.9978 (FS/2 LSBs) Adjust until output code flickers between 0111 1111 1110 0111 1111 1111.
Negative Full-Scale Adjust
Apply voltage -2.9993 (-FS/2 LSB) adjust until output code flickers between 1000 0000 0000 1000 0000 0001.
Figure AD7878-TMS32020 Interface
Figure AD7878 Full-Scale Adjust Circuit
MICROPROCESSOR INTERFACING
AD7878 high speed timing allows direct interfacing processors. complexity AD7878 internal logic, only synchronous interfacing allowed. This means that clock must same derivative processor clock. Suitable processor interfaces shown Figures
interfaces ADSP-2100 TMS32020 gate AD7878 BUSY provide signal which drives processor into wait state read/write operation attempted while track/hold amplifier going from track hold mode. This avoids digital feedthrough analog circuitry. TMS32020 does have separate outputs drive AD7878 DMWR DMRD inputs. These generated from processor STRB outputs with addition some logic gates.
three interfaces external timer conversion control, allowing sample analog input asynchronously microprocessor. AD7878 ALFL output interrupts processor when FIFO preprogrammed word count reached. processor then reads conversion results from AD7878 internal FIFO memory.
Figure AD7878-TMS32020 Interface
AD7878-M CC8000
Figure AD7878-ADSP-2700 Interface
This interface also uses external timer conversion control described previous three interfaces. discussed separately because needs extra logic nature interrupts. MC68000 eight levels external interrupt. When interrupting this processor these levels encoded onto IPL2-IPL0 inputs. This achieved with 74148 encoder Figure (interrupt Level taken example purposes only). MC68000 places this interrupt level address bits start interrupt service routine. Additional logic used decode this interrupt level address FC2-FC0 outputs generate signal MC68000. This results autovectored interrupt, start address service routine must loaded into appropriate auto vector location during initialization. further information 68000 interrupts consult 68000 User's Manual. -11-
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AD7878
MC68000 outputs used generate separate DMWR DMRD inputs AD7878. with three interfaces previously described, WAIT states inserted read/write operation attempted while track/hold amplifier going from track hold mode. THROUGHPUT RATE AD7878 maximum specified throughput rate (sample rate) kHz. This worst-case test condition specifications apply reduced sampling rates, provided that Nyquist criterion obeyed. throughput rate must take into account CONVST pulse width, conversion time track/hold amplifier acquisition time. time required each these tasks shown Table selection processors. Since clock synchronized microprocessor dock, conversion time depends microprocessor used. addition, time must allowed reading data from AD7878. this task performed during track/ hold amplifier acquisition period, then does impact overall throughput rate. However, read operations occur during conversion, they stretch conversion time reduce track/hold amplifier acquisition time. track/hold amplifier requires minimum operate specification. time required read from AD7878 depends number FIFO memory locations read software organization. example, consider application using ADSP-2100 AD7878 with throughput rate kHz. time required CONVST pulse conversion 7.375 This leaves 2.625 track/hold acquisition time reading (both operations occurring parallel). ADSP-2100, when operating from clock, instruction cycle interrupt response time This allows adequate time perform read operations within time budget allowed.
Table AD7878 Throughput Rate
CONVST Pulse Width Number Clock Cycles ADSP-21001 TMS320102 TMS320202
Conversion Time 7.125 11.14 11.14
Acquisition Time NonApplicable
Figure AD7878-MC68000 Interface
Typical AD7878 Microprocessor Operating Sequence
After power-up reset, status/control register initialized writing AD7878. This enables ALFL output required microprocessor interrupt sets effective word length FIFO memory. processor executes main body program while waiting interrupt. This interrupt will occur when preprogrammed number samples collected FIFO memory. interrupt service routine first interrogates DB5(FOOR) status/control register determine sample FIFO memory range. data samples valid, then program proceeds read FIFO memory. other hand, least sample range, then overrange routine called. There many actions that taken range routine, selection which application dependent. option ignore current samples residing FIFO memory, reinitialize status/control register return main body program. Another option check individual range status each word FIFO memory discard invalid ones. underrange overrange status each word also determined analog input adjusted accordingly before returning main program. Note: there need check out-of-range status analog input always assured within range.
NOTES ADSP-2100 Clock Frequency MHz. TMS320XX Clock Frequency MHz.
APPLICATION HINTS
Good printed circuit board (PCB) layout important overall circuit design itself achieving high speed performance. AD7878 required make decisions size 1.465 achieve this, designer conscious noise both itself preceding analog circuitry. Switching mode power supplies recommended switching spikes will feed through comparator, causing noisy code transitions. Other concerns ground loops digital feedthrough from microprocessors. These factors influence ADC, proper layout that minimizes these effects essential best performance.
LAYOUT HINTS
Ensure that layout printed circuit board digital analog signal lines separated much possible. Take care digital track alongside analog signal track. Guard (screen) analog input with AGND. REV.
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AD7878
Establish single point analog ground (star ground) separate from logic system ground (AGND) dose possible AD7878, shown Figure Connect other grounds (AD7878 DGND) this single analog ground point. connect other digital grounds this analog ground point. impedance analog digital power supply common returns essential noise operation ADC, make foil width these tracks wide possible. ground planes minimizes impedance paths also guards analog circuitry from digital noise. circuit layouts Figures have both analog digital ground planes, which kept separated only joined together AD7878 AGND pin.
NOISE
rupts labelled EIRQ3 EIRQ0. AD7878 ALFL output connects EIRQ0. AD7878 ADSP-2100 data lines aligned left justified data transfer. 26-way connector contains necessary contacts both TMS32010 TMS32020. There switches data acquisition board that must enable appropriate interface configuration (see Table III). interface connections TMS32010/32020 signal contact numbers shown Table Figure Note AD7878 input must decoded from address prior AD7878 evaluation board TMS320XX interfaces. Connections analog input (VIN) CONVST input made sockets labelled SKT1 SKT2 silkscreen. CONVST input derived from either microprocessor clock, effects clock noise coupling will reduced.
Table III. AD7878 Switch Settings
Keep input signal leads signal return leads from AGND (Pin short possible minimize input noise coupling. applications where this possible, shielded cable between source ADC. Reduce ground circuit impedance much possible since potential difference grounds between signal source appears error voltage series with input signal.
SWITCH SETTING Microprocessor ADSP-2100 TMS32010 TMS32020
POWER SUPPLY CONNECTIONS
Figure Power Supply Grounding Practice
DATA ACQUISITION BOARD
requires analog supplies digital supply. Connections analog supplies made directly shown silk screen Figure connections labelled range both these supplies Connection digital supply made through either microprocessor connectors. analog power supplies required AD7878 generated from voltage regulators power supply inputs (IC3 Figure 23).
COMPONENT LIST
Figure shows AD7878 data acquisition circuit that will interface directly either ADSP-2100, TMS32010 TMS32020. corresponding printed circuit board (PCB) layout silkscreen shown Figures only additional component required full data acquisition system antialiasing filter. There component grid provided near analog input which used such filter other conditioning circuitry. facilitate this option, wire link (labelled PCB) required analog input track. This link connects input signal either component grid directly buffer amplifier driving AD7878 analog input. Microprocessor connections made either ways: 96-contact ROW) Eurocard connector. 26-contact ROW) connector. 96-contact Eurocard connector directly compatible with ADSP-2100 Evaluation Board Prototype Expansion Connector. expansion connector ADSP-2100 eight decoded drip enable outputs labelled ECE8 ECE1. ECE6 used drive AD7878 input data acquisition board. avoid selecting onboard sockets same time, ADSP-2100 board must removed. addition, expansion connector ADSP-2100 four interREV.
IC5* IC6* C11, C13, C12, C14, R1*, SKT1, SKT2 SKT3 SKT4
AD711 AD7878 Analog-to-Digital Converter MC78L05 Regulator MC79L05 Regulator 74HC00 Quad NAND Gate 74HC04 Inverter 74HC02 Quad Gate Single Pole Double Throw Double Pole Double Throw Wire Link Analog Input Capacitors Capacitors Resistors Sockets 26-Contact Row) Connector 96-Contact Row) Eurocard Connector
*Not required ADSP-2100 Interface.
-13-
AD7878
Figure Data Acquisition Circuit Using AD7878
Figure Silkscreen Figure
-14-
REV.
AD7878
Figure Component Side Layout Figure
Figure Solder Side Layout Figure
REV.
-15-
AD7878
Table TMS32010/TMS32020 Interface Connections 28-Pin Cerdip (Q-28)
Contact
Signal Connect Mnemonic STRB DMRD DMWR READY RESET ALFL ADD0 DB10 DB11
TMS32010 Signal RESET CLKOUT
TMS32020 Signal STRB READY RESET CLKOUT2
28-Pin Ceramic (D-28)
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Terminal PLCC (P-28A)
28-Pin Plastic (N-28)
NOTE Analog Devices reserves right ship either cerdip ceramic hermetic packages.
-16-
REV.
PRINTED U.S.A.
28-Terminal LCCC (E-28A)
C1204a-1-5/97

FEATURES Complete with Interface, Comprising: Track/Hold Amplifier wit

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