CONFIGURATIONS 6-Lead Suffix) FEATURES Single Supply Operation: +

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CONFIGURATIONS 6-Lead Suffix) FEATURES Single Supply Operation: +

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CMOS Single Supply Rail-to-Rail Input/Output Operational Amplifiers with Shutdown AD8591/AD8592/AD8594
CONFIGURATIONS 6-Lead Suffix)
FEATURES Single Supply Operation: +2.5 High Output Current: Extremely Shutdown Supply Current: Supply Current: A/Amp Wide Bandwidth: Slew Rate: Phase Reversal Very Input Bias Current High Impedance Outputs When Shutdown Mode Unity Gain Stable APPLICATIONS Mobile Communication Handset Audio Audio PCMCIA/Modem Line Driving Battery Powered Instrumentation Data Acquisition ASIC Input Output Amplifier Display Reference Level Driver GENERAL DESCRIPTION
AD8591
10-Lead SOIC Suffix)
AD8592
(Not Scale)
16-Lead Narrow SOIC Suffix)
AD8591, AD8592 AD8594 single, dual quad rail-to-rail input output single supply amplifiers featuring output drive current power saving shutdown mode. AD8592 includes independent shutdown function each amplifier. When both amplifiers shutdown mode total supply current reduced less than AD8591 AD8594 include single master shutdown function that reduces total supply current less than amplifier outputs high impedance state when shutdown mode. These amplifiers have very input bias currents, making them suitable integrators diode amplification. Outputs stable with virtually capacitive load. Supply current less than amplifier active mode. Applications these amplifiers include audio amplification portable computers, portable phone headsets, sound ports, sound cards set-top boxes. AD859x family capable driving heavy capacitive loads such panel reference levels. ability swing rail-to-rail both input output enables designers buffer CMOS DACs, ASICs other wide output swing devices single supply systems. AD8591, AD8592 AD8594 specified over industrial (-40°C +85°C) temperature range. AD8591, single, available tiny 6-lead package. AD8592, dual, available 10-lead µSOIC surface mount package. AD8594, quad, available 16-lead narrow SOIC 16-lead TSSOP packages. REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
AD8594
VIEW (Not Scale)
CONNECT
16-Lead TSSOP Suffix)
AD8594
CONNECT
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
ELECTRICAL CHARACTERISTICS +2.7
+1.35 unless otherwise noted)
+2.7 Units V/mV µV/°C fA/°C fA/°C V/µs Degrees nV/Hz nV/Hz pA/Hz
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Output Current Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier Supply Current Shutdown Mode
Symbol
Conditions
-40°C +85°C -40°C +85°C -40°C +85°C CMRR IOUT ZOUT PSRR ISD1 ISD2 SHUTDOWN INPUTS Logic High Voltage Logic Voltage Logic Input Current DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density
Specifications subject change without notice.
+2.7 +0.3 +2.4
+2.61
-40°C +85°C -40°C +85°C MHz, +2.5 -40°C +85°C Amplifiers Shut Down -40°C +85°C Amplifier Shut Down (AD8592) Amplifier Shut Down (AD8592) -40°C +85°C -40°C +85°C -40°C +85°C 0.01%
+2.55 +2.5
1.25
VINH VINL
+1.6 +0.5 0.05
kHz,
REV.
AD8591/AD8592/AD8594 ELECTRICAL CHARACTERISTICS +5.0
+2.5 unless otherwise noted)
Units V/mV µV/°C fA/°C fA/°C V/µs Degrees nV/Hz nV/Hz pA/Hz
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Output Current Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier Supply Current-Shutdown Mode
Symbol
Conditions
-40°C +85°C -40°C +85°C -40°C +85°C CMRR IOUT ZOUT PSRR ISD1 ISD2 SHUTDOWN INPUTS Logic High Voltage Logic Voltage Logic Input Current DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density
Specifications subject change without notice.
+0.5 +4.5 -40°C +85°C
+4.94
-40°C +85°C -40°C +85°C MHz, +2.5 -40°C +85°C Amplifiers Shut Down -40°C +85°C Amplifier Shut Down (AD8592) Amplifier Shut Down (AD8592) -40°C +85°C -40°C +85°C -40°C +85°C Distortion 0.01%
+4.9 +4.85
1.25 1.75
VINH VINL
+2.4 +0.8 0.05
kHz,
REV.
AD8591/AD8592/AD8594
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Input Voltage Differential Input Voltage Output Short Circuit Duration Observe Derating Curves Storage Temperature Range Packages -65°C +150°C Operating Temperature Range AD8591/AD8592/AD8594 -40°C +85°C Junction Temperature Range Packages -65°C +150°C Lead Temperature Range (Soldering, sec) +300°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. supplies less than differential input voltage limited supplies.
Package Type 6-Lead SOT-23 (RT) 10-Lead µSOIC (RM) 16-Lead SOIC 16-Lead TSSOP (RU)
Units °C/W °C/W °C/W °C/W
NOTE specified worst case conditions, i.e., specified device socket surface mount packages.
ORDERING GUIDE
Model AD8591ART AD8592ARM AD8594AR AD8594ARU
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Package Description 6-Lead SOT-23 10-Lead µSOIC 16-Lead SOIC 16-Lead TSSOP
Package Option RT-6 RM-10 R-16A RU-16
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD8591/AD8592/AD8594 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
Typical Performance Characteristics
+2.7V
OUTPUT VOLTAGE
SUPPLY CURRENT/AMPLIFIER
0.90
0.85 0.80 0.75 0.70 0.65 0.60 +2.7V 0.55 0.50
OUTPUT VOLTAGE
SOURCE SINK
SOURCE
SINK
0.01
LOAD CURRENT
0.01
LOAD CURRENT
TEMPERATURE
Figure Output Voltage Supply Rail Load Current
Figure Output Voltage Supply Rail Load Current
Figure Supply Current Amplifier Temperature
REV.
AD8591/AD8592/AD8594
SUPPLY CURRENT/AMPLIFIER
INPUT OFFSET VOLTAGE
+2.5V
+2.7V, VS/2
INPUT BIAS CURRENT
TEMPERATURE TEMPERATURE
0.75
1.25 1.75 2.25 2.75 SUPPLY VOLTAGE Volts
Figure Supply Current Amplifier Supply Voltage
Figure Input Offset Voltage Temperature
Figure Input Bias Current Temperature
INPUT OFFSET CURRENT
+2.7V,
INPUT BIAS CURRENT
GAIN
TEMPERATURE
COMMON-MODE VOLTAGE Volts
100k FREQUENCY
100M
Figure Input Offset Current Temperature
Figure Input Bias Current Common-Mode Voltage
Figure Open-Loop Gain Phase Frequency
GAIN
LOAD
PHASE SHIFT Degrees
+2.7V 2.5V 4.9V
OUTPUT SWING
OUTPUT SWING
100k FREQUENCY
100M
100k FREQUENCY
100k FREQUENCY
Figure Open-Loop Gain Phase Frequency
Figure Closed-Loop Output Voltage Swing Frequency
Figure Closed-Loop Output Voltage Swing Frequency
REV.
PHASE SHIFT Degrees
+2.7V LOAD
AD8591/AD8592/AD8594
+2.5V
IMPEDANCE
CMRR
PSRR
+PSRR
PSRR
100k FREQUENCY
100M
100k FREQUENCY
100k FREQUENCY
Figure Closed-Loop Output Impedance Frequency
Figure Common-Mode Rejection Ratio Frequency
Figure Power Supply Rejection Ratio Frequency
SMALL SIGNAL OVERSHOOT PSRR +PSRR
SMALL SIGNAL OVERSHOOT
+2.5V
PSRR
100k FREQUENCY
CAPACITANCE
CAPACITANCE
Figure Power Supply Rejection Ratio Frequency
Figure Small Signal Overshoot Load Capacitance
Figure Small Signal Overshoot Load Capacitance
1.35V
20mV/DIV
20mV/DIV
1.35V 50mV 300pF
2.5V 50mV 300pF
500mV
500ns
ns/DIV
ns/DIV
Figure Small Signal Transient Response
Figure Small Signal Transient Response
Figure Large Signal Transient Response
REV.
AD8591/AD8592/AD8594
CURRENT NOISE DENSITY
2.5V
2.5V
500mV
500ns
0.01
FREQUENCY
100k
Figure Large Signal Transient Response
Figure Phase Reversal
Figure Current Noise Density Frequency
1000 FREQUENCY 1kHz
1000
QUANTITY Amplifiers
V/DIV
V/DIV
FREQUENCY 10kHz
+2.7V +1.35V
MARKER
MARKER 25.9 INPUT OFFSET VOLTAGE
Figure Voltage Noise Density Frequency
Figure Voltage Noise Density Frequency
Figure Input Offset Voltage Distribution
QUANTITY Amplifiers
+2.5V
INPUT OFFSET VOLTAGE
Figure Input Offset Voltage Distribution
REV.
AD8591/AD8592/AD8594
AD8591/AD8592/AD8594 APPLICATION SECTION Theory Operation Output Phase Reversal
AD859x family amplifiers CMOS, high output drive, rail-to-rail input output single supply amplifiers designed cost high output current drive. parts include power saving shutdown function making AD8591/AD8592/AD8594 amps ideal portable multimedia telecom applications. Figure shows simplified schematic AD8591/AD8592/ AD8594 amplifier. input differential pairs, consisting n-channel pair (M1-M2) p-channel pair (M3-M4), provide rail-to-rail input common-mode range. outputs input differential pairs combined compound folded-cascode stage, which drives input second differential pair gain stage. outputs second gain stage provide gate voltage drive rail-to-rail output stage. rail-to-rail output stage consists M16, which configured complementary common-source configuration. with rail-to-rail output amplifier, gain output stage, thus open-loop gain amplifier, dependent load resistance. Also, maximum output voltage swing directly proportional load current. difference between maximum output voltage supply rails, known dropout voltage, determined AD8591/AD8592/ AD8594 output transistors' on-channel resistance. output dropout voltage given Figure Figure
AD8591/AD8592/AD8594 immune output voltage phase reversal with input voltage within supply voltages device. However, either device's inputs exceeds +0.6 outside supply rails, output could exhibit phase reversal. This protection diodes becoming forward biased, thus causing polarity input terminals device switch. technique recommended Input Overvoltage Protection section should applied applications where possibility input voltages exceeding supply voltages exists.
Output Short Circuit Protection
achieve high output current drive rail-to-rail performance, outputs AD859x family have internal short circuit protection circuitry. Although these amplifiers designed sink source much output current, shorting output directly positive supply could damage destroy device. protect output stage, maximum output current should limited placing resistor series with output amplifier shown Figure output current limited. minimum value found from Equation
M337
single supply application, should least Because inside feedback loop, VOUT affected. tradeoff using slight reduction output voltage swing under heavy output current loads. will also increase effective output impedance amplifier where output impedance device.
M340
AD8592
VOUT
Figure Output Short Circuit Protection
Power Dissipation
*NOTE: CURRENT SOURCES SHUTDOWN MODE
Figure AD8591/AD8592/AD8594 Simplified Schematic
Although AD859x family amplifiers able provide load currents proper attention should given exceeding maximum junction temperature device. equation finding junction temperature given
PDISS
Input Voltage Protection Although shown simplified schematic, protection diodes connected from each input each power supply rail. These diodes normally reverse biased, will turn either input voltage exceeds either supply rail more than +0.6 Should this condition occur, input current should limited less than This done placing resistor series with input(s). minimum resistor value should
Where AD859x junction temperature PDISS AD859x power dissipation AD859x junction-to-ambient thermal resistance package; ambient temperature circuit
REV.
AD8591/AD8592/AD8594
application, absolute maximum junction temperature must limited +150°C. this junction temperature exceeded, device could suffer premature failure. output voltage output current phase, example, with purely resistive load, power dissipated AD859x found
50mV
47nF LOAD ONLY
PDISS LOAD VOUT
SNUBBER CIRCUIT
Where
ILOAD AD859x output load current AD859x supply voltage; VOUT output voltage
50mV
calculating power dissipation device using thermal resistance value given package type, maximum allowable ambient temperature application found using Equation
Capacitive Loading
Figure Snubber Network Reduces Overshoot Ringing Caused from Driving Heavy Capacitive Loads
optimum values snubber network should determined empirically based size capacitive load. Table shows sample snubber network values given load capacitance.
Table Snubber Networks Large Capacitive Loads
AD859x exhibits excellent capacitive load driving capabilities drive directly. Although device stable with large capacitive loads, there decrease amplifier bandwidth capacitive load increases. Figure shows graph AD8592 unity gain bandwidth under various capacitive loads.
2.5V
Load Capacitance (CL) 0.47
Snubber Network (RS,
PC-98 Compliant Headphone/Speaker Amplifier
BANDWIDTH
Because high output current performance shutdown feature, AD8592 makes excellent amplifier driving audio output jack computer application. Figure shows AD8592 interfaced with AC97 codec drive headphones speakers.
U1-A LEFTOUT 100k
0.01
CAPACITIVE LOAD
Figure Unity Gain Bandwidth Capacitive Load
AD1881 (AC97)
RIGHTOUT NOTE: ADDITIONAL PINS OMITTED CLARITY U1-B
When driving heavy capacitive loads directly from AD859x output, snubber network used improve transient response. This network consists series connected from amplifier's output ground, placing parallel with capacitive load. configuration shown Figure Although this network will increase bandwidth amplifier, will significantly reduce amount overshoot, shown Figure
AD8592
Figure PC-98 Compliant Headphone/Line Amplifier
AD8592
100mV 47nF
VOUT
When headphones plugged into jack, normalizing contacts disconnect from audio contacts. This allows voltage AD8592 shutdown pins pulled activating amplifiers. With plug output jack, shutdown voltage pulled through voltage divider. This powers AD8592 down when needed, saving current from power supply battery.
Figure Configuration Snubber Network Compensate Capacitive Loads
REV.
AD8591/AD8592/AD8594
gain required from output amplifier, four additional resistors should added shown Figure gain AD8592
Combined Microphone Speaker Amplifier Cellphone Portable Headsets
U1-A 100k
dual amplifiers AD8592 make efficient design interfacing with headset containing microphone speaker. Figure demonstrates simple method constructing interface codec.
2.2k U1-A SPEAKER JACK 100k U1-B FROM CODEC MONO LEFT OUT) (RIGHT OUT) (OPTIONAL) VREF FROM CODEC 100k CODEC
LEFTOUT
VREF
AD1881 (AC97)
RIGHTOUT
U1-B
AD8592
AD8592
+6dB WITH VALUES SHOWN
Figure Speaker/Mic Headset Amplifier Circuit
NOTE: ADDITIONAL PINS OMITTED CLARITY
Figure PC-98 Compliant Headphone/Line Amplifier With Gain
Input coupling capacitors required either circuit reference voltage supplied from AD1881. help protect AD8592 output case output jack headphone wires accidentally shorted ground. output coupling capacitors block current from headphones create high-pass filter with corner frequency
U1-A used microphone preamplifier, where gain preamplifier R3/R2. used bias electret microphone blocks voltages from amplifier. U1-B speaker amplifier, gain R5/R4. stereo output, should added, equal value Using same principle described previous section, normalizing contact microphone/speaker jack used AD8592 into shutdown when headset plugged AD8592 shutdown inputs also controlled with CMOS compatible logic, allowing microphone speaker muting desired.
Inexpensive Sample-and-Hold Circuit
Where resistance headphones.
independent shutdown control each amplifier AD8592 allows degree flexibility circuit design. particular application which this feature useful designing sample-and-hold circuit data acquisition. Figure shows schematic simple, extremely effective sample-and-hold circuit using single AD8592 capacitor.
U1-B
U1-A
SAMPLE HOLD OUTPUT
SAMPLE CLOCK
AD8592
Figure Efficient Sample-and-Hold Circuit
-10-
REV.
AD8591/AD8592/AD8594
U1-A amplifier configured unity gain buffer driving capacitor. input signal connected noninverting input, while sample clock controls shutdown that amplifier. When sample clock high, U1-A amplifier active output follows VIN. Once sample clock goes low, U1-A shuts down with output amplifier going high impedance state, holding voltage capacitor. U1-B amplifier used unity gain buffer prevent loading Because input bias current U1-B CMOS input stage high impedance state U1-A output shutdown, there very little voltage droop from during Hold period. This circuit used with sample frequencies high below Even lower voltage droop achieved very sample rates increasing value
Direct Access Arrangement PCMCIA Modems (Telephone Line Interface) Single Supply Differential Line Driver
Figure shows single supply differential line driver circuit that drive load with less than 0.7% distortion from with input signal single supply. design uses AD8594 mimic performance fully balanced transformer based solution. However, this design occupies much less board space while maintaining distortion operate down Like transformer based design, either output shorted ground unbalanced line driver applications without changing circuit gain
AD8592 GAIN
100k
Figure illustrates transmit/receive telephone line interface systems. allows full duplex transmission signals transformer-coupled line differential manner. Amplifier provides gain that adjusted meet modem output drive requirements. Both configured apply largest possible signal single supply transformer. Because AD8594's high output current drive dropout voltages, largest signal available single supply approximately into transmission system. Amplifier configured difference amplifier reasons: prevents transmit signal from interfering with receive signal extracts receive signal from transmission line amplification Amplifier A4's gain adjusted same manner A1's meet modem's input signal requirements. Standard resistor values permit (Single In-line Package) format resistor arrays. Couple this with AD8594 16-lead TSSOP SOIC footprint, this circuit offers compact, cost effective solution.
GAIN ADJUST
100k
SET: R10, SET: R12,
Figure Noise, Single Supply Differential Line Driver
common-mode output voltage equal half supply voltage. used couple input signal omitted input's voltage equal half supply voltage. circuit also configured provide additional gain desired. gain circuit
VOUT
9.09k
TELEPHONE LINE MIDCOM 671-8005 6.2V 6.2V
TRANSMIT
Where:
VOUT VO2, and,
SHUTDOWN
14.3k
GAIN ADJUST
RECEIVE
AD8592 AD8592
Figure Single Supply Direct Access Arrangement PCMCIA Modems
REV.
-11-
AD8591/AD8592/AD8594
SPICE Model AD8591/AD8592/AD8594 Amplifier
SPICE model AD8591/AD8592/AD8594 amplifier more realistic computer simulation macro-models available, providing high degree realism with respect characteristics actual amplifier. This model, shown Listing based typical values device downloaded from Analog Devices' Internet site www.analog.com. model uses common source output stage provide railto-rail performance. This allows realistic simulation openloop gain dependency load resistance well maximum output voltage versus output current. differential pairs used input stage model, simulating rail-to-rail input stage AD8591/AD8592/AD8594 amplifier. voltage source establishes input offset voltage also used simulate common-mode rejection power supply rejection, input voltage noise characteristics model. addition, used help open-loop gain gain-bandwidth product model.
number secondary characteristics also accurately portrayed SPICE model. Flicker noise accurately modeled with corner frequency through terms input stage transistors. used input section create secondary poles achieve accurate phase margin characteristic model. AD8591/AD8592/AD8594 shutdown circuitry included model. Switches through deactivate circuitry shutdown mode. logic threshold shutdown circuitry accurately modeled through VSWITCH model parameters near listing. active supply current versus supply voltage also modeled through voltage-controlled current source GSY. Characteristics this model based typical values AD8591/AD8592/AD8594 amplifier +27°C. model's characteristics optimized specifically +27°C, lose accuracy different simulation temperatures.
-12-
REV.
AD8591/AD8592/AD8594
Listing AD859x SPICE Macro-Model AD8592 SPICE Macro-Model Typical Values 9/98, Ver. ADSC Copyright 1998 Analog Devices Refer "README.DOC" file License Statement. this model indicates your acceptance terms provisions License Statement. Node Assignments noninverting input inverting input positive supply negative supply output shutdown .SUBCKT AD8592 INPUT STAGE L=0.8E-6 W=125E-6 L=0.8E-6 W=125E-6 2E-12 100E-6 L=0.8E-6 W=125E-6 L=0.8E-6 W=125E-6 2E-12 100E-6
POLY(3) (21,98) (73,98) (61,0) +1E-3 2.5E-12 (82,98) SOPEN (98,82) SCLOSE (82,98) SOPEN (98,82) SCLOSE CMRR=64dB, ZERO 20kHz ECM1 POLY(2) (1,98) (2,98) RCM1 79.6E3 CCM1 100E-12 RCM2 PSRR=80dB, ZERO 200Hz RPS1 RPS2 CPS1 1E-5
REV. -13-
AD8591/AD8592/AD8594
CPS2 1E-5 EPSY POLY(2) (70,0) (0,71) RPS3 1.59E6 CPS3 500E-12 RPS4 INTERNAL VOLTAGE REFERENCE EREF POLY(2) (99,0) (50,0) POLY(1) (99,50) 20E-6 10E-7 SHUTDOWN SECTION (80,50) 1E-9 VOLTAGE NOISE REFERENCE 30nV/rt(Hz) 16.45E-3 GAIN STAGE POLY(2) (4,6) (10,11) 2.19E-5 +2.19E-5 13E6 5E-12 (98,82) SCLOSE OUTPUT STAGE L=0.8E-6 W=16E-3 L=0.8E-6 W=16E-3 POLY(1) (98,30) 1.06 POLY(1) (30,98) 1.05 10E3 10E3 (98,82) SCLOSE (98,82) SCLOSE MODELS .MODEL PMOS (LEVEL=2,KP=20E-6,VTO=-0.7, LAMBDA=0.01,AF=1,KF=1E-31) .MODEL NMOS (LEVEL=2,KP=20E-6,VTO=0.7, LAMBDA=0.01,AF=1,KF=1E-31) .MODEL PMOS (LEVEL=2,KP=8E-6,VTO=-1, LAMBDA=0.067) .MODEL NMOS (LEVEL=2,KP=13.4E-6,VTO=1, LAMBDA=0.067) .MODEL SOPEN VSWITCH(VON=2.4,VOFF=0.8, RON=10,ROFF=1E9) .MODEL SCLOSE VSWITCH(VON=-0.8,VOFF=-2.4, RON=10,ROFF=1E9) .MODEL D(IS=1E-14) .ENDS AD8592
-14-
REV.
AD8591/AD8592/AD8594
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
0.122 (3.10) 0.106 (2.70)
0.124 (3.15) 0.112 (2.84)
0.071 (1.80) 0.059 (1.50)
0.118 (3.00) 0.098 (2.50)
0.124 (3.15) 0.112 (2.84)
0.199 (5.05) 0.187 (4.75)
0.037 (0.95) 0.075 (1.90) 0.051 (1.30) 0.035 (0.90) 0.059 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35)
0.0197 (0.50) 0.122 (3.10) 0.110 (2.79) 0.043 (1.09) 0.037 (0.94) 0.016 (0.41) 0.006 (0.15) SEATING 0.011 (0.28) PLANE 0.003 (0.08) 0.022 (0.56) 0.021 (0.53) 0.120 (3.05) 0.112 (2.84)
0.038 (0.97) 0.030 (0.76)
0.006 (0.15) 0.002 (0.05)
16-Lead Thin Shrink Small Outline (RU-16)
0.201 (5.10) 0.193 (4.90)
0.1574 (4.00) 0.1497 (3.80)
16-Lead Narrow Body (R-16A)
0.3937 (10.00) 0.3859 (9.80)
0.177 (4.50) 0.169 (4.30)
0.256 (6.50) 0.246 (6.25)
0.2440 (6.20) 0.2284 (5.80)
0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090)
0.0500 SEATING (1.27) PLANE
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
SEATING PLANE
0.0256 (0.65)
0.028 (0.70) 0.020 (0.50)
REV.
-15-
PRINTED U.S.A.
C3456a-0-2/99
6-Lead (RT-6)
10-Lead SOIC (RM-10)

CONFIGURATIONS 6-Lead Suffix) FEATURES Single Supply Operation: +

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