2758.4 Digital Filter HSP43881 video speed Digital Filter (D

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2758.4 Digital Filter HSP43881 video speed Digital Filter (D

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HSP43881
2758.4
Digital Filter
HSP43881 video speed Digital Filter (DF) designed efficiently implement vector operations such digital filters. comprised eight filter cells cascaded internally shift output stage, single integrated circuit. Each filter cell contains 8-bit multiplier, three decimation registers 26-bit accumulator. output stage contains additional 26-bit accumulator which contents filter cell accumulator output stage accumulator shifted right bits. HSP43881 maximum sample rate 30MHz. effective multiply accumulate (mac) rate 240MHz. HSP43881 configured process expanded coefficient word sizes. Multiple cascaded larger filter lengths without degrading sample rate single process larger filter lengths less than 30MHz with multiple passes. architecture permits processing filter lengths over 1000 taps with guarantee overflows. practice, most filter coefficients less than 1.0, making even larger filter lengths possible. provides 8-bit unsigned two's complement arithmetic, independently selectable coefficients signal data. Each filter cell contains three resampling decimation registers which permit output sample rate reduction rates 1/2, input sample rate. These registers also provide capability perform operations such matrix multiplication spatial correlations/convolutions image processing applications.
Features
Eight Filter Cells 0MHz 30MHz Sample Rate 8-Bit Coefficients Signal Data 26-Bit Accumulator Stage Filter Lengths Over 1000 Taps Expandable Coefficient Size, Data Size Filter Length Decimation
Applications
Filters Radar/Sonar Adaptive Filters Echo Cancellation Complex Multiply-Add Sample Rate Converters
Ordering Information
PART NUMBER HSP43881JC-20 HSP43881JC-25 HSP43881JC-30 HSP43881GC-20 HSP43881GC-25 HSP43881GC-30 TEMP. RANGE (oC) PACKAGE PLCC PLCC PLCC PKG. N84.1.15 N84.1.15 N84.1.15 G85.A G85.A G85.A
Block Diagram
DIENB CIENB DCMO ERASE TCCI CIN0 RESET ADR0 RESET SHADD SENBL SENBH DIN0 DIN7 FILTER CELL ADR0, ADR1, ADR2 OUTPUT STAGE SUM0 FILTER CELL FILTER CELL FILTER CELL FILTER CELL FILTER CELL FILTER CELL FILTER CELL TCCO COUT0 COENB
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
HSP43881 Pinouts
GRID ARRAY (PGA) VIEW, PINS DOWN
DIN6 DIN3 DIN0 TCCI CIN6 CIN4
COENB
RESET DIN7
COUT7 TCCO ERASE ALIGN
DIN1
DIN2 CIENB CIN7
COUT5 COUT6
DIENB DIN5
DIN4
CIN5
CIN3
COUT3 COUT4
CIN2
COUT1
COUT2
CIN1
CIN0 SENBL
COUT0 SHADD
SUM0
ADR2 DCM0
SUM1 SUM3 SUM2
ADR1
ADR0 SUM25 SUM20 SUM17 SUM16
SUM5 SUM4 SUM7
SENBH SUM24
SUM19
SUM15 SUM12 SUM10 SUM8 SUM6
DCM1 SUM23 SUM22 SUM21 SUM18 SUM14
SUM13
SUM11 SUM9
HSP43881 VIEW, PINS
DCM1 SENBH ADR1 ADR2 COUT1 COUT3 COUT5 COUT6 COENB RESET DIN7 DIN6 DIN3 DIN0 CIN8 COUT7 COUT8 ERASE DIN8 DIN1 DIN2 CIENB CIN7 CIN6 CIN4 ALIGN DIENB DIN5 DIN4 CIN5 CIN3 COUT4 CIN2 COUT2 CIN1 CIN0 SENBL COUT0 SHADD SUM0 DCM0 SUM1 SUM3 SUM2 ADR0 SUM5 SUM4 SUM25 SUM20 SUM17 SUM16 SUM7 SUM24 SUM19 SUM15 SUM12 SUM10 SUM8 SUM6 SUM23 SUM22 SUM21 SUM18 SUM14 SUM13 SUM11 SUM9
HSP43881 Pinouts
(Continued) LEAD PLCC PACKAGE BOTTOM VIEW
SHADD SENBH ADDR0 ADDR1 ADDR2 COUT0 COUT1 COUT2 COUT3 COUT4 COUT5 SUM24 SUM25 DCM1 DCM0
SUM23 SUM22 SUM21 SUM20 SUM19 SUM18 SUM17 SUM16 SUM15 SUM14 SUM13 SUM12 SUM11 SUM10 SUM9 SUM8 SUM7
COUT6 COUT7 TCCO COENB ERASE RESET DIENB DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 CIENB TCCI
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
SUM6
SUM5
SUM4
SUM3
SUM2
SUM1
SUM0
NOTE: overbar signal name represents active signal.
SENBL
CIN7
HSP43881 Description
SYMBOL NUMBER A10, D11, F10, A11, E11, H11, A58, B67, TYPE Power Supply Input. DESCRIPTION
Power Supply Ground Input.
DIN0-7
input provides system sample clock. maximum clock frequency 30MHz. These eight inputs data sample input bus. Eight data samples synchronously loaded through these pins register each filter cell simultaneously. DIENB signal enables loading, which synchronous rising edge clock signal. input determines number system interpretation data input samples pins DIN0-7 follows: Unsigned Arithmetic. High Two's Complement Arithmetic. signal synchronously loaded into register same DIN0-7 inputs. this enables data sample input (DIN0-7) filter cells. rising edge signal occurring while DIENB will load register every filter cell with 8-bit value present DIN0-7. high this input forces bits data sample input zero; rising edge when DIENB high will load register every filter cell with zeros. This signal latched inside delaying effect clock internal Therefore, must during clock cycle immediately preceding presentation desired data DIN0-7 inputs. Detailed operation shown later timing diagrams. These eight inputs used input 8-bit coefficients. coefficients synchronously loaded into register filter CELL rising edge occurs while CIENB low. CIENB signal delayed clock discussed below. TCCI input determines number system interpretation coefficient inputs pins CIN07 follows: TCCI Unsigned Arithmetic. TCCI HIGH Two's Complement Arithmetic. TCCI signal synchronously loaded into register same CIN0-7 inputs. this input enable register every filter cell registers (decimation) every filter cell according state DCM0-1 inputs. rising edge signal occurring while CIENB will load register appropriate registers with coefficient data present their inputs. This provides mechanism shifting coefficients from cell cell through device. high this input freezes contents register registers ignoring signal. This signal latched delayed clock internal Therefore, must during clock cycle immediately preceding presentation desired coefficient CIN07 inputs. Detailed operation shown Timing Diagrams Section. These eight three-state outputs used output 8-bit coefficients from filter cell These outputs enabled COENB signal low. These outputs tied CIN0-7 inputs same recirculate coefficients, they tied CIN0-7 inputs another cascade longer filter lengths. TCCO three-state output determines number system representation coefficients output COUTO-7. tracks TCCI signal this same should tied TCCI input next cascade increased filter lengths. This signal enabled COENB low. COENB input enables COUT0-7 TCCO output. high this input places these outputs their high impedance state.
DIENB
CIN0-7
B9-11, C10-11, D10, E9-10
TCCI
CIENB
COUT0-7
C1-2, D1-2,
TCCO
COENB
HSP43881 Description
SYMBOL DCM0-1 (Continued) TYPE DESCRIPTION These inputs determine internal decimation registers follows: DCM1 DCM0 Decimation Function Decimation Registers used. Decimation Register used. Decimation Registers used. Three Decimation Registers used. coefficients pass from cell cell rate determined number decimation registers used. When decimation registers used, coefficients move from cell cell each clock. When decimation register used, coefficients move from cell cell every other clock, etc. These signals latched delayed clock internal These three-state outputs used output results internal filter cell computations. Individual filter cell results result shift output stage output. individual filter cell result output, ADR0-2 signals select filter cell result. SHADD signal determines whether selected filter cell result output stage adder result output. signals SENBH SENBL enable most significant least significant bits SUM0-25 result, respectively. Both SENBH SENBL enabled simultaneously system 26-bit larger bus. However, individual enables provided facilitate with 16-bit bus. this input enables result bits SUM16-25. high this input places these bits their high impedance state. this input enables result bits SUM0-15. high this input places these bits their high impedance state. These inputs select cell whose accumulator will read through output (SUM0-25) added output stage accumulator. They also determine which accumulator will cleared when ERASE low. selection which accumulator read through output (SUM0-25) which output stage accumulator, these inputs latched delayed clock internal device. ADR0-2 lines remain same address more than clock, output SUM0-25 will change reflect subsequent accumulator updates addressed cell. Only result available during first clock, when ADR0-1 selects cell, will output. This does hinder normal operation since ADR0-1 lines changed sequentially. This feature facilitates interface with slow memories where output required fixed more than clock. SHADD input controls activation shift-and-add operation output stage. This signal latched delayed clock internal device. detailed explanation given Output Stage Section. this input synchronously clears internal registers, except cell accumulators. used with ERASE also clear accumulators simultaneously. This signal latched delayed clock internal this input synchronously clears cell accumulator selected ADR0-1 signals. RESET also simultaneously, cell accumulators cleared. Used aligning chip socket printed circuit board. Must left connect circuit.
NUMBER
SUM0-25
J5-8, J10, K5-11, L-26, L10-11
SENBH SENBL ADR0-2
H1-2
SHADD
RESET
ERASE ALIGN
Functional Description
Digital Filter Processor (DF) composed eight filter cells cascaded together output stage combining selecting filte5r cell outputs (See Block Diagram). Each filter cell contains multiplier accumulator several registers (Figure Each 8-bit coefficient multiplied 8-bit data sample, with result added 26-bit accumulator contents. coefficient output each cell cascaded coefficient input next cell right.
COUT0-7. With decimation, coefficient moves directly from register output, valid clock following entrance. When decimation selected coefficient exit delayed clocks passing through more decimation registers (D1, D3). combination registers through which coefficient passes determined state DCM0 DCM1. output signals (COUT0-7) connected CIN0-7 inputs next cell right. COENB input signal enables COUT0-7 outputs right most cell COUT-07 pins device. registers enabled loading CIENB. Loading synchronous with when CIENB low. Note that
Filter Cell
8-bit coefficient (CIN0-7) enters each cell through register left exits cell right signals
HSP43881
CIENB latched internally. enables register loading after next following onset CIENB low. Actual loading occurs second following onset CIENB low. Therefore, CIENB must during clock cycle immediately preceding presentation coefficient CIN0-7 inputs. most basic operations, CIENB will throughout process, this latching delay sequence only important during initialization phase. When CIENB high, coefficients frozen. These registers cleared synchronously under control RESET, which latched delayed exactly like CIENB. output register (C0-8) input multiplier. other input multiplier comes from output register. This register loaded with data sample from device input signals DIN0-7 discussed above. register enabled loading DIENB. Loading synchronous with when DIENB low. Note that DIENB latched internally. enables register loading after next following onset DIENB low. Actual loading occurs second following onset DIENB low; therefore, DIENB must during clock cycle immediately preceding presentation data sample DIN0-7 inputs. most basic operations, DIENB will throughout process, this latching delay sequence only important during initialization phase. When DIENB high, register loaded with zeros. multiplier pipelined modeled multiplier core followed pipeline registers, MREG0 MREG1 (Figure multiplier output sign extended input operand 26-bit adder. other adder operand output 26-bit accumulator. adder output loaded synchronously into both accumulator TREG. TREG loading disabled cell select signal, CELLn, where cell number. cell select decoded from ADR0-2 signals generate TREG load enable. cell select inverted applied load enable TREG. Operation such that TREG loaded whenever cell selected. Therefore, TREG loaded every clock except clock following cell selection. purpose TREG hold result products calculation during clock when accumulator cleared prepare next products calculation. This allows continuous accumulation without wasting clocks. accumulator loaded with adder output every clock unless cleared. cleared synchronously ways. When RESET ERASE both low, accumulator cleared along with other registers device. Since ERASE RESET latched delayed clock internally, clearing occurs second following onset both ERASE RESET low. second accumulator clearing mechanism clears single accumulator selected cell. cell select signal, CELLn, decoded from ADR0-2 ERASE signal enable clearing accumulator next CLK. ERASE RESET signals clear internal registers states follows:
ERASE RESET CLEARING EFFECT clearing occurs, internal state remains same. RESET only active, registers except accumulators cleared, including internal pipeline registers. ERASE only active, accumulator whose address given ADR0-2 inputs cleared. Both RESET ERASE active, accumulators, well other registers cleared.
Output Stage
output stage consists 26-bit adder, 26-bit register, feedback multiplexer from register adder, output multiplexer 26-bit three-state driver stage (Figure 26-bit output adder filter cell accumulator result most significant bits output buffer. This result stored back output buffer. This operation takes place clock period. eight LSBs output buffer lost. filter cell accumulator selected ADR0-2 inputs. MSBs output buffer actually pass through zero their output adder input. zero controlled SHADD input signal selects either output buffer MSBs zeros adder input. SHADD input selects zero. high SHADD input selects output buffer MSBs, thus, activating shift operation. SHADD signal latched delayed clock internally.
HSP43881
DCM1.D DCM0.D RESET.D CIENB.D TCCI CIN0-7 C0-7 C.TCCI RESET.D DIENB.D DIN0-7 MREG0 DCM1.D DCM0.D RESET.D DIENB.D CIENB.D ADR0.D ADR1.D ADR2.D ERASE.D ADDER ACC0-25 ERASE.D CELLn ACC.D0-25 0-17 SIGN EXTENSION 18-25 MREG1 RESET.D X0-8 MULTIPLIER CORE P0-17 C0-8 D.TCCI D0-7 TCCO THREE-STATE BUFFERS CELL ONLY
COUT0-7
COENB
LATCHES DCM1 DCM0 RESET DIENB CIENB ADR0 ADR1 ADR2 ERASE
ADR0 ADR1 ADR2 DECODER
CELL CELL
CELL
CELLn
AOUT0-25
FIGURE FILTER CELL
HSP43881
ADR0.D-ADR2.D 0-18 SIGN 18-25 RESET.D (LSBs) 0-17
CELL RESULT
SHADD
SHADD.D ZERO 8-25 OUTPUT BUFFER RESET.D
MSBs SHIFTED BITS RIGHT (BITS
OUTPUT RESET.D
SENBL SENBH
THREE-STATE BUFFER
SUM0-25
FIGURE OUTPUT STAGE
least significant bits (LSBs) from either cell accumulator output buffer output SUM0-25 bus. output determines whether cell accumulator selected ADR0-2 output buffer output bus. This controlled SHADD input signal. Control based state SHADD during successive clocks; other words, output selection contains memory. SHADD during clock cycle during previous clock, output selects contents filter cell accumulator addressed ADR0-2. Otherwise output selects contents output buffer. ADR0-2 lines remain same address more than clock, output SUM0-25 will change reflect subsequent accumulator updates addressed cell. Only result available during first clock when ADR0-2 selects cell will output. This does hinder normal operation since ADR0-2 lines changed sequentially. This feature facilitates interface with slow memories where output required fixed more than clock.
SUM0-25 output controlled SENBH SENBL signals. SENBL enables bits SUM0-15. SENBH enables bits SUM16-25. Thus, bits output simultaneously external system 26-bit larger bus. external system only bits, bits enabled groups bits (sign extended).
Arithmetic
Both data samples coefficients represented either unsigned two's complement numbers. TCCI inputs determine type arithmetic representation. Internally values represented 9-bit two's complement number. value additional ninth depends arithmetic representation selected. two's complement arithmetic, sign extended into ninth bit. unsigned arithmetic, bit-9 multiplier output bits accumulator bits. accumulator width determines maximum possible number terms products without
HSP43881
overflow. maximum number terms depends also number system distribution coefficient data values. Then maximum numbers terms products are:
TERMS 1032 2080 2047 2064
practical filters, coefficients never near maximum value, even larger vectors possible practice.
Basic Operation
NUMBER SYSTEM Unsigned Vectors Two's Complement:
Positive Vectors Negative Vectors Positive Negative Vector
Unsigned Two's Complement Vector:
Positive Two's Complement Vector Negative Two's Complement Vector
1036 1028
simple, 30MHz 8-tap filter example serves illustrate more clearly operation sequence table (Table shows results multiply accumulate each cell after each clock. coefficient sequence, enters left moves from left right through cells. data sample sequence, enters from top, with each cell receiving same sample simultaneously. Each cell accumulates products output point. Eight sums products calculated simultaneously, staggered time that output available every system clock.
TABLE 30MHz, 8-TAP FILTER SEQUENCE X15.X9, X7.X1, C0.C6, C0.C6,
HSP43881
Y15.Y14,.Y8,
CELL
CELL
CELL
CELL
CELL
CELL
CELL
CELL
SUM/CLR
Cell (Y7) Cell (Y8) Cell (Y9) Cell (Y10) Cell (Y11) Cell (Y12) Cell (Y13) Cell (Y14) Cell (Y15)
HSP43881
SAMPLE DATA (Xn) 30MHz CLOCK
3-BIT COUNTER
ADR2 ADR1 ADR0 SHADD SENBH DIN0-7
SENBL
DIENB HSP43881 D0-D7 COEFF. RAM/ROM SYSTEM RESET ERASE CIN0-7 CIENB DCM1 DCM0 RESET ERASE COENB TCCI COUT0-7 TCCO SUM0-25
(Yn)
FIGURE 30MHZ, FILTER APPLICATION SCHEMATIC
Detailed operation perform basic 8-tap, 8-bit coefficient, 8-bit data, 30MHz filter best understood observing schematic (Figure timing diagram (Figure internal pipeline length four clock cycles, corresponding register levels CREG XREG), MREG0, MREG1, TREG (Figures Therefore, delay from presentation data coefficients DIN0-7 CIN0-7 inputs appearing SUM0-25 output Where: filter length internal pipeline delay After pipeline filled, output sample available every clock. delay last sample output from last sample input output sums, shown Timing Diagram derived from products equation: Y(n) C(0) X(n) C(1) X(n1) C(2) C(3) C(4) C(5) C(6) C(7)
Extended Filter Length
Filter lengths greater that eight taps created either cascading together multiple devices "reusing" single device. Using multiple devices, filter over 1000taps constructed operate 30MHz sample rate. Using single device clocked 30MHz, filter over 1000 taps constructed operate less than 30MHz sample rate. Combinations these techniques also possible.
HSP43881
RESET ERASE DIN0-7 DIENB CIN0-7 CIENB ADR0-2 SUM0-24 SHADD SENBL SENBH DCM0-1
FIGURE 30MHz, 8-TAP FILTER TIMING
SAMPLE DATA (Xn) 30MHz CLOCK
DIN0-7 DIENB 4-BIT COUNTER RESET 8x16 COEFF. RAM/ROM D0-D7 TCCI CIN0-7 SYSTEM RESET
ADR1 ADR0 ADR2 SHADD SENBH
SENBL SUM0-24
ADR1 ADR0 ADR2 SHADD SENBH DIN0-7 DIENB
SENBL SUM0-24
HSP43881 TCCO COUT0-7
TCCI
HSP43881
HSP43881
TCCO
CIN0-7 COUT0-7
CIENB DCM1 DCM0 RESET ERASE COENB
CIENB DCM1 DCM0 RESET ERASE COENB
(Yn)
FIGURE 30MHz, 16-TAP FILTER CASCADE APPLICATION SCHEMATIC
HSP43881 Cascade Configuration
design filter length L>8, cascaded connecting COUT0-7 outputs (i)th CIN07 inputs (i+1)th DIN0-7 inputs SUM0-25 outputs also tied together. specific example cascaded illustrates technique (Figure Timing (Figure similar simple 8-tap FIR, except ERASE SENBL/SENBH signals must enabled independently order clear correct accumulators enable SUM0-25 output signals proper times.
Extended Coefficient Data Sample Word Size
sample coefficient word size extended utilizing several parallel maximum sample rate single with resulting lower sample rates. technique compute partial products combine these partial products shifting adding obtain final result. shifting adding accomplished with external adders full speed) with DF's shift mechanism contained output stage reduced speed).
Single Configuration
Using single filter length constructed processing passes illustrated following table (Table 16-tap FIR. Each pass composed cycles computes eight output samples. pass sample with indices +(L1) enter DIN0-7 inputs. coefficients enter CIN0-7 inputs, followed seven zeros. these zeros entered, result samples output accumulators reset. Initial filing pipeline shown this sequence table. Filter outputs through FIFO even sample rate.
Decimation/Resampling
HSP43881 provides mechanism decimating factors From filter cell block diagram (Figure note three registers multiplexers coefficient path through cell. These allow coefficients delayed clocks through cell. sequence table (Table decimate filter illustrates technique (internal cell pipelining ignored simplicity). Detailed timing 30MHz input sample rate, 15MHz output sample rate (i.e., decimate two), 16-tap filter, including pipelining, shown Figure This filter requires only single HSP43881
RESET
ERASE
ERASE
DIN0-7
DIENB
CIN0-7
CIENB
HSP43881
ADR0-2
SUM0-25
SUM0-25
SHADD
SENBL/H
SENBL/H
DCM0-1
FIGURE 16-TAP 30MHz FILTER TIMING USING CASCADED HSP43881s
HSP43881
TABLE 16-TAP FILTER SEQUENCE USING SINGLE Data Sequence X30.X9, X22.X1, Input Coefficient Sequence C0.C14, C15, 0.0, C0.C14, Input CELL +C14 +C13 +C12 +C11 +C10 CELL CELL CELL +C14 +C13 +C12 +C11 +C10
HSP43881
.Y23, 0.0, Y22,.Y15, CELL CELL CELL SUM/CLR
CELL
CELL (Y15) CELL (Y16) CELL (Y17) CELL (Y18) CELL (Y19) CELL (Y20) CELL (Y21) CELL (Y22)
HSP43881
TABLE 16-TAP FILTER SEQUENCE USING SINGLE (Continued) Data Sequence X30.X9, X22.X1, Input Coefficient Sequence C0.C14, C15, 0.0, C0.C14, Input CELL +C14 +C13 +C12 +C11 +C10 CELL
HSP43881
.Y23, 0.0, Y22,.Y15, CELL CELL CELL SUM/CLR CELL (Y23) CELL (Y24) CELL (Y25) CELL (Y26) CELL (Y27)
CELL
CELL
CELL
+C15
HSP43881
TABLE 16-TAP DECIMATE FILTER SEQUENCE; 30MHz 15MHz Data Sequence .X2, Input Coefficient Sequence .C15, .C13, C14, Input CELL +C14 +C13 +C12 +C11 +C10 +C14 +C13 +C12 +C11 +C10 +C14 +C14 +C14 +C14 +C14 +C14 CELL CELL CELL
HSP43881
.Y19, .Y17, CELL CELL CELL +C14 +C13 +C12 +C11 +C10 +C14 SUM/CLR CELL (Y15) CELL (Y17) CELL (Y19) CELL (Y21) CELL (Y23) CELL (Y25) CELL (Y27) CELL (Y29) CELL (Y31)
CELL
RESET
ERASE
DIN0-7
DIENB
CIN0-7
CIENB ADR0-2
SUM0-25
HSP43881
SHADD
SENBL
SENBH
DCM0-1
FIGURE 16-TAP DECIMATE-BY-TWO FILTER TIMING; 30MHz, 15MHz
HSP43881
Absolute Maximum Ratings
Supply Voltage 8.0V Input, Output Voltage -0.5 0.5V Rating Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PLCC Package Package Maximum Junction Temperature PLCC Package 150oC Package 175oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (PLCC Lead Tips Only)
Operating Conditions
Voltage Range Temperature Range 70oC
Characteristics
Gate Count 17,763 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical Input Voltage Logical Zero Input Voltage Logical Output Voltage Logical Zero Output Voltage Clock Input High Clock Input Input Capacitance PLCC Output Capacitance PLCC NOTES: Operating supply current proportional frequency. Typical rating 7mA/MHz. Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. Output load test load circuit 40pF. SYMBOL ICCOP ICCSB VIHC VILC COUT Note NOTES Notes Note TEST CONDITIONS Frequency 20MHz Max, Input Max, Input 400µA, 2mA, Frequency 1MHz measurements referenced 25oC UNITS
HSP43881
Electrical Specifications
PARAMETER TEST CONDITIONS Clock Period Clock Clock High Input Setup Input Hold Coefficient Output Delay Output Enable Delay Output Disable Delay Output Delay Output Rise Output Fall NOTE: Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. ±5%, 70oC (20MHz) SYMBOL Note Note Note NOTES (25.6MHz) (30MHz) UNITS
Test Load Circuit
(NOTE
1.5V
EQUIVALENT CIRCUIT
NOTES: Includes stray capacitance. Switch Open ICCSB ICCOP Tests.
HSP43881 Waveforms
2.0V 2.0V 2.0V 2.0V 3.0V INPUT 0.0V 1.5V 1.5V
4.0V 0.0V
FIGURE CLOCK PARAMETERS
Input includes: DIN0-7, CIN0-7, DIENB, CIENB, ERASE, RESET,DCM0-1, ADRO-2, TCS, TCCI, SHADD FIGURE INPUT SETUP HOLD
2.0V tODC, tODS SUM0-25 COUT0-7 TCCO 1.5V 2.0V 0.8V
SUM-25, COUTO-7, TCCO assumed highimpedance state. FIGURE SUM0-25, COUT0-7, TCCO OUTPUT DELAYS
FIGURE OUTPUT RISE FALL TIMES
SENBL SENBH COENB
3.0V 1.5V tOED tODD 1.5V INPUT 0.0V 1.5V
DEVICE UNDER TEST
1.5V
OUTPUT
SUM0-25 COUT0-7 TCCO
HIGH IMPEDANCE
1.7V 1.3V
HIGH IMPEDANCE
NOTE: Testing: Inputs driven 3.0V Logic 0.0V Logic "0". Input output timing measurements made both Logic "0". driven measured 2.0V. FIGURE TESTING INPUT, OUTPUT WAVEFORM
FIGURE OUTPUT ENABLE, DISABLE TIMING
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
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2758.4 Digital Filter HSP43881 video speed Digital Filter (D

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