2802.3 Decimating Digital Filter HSP43220/883 Decimating Dig

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2802.3 Decimating Digital Filter HSP43220/883 Decimating Dig

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HSP43220/883
2802.3
Decimating Digital Filter
HSP43220/883 Decimating Digital Filter linear phase pass decimation filter which optimized filtering narrow band signals broad spectrum signal processing applications. HSP43220/883 offers single chip solution signal processing application which have historically required several boards ICs. This reduction component count results faster development times, well reduction hardware costs. HSP43220/883 implemented stage filter structure. seen Block Diagram, first stage High Order Decimation Filter (HDF) which utilizes efficient decimation (sample rate reduction) technique obtain decimation 1024 through coarse low-pass filtering process. provides 96dB aliasing rejection signal pass band. second stage consists Finite Impulse Response (FIR) decimation filter structured transversal filter with symmetric taps which implement filters with sharp transition regions. perform further decimation required, while preserving 96dB aliasing attenuation obtained HDF. combined total decimation capability 16,384. HSP43220/883 accepts 16-bit parallel data complement format sampling rates 30MSPS. provides 16-bit microprocessor compatible interface simplify task programming three-state outputs allow connection several common bus. HSP43220/883 also provides capability bypass either additional flexibility.
Features
This Circuit Processed Accordance MIL-STD-883 Fully Conformant Under Provisions Paragraph 1.2.1. Single Chip Narrow Band Filter with 96dB Attenuation 25.6MHz Clock Rate 16-Bit Complement Input 20-Bit Coefficients 24-Bit Extended Precision Output Programmable Decimation Maximum 16,384 Standard 16-Bit Microprocessor Interface Filter Design Software Available
Applications
Very Narrow Band Filters Zoom Spectral Analysis Channelized Receivers
Ordering Information
PART NUMBER HSP43220GM-15/883 HSP43220GM-25/883 TEMP. RANGE (oC) PACKAGE PKG.
Block Diagram
DECIMATION 1024 INPUT CLOCK DATA INPUT CONTROL COEFFICIENTS HIGH ORDER DECIMATION FILTER DECIMATION DECIMATION FILTER CLOCK DATA DATA READY
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999 DECIMATEis trademark Intersil Corporation. PS/2are trademarks Corporation.
HSP43220/883
Absolute Maximum Ratings
Supply Voltage Input, Output Voltage 0.5V Rating Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) Package. 32.9 Maximum Package Power Dissipation 125oC Package. 1.52 Maximum Junction Temperature .175oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) .300oC
Operating Conditions
Voltage Range +4.5V 5.5V Temperature Range -55oC 125oC
Characteristics
Number Gates 48,250
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air. TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed 100% Tested TEST CONDITIONS 5.5V 4.5V 400µA, 4.5V (Note 2.0mA 4.5V (Note GND, 5.5V VOUT GND, 5.5V 5.5V 4.5V GND, 5.5V, Outputs Open 15.0MHz, 5.5V (Note (Note GROUP SUBGROUPS LIMITS TEMP (oC) UNITS
PARAMETER Logical Input Voltage Logical Zero Input Voltage Output HIGH Voltage Output Voltage Input Leakage Current Output Leakage Current Clock Input High Clock Input Standby Power Supply Current
SYMBOL VIHC VILC ICCSB
Operating Power Supply Current Functional Test NOTES:
ICCOP
Interchanging force sense conditions permitted. Operating supply current proportional frequency, typical rating 8mA/MHz. Tested follows: 1MHz, 2.6, 0.4, 1.5V, 1.5V, VIHC 3.4V VILC 0.4V.
HSP43220/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed 100% Tested (NOTES) (NOTE GROUP SUBGROUPS (15MHz) TEMP (oC) TFIR (25.6MHz) TFIR UNITS
PARAMETER Input Clock Period Clock Period Clock Pulse Width Clock Pulse Width High Clock Skew Between FIR_CLK CK_IN RESET Pulse Width Recovery Time RESET ASTARTIN Pulse Width STARTOUT Delay From CK_IN STARTIN Setup Setup Time DATA_IN Hold Time Inputs Write Pulse Width Write pulse Width High Setup Time Address Before Rising Edge Write Setup Time Chip Select Before Rising Edge Write Setup Time Control Before Rising Edge Write DATA_RDY Pulse Width DATA_OUT Delay Relative FIR_CK DATA_RDY Valid Delay Relative FIR_CK DATA_OUT Delay Relative OUT_SELH Output Enable Data Valid NOTES:
SYMBOL tFIR tSPWL tSPWH tRSPW tRTRS tAST tSTOD tSTIC tSET tHOLD tSTADD
tSTCS
tSTCB
tDRPWL tFIRDV tFIRDR tOUT tOEV Note
2TFIR
2TFIR
Testing: 4.5V 5.5V. Inputs driven 3.0V Logic 0.0V Logic "0". Input output timing measurements made 1.5V both Logic "0". driven 4.0V measured 2.0V. Transition measured ±200mV from steady state voltage with loading specified test load circuit 40pF.
HSP43220/883
TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Devices Guaranteed 100% Tested TEST CONDITIONS (15MHz) NOTES Open, 1MHz, measurements referenced device Open, 1MHz, measurements referenced device TEMP (oC) 25oC (25.6MHz) UNITS
PARAMETER CK_IN Pulse Width CK_IN Pulse Width High CK_IN Setup FIR_CK CK_IN Hold from FIR_CK Input Capacitance
SYMBOL tCH1L tCH1H tCIS tCIH
Output Capacitance
COUT
25oC
Output Disable Delay Output Rise Time Output Fall Time NOTES:
tOEZ
Parameters listed Table controlled design process parameters directly tested. These parameters characterized upon initial design after major process and/or design changes. Loading specified test load circuit with 40pF. Applies only when H_BYP H_DRATE
TABLE APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test Final Test Group Groups METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS
HSP43220/883 Burn-In Circuit
HSP43220/883 VIEW PINS DOWN
START ASTART DATA_ START RESET DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_
CLK_IN
DATA_ DATA_
C_BUS C_BUS C_BUS C_BUS C_BUS
C_BUS C_BUS C_BUS C_BUS C_BUS
C_BUS C_BUS
DATA_
DATA_ DATA_ OUT_ SELH C_BUS C_BUS C_BUS C_BUS OUT_ OUT_ FIR_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_
DATA_
BURN-IN CIRCUIT SIGNALS LEAD NAME DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN DATA_IN STARTIN STARTOUT DATA_IN DATA_IN DATA_IN BURN-IN SIGNAL VCC/2 LEAD NAME ASTARTIN DATA_IN DATA_IN DATA_IN DATA_OUT DATA_OUT RESET DATA_OUT DATA_OUT DATA_OUT DATA_OUT BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 LEAD NAME DATA_OUT C_BUS C_BUS C_BUS DATA_OUT DATA_OUT C_BUS DATA_OUT DATA_OUT C_BUS OUT_SEL FIR_CK BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
HSP43220/883
BURN-IN CIRCUIT SIGNALS (CONTINUED) LEAD NOTES: VCC/2 (2.7 ±10%) used outputs only. (±20%) resistor connected pins except GND. ±0.5V. 0.1µF (minimum) capacitor between position. 100kHz ±10%, F0/2, F1/2.F16 F15/2, duty cycle. Input voltage limits: maximum, 4.5V ±10%. NAME DATA_IN DATA_IN DATA_IN CK_IN DAT_OUT OUT_ENP DATA_OUT DATA_OUT DATA_OUT BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 LEAD NAME DATA_OUT C_BUS C_BUS C_BUS DATA_OUT9 DATA_OUT C_BUS C_BUS C_BUS C_BUS OUT_ENX BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 LEAD NAME DATA_OUT DATA_OUT C_BUS C_BUS C_BUS C_BUS DATA_RDY DATA_OUT DATA_OUT DATA_OUT DATA_OUT BURN-IN SIGNAL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
Metal Topology
DIMENSIONS: 349.2 mils METALLIZATION: Type: Thickness: WORST CASE CURRENT DENSITY: 1.18 105A/cm2 GLASSIVATION: Type: Nitrox Thickness:
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
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2802.3 Decimating Digital Filter HSP43220/883 Decimating Dig

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