10-Bit 8-Lead microSOIC/DIP AD7810 AGND VREF AD7810 CHA
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FEATURES 10-Bit with Conversion Time Small Footprint 8-Lead microSOIC Package Specified Over +105 Temperature Range Inherent Track-and-Hold Functionality Operating Supply Range: Specifications Microcontroller-Compatible Serial Interface Optional Automatic Power-Down Conversion Power Operation kSPS Throughput Rate kSPS Throughput Rate Analog Input Range: VREF Reference Input Range: APPLICATIONS Power, Hand-Held Portable Applications that Require Analog-to-Digital Conversion with 10-Bit Accuracy; e.g., Battery Powered Test Equipment, Battery-Powered Communications Systems
10-Bit 8-Lead microSOIC/DIP AD7810
AGND VREF
AD7810
CHARGE REDISTRIBUTION CLOCK
SERIAL PORT
DOUT SCLK
VIN+ VIN- COMP VDD/3 CONTROL LOGIC
CONVST
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7810 high speed, power, 10-bit converter that operates from single supply. part contains successive approximation converter, with inherent track/hold functionality, pseudo differential input high speed serial interface that interfaces most microcontrollers. AD7810 fully specified over temperature range -40°C +105°C. using technique that samples state CONVST (convert start) signal conversion, AD7810 used automatic power-down mode. When used this mode, AD7810 automatically powers down conversion "wakes start conversion. This feature significantly reduces power consumption part lower throughput rates. AD7810 also operate high speed mode where part powered down between conversions. this high speed mode operation, conversion time AD7810 maximum throughput rate dependent speed serial interface microcontroller. part available small 8-lead, 0.3" wide, plastic dualin-line package (mini-DIP); 8-lead, small outline (SOIC); 8-lead microSOIC package.
Complete, 10-Bit 8-Lead Package AD7810 10-bit with inherent track/hold functionality high speed serial interface-all 8-lead microSOIC package. VREF connected eliminate need external reference. result high speed, power, space saving solution. Power, Single Supply Operation AD7810 operates from single supply typically consumes only power while converting. power dissipation significantly reduced lower throughput rates using automatic power-down mode, e.g., throughput rate kSPS power consumption only Automatic Power-Down automatic power-down mode, whereby AD7810 powers down conversion "wakes before next conversion, means AD7810 ideal battery powered applications. Power Throughput Rate section. Serial Interface easy use, fast serial interface allows connection most popular microprocessors with external circuitry.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
AD7810-SPECIFICATIONS (GND
Parameter DYNAMIC PERFORMANCE Signal (Noise Distortion) Ratio1 Total Harmonic Distortion1 Peak Harmonic Spurious Noise Intermodulation Distortion2 Order Terms Order Terms ACCURACY Resolution Relative Accuracy1 Differential Nonlinearity (DNL)1 Offset Error1 Gain Error1 Minimum Resolution Which Missing Codes Guaranteed ANALOG INPUT Input Voltage Range Input Leakage Current2 Input Capacitance2 REFERENCE INPUTS2 VREF Input Voltage Range Input Leakage Current Input Capacitance LOGIC INPUTS2 VINH, Input High Voltage VINL, Input Voltage Input Current, Input Capacitance, LOGIC OUTPUTS Output High Voltage, Output Voltage, High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Conversion Time Track/Hold Acquisition Time1 POWER SUPPLY Power Dissipation Power-Down Mode Power Dissipation Automatic Power Down kSPS Throughput kSPS Throughput kSPS Throughput VREF 2.7-5.5 17.5
VDD. specifications +105 unless otherwise noted.)
Unit kHz, 48.5 Bits Bits Volts Test Conditions/Comments kHz, fSAMPLE
Version
Typically
ISOURCE ISINK
Acquisition Time Section Specified Performance Sampling kSPS Logic Inputs
NOTES Terminology section. Sample tested during initial release after redesign process change that affect this parameter. Specifications subject change without notice.
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AD7810 Timing Characteristics1, (-40 +105
Parameter t83, tPOWER
VDD, unless otherwise noted)
Conditions/Comments Conversion Time Mode Operation (High Speed Mode) CONVST Pulsewidth SCLK High Pulsewidth SCLK Pulsewidth CONVST Rising Edge SCLK Rising Edge Set-Up Time SCLK Rising Edge DOUT Data Valid Delay Data Hold Time after Rising Edge SCLK Relinquish Time after Falling Edge SCLK Power-Up Time after Rising Edge CONVST
Unit (max) (min) (min) (min) (min) (max) (max) (max) (min) (max)
NOTES Sample tested ensure compliance. Figures These numbers measured with load circuit Figure They defined time required cross 10%. Derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that time, quoted Timing Characteristics true relinquish time part such independent external loading capacitances. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
25°C unless otherwise noted)
-0.3 Digital Input Voltage (CONVST, SCLK) -0.3 Digital Output Voltage (DOUT) -0.3 VREF -0.3 Analog Inputs (VIN+, VIN-) -0.3 Storage Temperature Range -65°C +150°C Junction Temperature 150°C Plastic Package, Power Dissipation Thermal Impedance 125°C/W Thermal Impedance 50°C/W Lead Temperature Soldering sec) 260°C
SOIC Package, Power Dissipation Thermal Impedance 160°C/W Thermal Impedance 56°C/W Lead Temperature, Soldering Vapor Phase sec) 215°C Infrared sec) 220°C MicroSOIC Package, Power Dissipation Thermal Impedance 206°C/W Thermal Impedance 44°C/W Lead Temperature, Soldering Vapor Phase sec) 215°C Infrared sec) 220°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ORDERING GUIDE
Model AD7810YN AD7810YR AD7810YRM
Linearity Error (LSB)
Temperature Range -40°C +105°C -40°C +105°C -40°C +105°C
Package Description Plastic Small Outline (SOIC) microSOIC
Package Options SO-8 RM-8
Branding Information
OUTPUT 1.6V 50pF
Figure Load Circuit Digital Output Timing Specifications
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AD7810
FUNCTION DESCRIPTIONS
Mnemonic CONVST
Description Convert Start. Falling edge puts track-and-hold into hold mode initiates conversion. rising edge CONVST enables serial port AD7810. This useful multipackage applications where number devices share same serial bus. state this conversion also determines whether part powered down not. Operating Modes section this data sheet. Positive input pseudo differential analog input. Negative input pseudo differential analog input. Ground reference analog digital circuitry. External reference connected here. Serial data shifted this pin. Serial Clock. external serial clock applied here. Positive Supply Voltage
VIN+ VIN- VREF DOUT SCLK
CONFIGURATION DIP/SOIC
CONVST VIN+
SCLK VIEW VIN- (Not Scale) DOUT VREF
AD7810
Typical Performance Characteristics
2048 POINT SAMPLING 357.142kSPS 30kHz
POWER
THROUGHPUT kSPS
Figure Power Throughput
1013
0.01
-115
FREQUENCY BINS
Figure AD7810
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AD7810
TERMINOLOGY Signal (Noise Distortion) Ratio
This measured ratio signal (noise distortion) output converter. signal amplitude fundamental. Noise nonfundamental signals half sampling frequency (fS/2), excluding ratio dependent upon number quantization levels digitization process; more levels, smaller quantization noise. theoretical signal (noise distortion) ratio ideal N-bit converter with sine wave input given Signal (Noise Distortion) (6.02N 1.76) Thus 10-bit converter, this
Total Harmonic Distortion
AD7810 tested using CCIF standard where input frequencies near input bandwidth used. this case, second third order terms different significance. second order terms usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental expressed dBs.
Relative Accuracy
Total harmonic distortion (THD) ratio harmonics fundamental. AD7810 defined
Relative accuracy endpoint nonlinearity maximum deviation from straight line passing through endpoints transfer function.
Differential Nonlinearity
This difference between measured ideal change between adjacent codes ADC.
Offset Error
where amplitude fundamental amplitudes second through sixth harmonics.
Peak Harmonic Spurious Noise
This deviation first code transition (0000 000) (0000 001) from ideal, i.e., AGND LSB.
Gain Error
Peak harmonic spurious noise defined ratio values next largest component output spectrum fS/2 excluding value fundamental. Normally, value this specification determined largest harmonic spectrum, parts where harmonics buried noise floor, will noise peak.
Intermodulation Distortion
This deviation last code transition (1111 110) (1111 111) from ideal (i.e., VREF LSB) after offset error been adjusted out.
Track/Hold Acquisition Time
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include fb), while third order terms include (2fa fb), (2fa fb), 2fb) 2fb).
Track/hold acquisition time time required output track/hold amplifier reach final value, within ±1/2 LSB, after conversion (the point which track/hold returns track mode). also applies situations where there step input change input voltage applied VIN+ input AD7810. means that user must wait duration track/hold acquisition time, after conversion after step input change VIN+, before starting another conversion ensure that part operates specification.
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AD7810
CIRCUIT DESCRIPTION Converter Operation
SUPPLY 2.7V 5.5V
AD7810 successive approximation analog-to-digital converter based around charge redistribution DAC. convert analog input signals range VDD. Figures below show simplified schematics ADC. Figure shows during acquisition phase. closed Position comparator held balanced condition; sampling capacitor acquires signal VIN+.
CHARGE REDISTRIBUTION
WIRE SERIAL INTERFACE VREF SCLK
VREF INPUT
VIN+ VIN- AGND
AD7810
DOUT CONVST
Figure Typical Connection Diagram
Analog Input
VIN+
SAMPLING CAPACITOR
ACQUISITION PHASE
CONTROL LOGIC COMPARATOR CLOCK
Figure Acquisition Phase
When starts conversion (see Figure will open will move Position causing comparator become unbalanced. control logic charge redistribution used subtract fixed amounts charge from sampling capacitor bring comparator back into balanced condition. When comparator rebalanced, conversion complete. control logic generates output code. Figure shows transfer function.
CHARGE REDISTRIBUTION
Figure shows equivalent circuit analog input structure AD7810. diodes, provide protection analog inputs. Care must taken ensure that analog input signal never exceeds supply rails more than This will cause these diodes become forward biased start conducting current into substrate. maximum current these diodes conduct without causing irreversible damage part capacitor typically about primarily attributed capacitance. resistor lumped component made resistance multiplexer switch. This resistor typically about capacitor sampling capacitor capacitance
VIN+ CONVERT PHASE SWITCH OPEN ACQUISITION PHASE SWITCH CLOSED 3.5pF
VIN+
SAMPLING CAPACITOR
Figure Equivalent Analog Input Circuit
CONTROL LOGIC COMPARATOR CLOCK
CONVERSION PHASE
Figure Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure shows typical connection diagram AD7810. serial interface implemented using wires; rising edge CONVST enables serial interface-see Serial Interface section more details. VREF connected well decoupled provide analog input range VDD. When first connected, AD7810 powers current mode, i.e., power-down. rising edge CONVST input will cause part power up-see Operating Modes. power consumption concern, automatic power-down conversion should used improve power performance. Power Throughput Rate section data sheet.
analog input AD7810 made pseudo differential pair. VIN+ pseudo differential with respect VIN-. signal applied VIN+, pseudo differential scheme sampling capacitor connected VIN- during conversion (see Figure This input scheme used remove offsets that exist system. example, system offset offset could applied VIN- signal applied VIN+. This effect offsetting input span only possible offset input span when reference voltage (VREF) less than VOFFSET.
CHARGE REDISTRIBUTION SAMPLING CAPACITOR VOFFSET VOFFSET VIN+ CONVERSION PHASE CLOCK COMPARATOR CONTROL LOGIC
Figure Pseudo Differential Input Scheme
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AD7810
When using pseudo differential input scheme, signal VIN- must vary more than during conversion process. signal VIN- varies during conversion, conversion result will incorrect. single-ended operation, VIN- always connected AGND. Figure shows AD7810 pseudo differential input being used make unipolar current measurement. sense resistor used convert current voltage voltage, applied differential input shown.
small values source impedance, settling time associated with sampling circuit (100 effect, acquisition time ADC. example, with source impedance (R2) charge time sampling capacitor approximately charge time becomes significant source impedances greater.
Acquisition Time
VIN+ RSENSE VIN-
AD7810
applications recommended always buffer analog input signals. source impedance drive circuitry must kept possible minimize acquisition time ADC. Large values source impedance will cause degrade high throughput rates. addition, better performance generally achieved using external capacitor VIN+.
TRANSFER FUNCTION
Figure Current Measurement Scheme
Acquisition Time
starts acquisition phase conversion ends falling edge CONVST signal. conversion there settling time associated with sampling circuit. This settling time lasts approximately analog signal VIN+ also being acquired during this settling time; therefore, minimum acquisition time needed approximately Figure shows equivalent charging circuit sampling capacitor when acquisition phase. represents source impedance buffer amplifier resistive network; internal multiplexer resistance sampling capacitor.
VIN+ 3.5pF
output coding AD7810 straight binary. designed code transitions occur successive integer values (i.e., LSB, LSBs, etc.). size VREF/1024. ideal transfer characteristic AD7810 shown Figure below.
111.111 111.110
CODE
111.000 011.111 1LSB VREF/1024
000.010
000.001 000.000 1LSB ANALOG INPUT +VREF -1LSB
Figure Transfer Characteristic Figure Equivalent Sampling Circuit
During acquisition phase, sampling capacitor must charged within final value. time takes charge sampling capacitor (tCHARGE) given following formula: tCHARGE
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AD7810
POWER-UP TIMES
AD7810 power-up time. When first connected, AD7810 current mode operation. order carry conversion, AD7810 must first powered powered rising edge CONVST pin. conversion initiated falling edge CONVST. Figure shows power AD7810 when first connected after AD7810 powered down using CONVST pin. Care must taken ensure that CONVST AD7810 logic when first applied.
MODE (CONVST IDLES HIGH)
OPERATING MODES Mode Operation (High Speed Sampling)
tPOWER-UP
When AD7810 used this mode operation, part powered down between conversions. This mode operation allows high throughput rates achieved. timing diagram Figure shows this optimum throughput rate achieved bringing CONVST signal high before conversion. AD7810 leaves tracking mode goes into hold falling edge CONVST. conversion also initiated this time. conversion takes complete. this point, result current conversion latched into serial shift register, state CONVST signal checked. CONVST signal should high conversion prevent part from powering down.
CONVST
CONVST MODE (CONVST IDLES LOW) CONVST
SCLK
tPOWER-UP
Figure Power-Up Times
POWER THROUGHPUT RATE
DOUT
CURRENT CONVERSION RESULT
Figure Mode Operation Timing
operating AD7810 Mode average power consumption AD7810 decreases lower throughput rates. Figure shows automatic power-down implemented using CONVST signal achieve optimum power performance AD7810. throughput rate reduced, device remains power-down state longer average power consumption over time drops accordingly.
tCONVERT tPOWER-UP
CONVST POWER-DOWN
tCYCLE
10kSPS
serial port AD7810 enabled rising edge CONVST signal (see Serial Interface section). explained earlier, this rising edge should occur before conversion process part powered down. serial read take place stage after rising edge CONVST. serial read initiated before current conversion process (i.e., time "A"), result previous conversion shifted DOUT pin. possible allow serial read extend beyond conversion. this case data will latched into output shift register until read finished. dynamic performance AD7810 typically degrades while reading during conversion. user waits until conversion process, i.e., after falling edge CONVST (Point "B"), before initiating read, current conversion result shifted out.
Figure Automatic Power-Down
example, AD7810 operated continuous sampling mode with throughput rate kSPS, power consumption calculated follows. power dissipation during normal operation power-up time conversion time AD7810 said dissipate (worst case) during each conversion cycle. throughput rate kSPS, cycle time average power dissipated during each cycle (3.8/100) Figure shows graph Power Throughput.
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AD7810
Mode Operation (Automatic Power-Down)
When used this mode operation, part automatically powers down conversion. This achieved leaving CONVST signal until conversion. Because takes approximately part power after been powered down, this mode operation intended used applications where slower throughput rates required, i.e., order kSPS. timing diagram Figure shows operate part this mode. AD7810 powered down, rising edge CONVST pulse causes part power When part powered after rising edge CONVST), CONVST signal brought low, conversion initiated this falling edge CONVST signal. conversion takes after this time, conversion result latched into serial shift register part powers down. Therefore, when part operated Mode effective conversion time equal power-up time (1.5 conversion time (2.3 µs). NOTE: Although AD7810 takes power after rising edge CONVST, necessary leave CONVST high after rising edge before bringing initiate conversion. CONVST signal goes before time elapsed, then power-up time timed internally conversion then initiated. Hence AD7810 guaranteed have always powered before conversion initiated-even CONVST pulsewidth CONVST width then conversion initiated falling edge. case Mode operation, rising edge CONVST pulse enables serial port AD7810 (see Serial Interface section). serial read initiated soon after this rising edge (Point "A"), i.e., before conversion, result previous conversion shifted DOUT. order read result current conversion, user must wait least after falling edge CONVST
before initiating serial read. serial port AD7810 still functional even though AD7810 been powered down. NOTE: Serial read should cross next rising edge CONVST. Because possible serial read from part while powered down, AD7810 powered only conversion immediately powered down conversion. This significantly improves power consumption part slower throughput rates-see Power Throughput Rate section.
SERIAL INTERFACE
serial interface AD7810 consists three wires, serial clock input SCLK, serial port enable CONVST serial data output DOUT (see Figure 16). serial interface designed allow easy interfacing most microcontrollers, e.g., PIC16C, PIC17C, QSPI SPI, without need gluing logic. When interfacing 8051, SCLK must inverted. Microprocessor Interface section explains interface some popular microcontrollers. Figure shows timing diagram serial read from AD7810. serial interface works with both continuous noncontinuous serial clock. rising edge CONVST signal resets counter, which counts number serial clocks ensure correct number bits shifted serial shift registers. SCLK ignored once correct number bits have been shifted out. order another serial transfer take place, counter must reset falling edge 10th SCLK. Data clocked from DOUT line first rising SCLK edge after rising edge CONVST signal subsequent SCLK rising edges. DOUT enters high impedance state again falling edge 10th SCLK. multipackage applications, CONVST signal used chip select signal. serial interface will shift data until receives rising edge CONVST pin.
tPOWER-UP
CONVST
SCLK DOUT CURRENT CONVERSION RESULT
Figure Mode Operation Timing
SCLK
CONVST
DOUT
Figure AD7810 Serial Interface Timing
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AD7810
MICROPROCESSOR INTERFACING AD7810 8051
serial interface AD7810 allows parts directly connected range many different microprocessors. This section explains interface AD7810 with some more common microcontroller serial interface protocols.
AD7810 PIC16C6x/7x
PIC16C6x Synchronous Serial Port (SSP) configured Master with Clock Polarity This done writing Synchronous Serial Port Control Register (SSPCON). PIC16/17 Microcontroller User Manual. Figure shows hardware connections needed interface PIC16/PIC17. this example port being used pulse CONVST enable serial port AD7810. This microcontroller transfers only eight bits data during each serial transfer operation, therefore, consecutive read operations needed.
AD7810*
SCLK DOUT CONVST
AD7810 requires clock synchronized serial data; therefore, 8051 serial interface must operated Mode this mode serial data enters exits through RXD, serial clock output (half duplex). Figure shows 8051 connected AD7810. However, because AD7810 shifts data rising edge serial clock, serial clock must inverted.
AD7810*
SCLK DOUT CONVST P1.1
8051*
*ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing 8051 Serial Port
PIC16C6x/7x*
SCK/RC3 SDO/RC5
*ADDITIONAL PINS OMITTED CLARITY
possible implement serial interface using data ports 8051 microcontroller). This would allow direct interfacing between AD7810 8051 implemented. technique involves "bit banging" port (e.g., P1.0) generate serial clock using another port (e.g., P1.1) read data, Figure
AD7810*
SCLK DOUT CONVST *ADDITIONAL PINS OMITTED CLARITY P1.0 P1.1 P1.2
Figure Interfacing PIC16/PIC17
AD7810 MC68HC11
8051*
Serial Peripheral Interface (SPI) MC68HC11 configured Master Mode (MSTR Clock Polarity (CPOL) Clock Phase (CPHA) configured writing Control Register (SPCR)-see 68HC11 User Manual. connection diagram shown Figure
AD7810*
SCLK DOUT CONVST *ADDITIONAL PINS OMITTED CLARITY
Figure Interfacing 8051 Using Ports
MC68HC11*
SCLK/PD4 MISO/PD2
Figure Interfacing MC68HC11
-10-
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AD7810
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
8-Lead Plastic (N-8)
0.430 (10.92) 0.348 (8.84)
0.280 (7.11) 0.240 (6.10)
0.210 (5.33) 0.160 (4.06) 0.115 (2.93)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) SEATING PLANE
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15)
0.015 (0.381) 0.008 (0.204)
8-Lead Small Outline (SO-8)
0.1968 (5.00) 0.1890 (4.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35)
0.0098 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
8-Lead microSOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
0.122 (3.10) 0.114 (2.90)
0.199 (5.05) 0.187 (4.75)
0.0256 (0.65) 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 0.028 (0.71) 0.016 (0.41) 0.120 (3.05) 0.112 (2.84)
REV.
-11-
PRINTED U.S.A.
C01311a-0-10/00 (rev.
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