AC'97 SoundMAX Codec AD1886A Stereo Line Level Outputs Mono Outpu

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AC'97 SoundMAX Codec AD1886A Stereo Line Level Outputs Mono Outpu

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AC'97 FEATURES Variable Sample Rate Audio Multiple Codec Configuration Options External Audio Power-Down Control AC'97 FEATURES AC'97 Compliant Greater than Dynamic Range Stereo Headphone Amplifier Multibit Converter Architecture Improved Ratio Greater than 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs for: LINE-IN, VIDEO, Analog Line-Level Mono Inputs Speakerphone BEEP Mono Input w/Built-In Preamp, Switchable from External Sources High-Quality Input with Ground Sense
AC'97 SoundMAX Codec AD1886A
Stereo Line Level Outputs Mono Output Speakerphone Internal Speaker Power Management Support 48-Terminal LQFP Package ENHANCED FEATURES 20-Bit SPDIF Output w/32 kHz, 44.1 kHz, Symbol Rates Full Duplex Variable Sample Rates from 7040 with Resolution Jack Sense Pins Provide Automatic Output Switching Software-Enabled VREFOUT Output Microphones External Power Split Power Supplies (3.3 Digital/5 Analog) Mobile Low-Power Mixer Mode Extended 6-Bit Master Volume Control Extended 6-Bit Headphone Volume Control Digital Audio Mixer Mode PhatStereo Stereo Enhancement
FUNCTIONAL BLOCK DIAGRAM
SPDIF
VREFOUT MIC1 MIC2 LINE VIDEO PHONE_IN 0dB/ 20dB
VREF CHIP SELECT JACK SENSE
AD1886A
SPDIF
SELECTOR
16-BIT CONVERTER
16-BIT CONVERTER
RESET
SYNC MONO_OUT
LINK
SAMPLE RATE GENERATORS
BIT_CLK
HP_OUT_L
PHAT STEREO
SDATA_OUT 16-BIT CONVERTER
LINE_OUT_L
SDATA_IN
LINE_OUT_R
PHAT STEREO GAIN ATTENUATE MUTE
16-BIT CONVERTER
HP_OUT_R
OSCILLATOR
PC_BEEP
XTAL_OUT XTAL_IN
SoundMAX registered trademark Phat trademark Analog Devices, Inc.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2001
AD1886A-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (fS) Input Signal Analog Output Pass Band (CS0, CS1, CHAIN_IN)
ANALOG INPUT
25°C 1008
Test Conditions Calibrated Attenuation Relative Full Scale Input Output Load (LINE_OUT) Output Load (HP_OUT) Test Conditions Calibrated Gain Input -3.0 Relative Full Scale
Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, VIDEO, PHONE_IN, PC_BEEP MIC1 MIC2 with Gain (M20 MIC1 MIC2 with Gain (M20 Input Impedance* Input Capacitance*
MASTER VOLUME
2.83 0.283 2.83
Unit
Parameter Step Size -94.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range Span* Step Size -46.5 dB); MONO_OUT Output Attenuation Range Span* Step Size -88.5 dB); HP_OUT_R, HP_OUT_L Output Attenuation Range Span* Mute Attenuation Fundamental*
PROGRAMMABLE GAIN AMPLIFIER-ADC
-94.5 -46.5 -94.5
Unit
Parameter Step Size 22.5 Gain Range Span
ANALOG MIXER-INPUT GAIN AMPLIFIERS ATTENUATORS
22.5
Unit
Parameter Signal-to-Noise Ratio (SNR) LINE_OUT Other LINE_OUT Step Size (+12 -34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, VIDEO, PHONE_IN, Input Gain/Attenuation Range: MIC, LINE, AUX, VIDEO, PHONE_IN, Step Size dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP
*Guaranteed tested.
-46.5
Unit
REV.
AD1886A
DIGITAL DECIMATION INTERPOLATION FILTERS*
Parameter Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Rejection Group Delay Group Delay Variation over Pass Band
ANALOG-TO-DIGITAL CONVERTERS
0.09 12/fS
Unit
Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 input Referenced Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Crosstalk* Line Inputs (Input Ground Read Input Ground Read LINE_IN Other Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Offset Error
DIGITAL-TO-ANALOG CONVERTERS
-100
Unit Bits
Parameter Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT Dynamic Range (-60 Input Referenced Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Crosstalk* (Input Zero Measure R_OUT; Input Zero Measure L_OUT) Total Audible Out-of-Band Energy (Measured from kHz)*
ANALOG OUTPUT
-100
Unit Bits
Parameter Full-Scale Output Voltage; LINE_OUT Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance Full-Scale Output Voltage; HP_OUT Gain) Output Capacitance* External Load Impedance* VREF VREF_OUT VREF _OUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale Output)
*Guaranteed tested.
2.83
Unit
2.05 2.25 2.25 2.45
REV.
AD1886A-SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS
Parameter High-Level Input Voltage (VIH): Digital Inputs Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH), Low-Level Output Voltage (VOL), Input Leakage Current Output Leakage Current
POWER SUPPLY
0.65 DVDD DVDD
0.35 DVDD DVDD
Unit
Parameter Power Supply Range-Analog (AVDD) Power Supply Range-Digital (DVDD) Power Dissipation-5 V/3.3 Analog Supply Current-5 (AVDD) Digital Supply Current-3.3 (DVDD) Power Supply Rejection (100 Signal kHz)* Both Analog Digital Supply Pins, Both ADCs DACs)
CLOCK SPECIFICATIONS*
4.75
5.25
Unit
Parameter Input Clock Frequency Recommended Clock Duty Cycle
POWER-DOWN STATES
24.576
Unit
Parameter Mixer (Analog Mixer Mixer Mixer Mixer Analog Only (AC-Link Analog Only (AC-Link Off) Standby Headphone Standby
*Guaranteed tested. Specifications subject change without notice.
Bits PR1, LPMIX, PR1, PR2, PR2, PR2, PR1, LPMIX, PR5, PR1, LPMIX, PR1, PR0, PR4, PR5, PR4, PR3, PR2, PR1,
DVDD 17.5 17.0 17.6
AVDD 41.6 38.3 31.9 22.4 17.5 11.2 22.4 22.4 38.8
Unit
REV.
AD1886A
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter RESET Active Pulsewidth RESET Inactive BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Pulsewidth SYNC Inactive BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Pulsewidth SYNC Frequency SYNC Period Setup Falling Edge BIT_CLK Hold from Falling Edge BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time Slot BIT_CLK, SDATA_IN Setup Trailing Edge RESET (Applies SYNC, SDATA_OUT) Rising Edge RESET HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge BIT_CLK Valid
*Guaranteed tested. Specifications subject change without notice.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
162.8
19.5
Unit
162.8 12.288 81.4 32.56 32.56 48.0 20.8 48.84 48.84
REV.
AD1886A
tRST_LOW
RESET
tRST2CLK
BIT_CLK
tRISECLK
SYNC
tFALLCLK
BIT_CLK
Figure Cold Reset
tRISESYNC
SDATA_IN
tFALLSYNC
tSYNC_HIGH
SYNC
tRST2CLK
SDATA_OUT
tRISEDIN
tFALLDIN
BIT_CLK
tRISEDOUT
tFALLDOUT
Figure Warm Reset
tCLK_LOW
BIT_CLK
Figure Signal Rise Fall Time
tCLK_HIGH tCLK_PERIOD
SYNC
SLOT
SLOT
BIT_CLK
tSYNC_LOW
SYNC
SDATA_OUT
WRITE 0x26
DATA
DON'T CARE
tSYNC_HIGH tSYNC_PERIOD
tS2_PDOWN
SDATA_IN NOTE: BIT_CLK SCALE
Figure Clock Timing
Figure Link Power Mode Timing
tSETUP
RESET
BIT_CLK SYNC SDATA_OUT
SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK HI-Z
tHOLD
tOFF
Figure Data Setup Hold
Figure Test Mode
REV.
AD1886A
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter Power Supplies Digital (DVDD) Analog (AVCC) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
-0.3 -0.3 -0.3 -0.3
+3.6 +6.0 10.0 AVDD DVDD +150
Unit Model
Temperature Range
Package Description 48-Lead LQFP
Package Option* ST-48
AD1886AJST 70°C
Thin Quad Flatpack.
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Ambient Temperature Rating TAMB TCASE TCASE Case Temperature Power Dissipation Thermal Resistance (Case-to-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Package LQFP
76.2°C/W
17°C/W
59.2°C/W
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD1886A features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD1886A
CONFIGURATION
HP_OUT_R HP_OUT_L MONO_OUT
SPDIF
AVDD3
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP
AVDD2
AVSS3
AVSS2
IDENTIFIER
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
AD1886A
VIEW (Not Scale)
CD_GND_REF
LINE_IN_L
PHONE_IN
CONNECT
FUNCTION DESCRIPTIONS Digital
Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET SPDIF
CHIP SELECTS
LQFP
Description Crystal Clock) Input, 24.576 MHz. Crystal Output AC-Link Serial Data Output, AD1886A Input Stream. AC-Link Clock. 12.288 Serial Data Clock. Daisy-Chain Output Clock. AC-Link Serial Data Input. AD1886A Output Stream. AC-Link Frame Sync AC-Link Reset. AD1886A Master Reset. SPDIF Output
Name
LQFP
Type
Description Chip Select Input (Active Low) Chip Select Input (Active Low)
JACK SENSE/GENERAL-PURPOSE DIGITAL OUTPUT
used sense presence audio plug output jacks automatically mute MONO and/or LINE_OUT audio outputs. Alternatively, programmed general-purpose digital output pin. Name LQFP Type Description JACK SENSE Input, GPIO.
LINE_IN_R
AUX_L
AUX_R
CD_L
CD_R
MIC1
VIDEO_L
VIDEO_R
MIC2
REV.
AD1886A
Analog
These signals connect AD1886A component analog sources sinks, including microphones speakers. Name PC_BEEP PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R
Filter/Reference
LQFP
Description Beep. Speaker beep passthrough. Phone. From telephony subsystem speakerphone handset. Auxiliary Input Left Channel Auxiliary Input Right Channel Video Audio Left Channel Video Audio Right Channel Audio Left Channel Audio Analog Ground Reference Input Audio Right Channel Microphone Desktop microphone input. Microphone Second microphone input. Line Left Channel. Line Right Channel. Line Out, Left Channel. Line Out, Right Channel. Monaural Output Telephony Subsystem Speakerphone Headphones Out, Left Channel. Headphones Out, Right Channel.
These signals connected resistors, capacitors, specific voltages. Name VREF VREFOUT AFILT1 AFLIT2 FILT_R FILT_L RX3D CX3D LQFP Description Voltage Reference Filter Voltage Reference Output Drive. (Intended Bias.) Antialiasing Filter Capacitor-ADC Right Channel. Antialiasing Filter Capacitor-ADC Left Channel. AC-Coupling Filter Capacitor-ADC Right Channel. AC-Coupling Filter Capacitor-ADC Left Channel. Phat Stereo Enhancement-Resistor. Phat Stereo Enhancement-Capacitor.
Power Ground Signals
Name DVDD1 DVSS1 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3
Connects
LQFP
Type
Description Digital Digital Digital Digital Analog Analog Analog Analog Analog Analog
Name
LQFP
Type
Description Connect
REV.
AD1886A
SPDIF
AD1886A
MIC1 MIC2
SPDIF JACK SENSE 0x72 0x3A 0x2A 0x28 0x72
0x20
0dB/20dB 0x0E
LS/RS 0x1C LS/RS 0x1C LS/RS
LINE_IN
0x1C
16-BIT
VIDEO PHONE_IN
0x1C
16-BIT
RESET
0x1A
SYNC 0x0C 0x0C 0x04 0x04 0x02 0x06 0x02 0x04 0x0A 0x18 0x0E 0x10 0x12 0x16 0x14 SDATA_IN 0x0E 0x10 0x12 0x16 0x14
LINK
BIT_CLK
SDATA_OUT
HP_OUT_L
0x02
LINE_OUT_L
0x06
0x22 POP3D
16-BIT
0x20
0x22 POP3D
MONO_OUT 0x02 0x04
0x20 SWITCH
LINE_OUT_R
0x18
16-BIT
HP_OUT_R
PC_BEEP
0x0A
OSCILLATORS
XTL_OUT
XTL_IN
Figure Block Diagram Register
-10-
REV.
AD1886A
Indexed Control Registers
Name Reset Master Volume Headphones Volume Master Volume Mono Reserved Beep Volume Phone-In Volume Volume Line-In Volume Volume Video Volume Volume Record Select Record Gain General-Purpose Control Power-Down Ctrl/Stat Ext'd Audio Ext'd Audio Stat/Ctrl SR14 LMV5 LHV5 SR13 LMV4 LHV4 LLV4 LCV4 LVV4 LAV4 LOV4 SR12 LMV3 LHV3 LLV3 LCV3 LVV3 LAV3 LOV3 LIM3 SR11 RMV3 RHV3 MMV3 PCV2 PHV3 MCV3 RLV3 RCV3 RVV3 RAV3 ROV3 RIM3 RMV2 RHV2 Default 0410h 8000h 8000h
LMV2 LMV1 LMV0 LHV2 LLV2 LCV2 LVV2 LAV2 LOV2 LIM2 SPCV SR10 LHV1 LLV1 LCV1 LVV1 LAV1 LOV1 LIM1 LHV0 LLV0 LCV0 LVV0 LAV0 LOV0 LIM0
RMV5 RMV4 RHV5 RHV4 MMV4 PCV3 PHV4 MCV4 RLV4 RCV4 RVV4 RAV4 ROV4
RMV1 RMV0 RHV1 RHV0
MMV2 MMV1 MMV0 8000h PCV1 PHV2 MCV2 RLV2 RCV2 RVV2 RAV2 ROV2 RIM2 SPDF PCV0 8000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Xh 0005h 0000h BB80h
PHV1 PHV0 MCV1 MCV0 RLV1 RLV0
RCV1 RCV0 RVV1 RVV0
RAV1 RAV0 ROV1 ROV0 RIM1 RIM0
LPBK
SPSA1 SPSA0
SPDIF
2Ch/ Rate (SR1) SR15 (7Ah)* 32h/ Rate (SR0) SR15 (78h)* SPDIF Control Jack Sense/SPDIF Serial Configuration Misc Control Bits SPMIX
SR14
SR13
SR12
SR11
SR10
BB80h
JSOD
SPSR1 SPRZ
SPSR0 JSPD
JSOE
JSLM
ALSR
COPY DRSR
ARSR
0000h 0000h 7000h 0404h
JSMM SRX8 REV5
SLOT16 REGM2 REGM1 REGM0 DRQEN DACZ LPMIX DLSR
SRX1
Vendor Vendor
REV4
REV3
REV2
REV1
REV0
4144h 5363h
REV7 REV6
NOTES registers shown bits containing assumed reserved. register addresses aliased next lower even address. Reserved registers should written. Zeros should written reserved bits. *Indicates Aliased register AD1819, AD1819A backward compatibility
REV.
-11-
AD1886A
Reset (Index 00h)
Name Reset Default 0410h
Note: Writing value this register performs register reset, which causes registers revert their default values (except 74h, which forces serial configuration). Reading this register returns code part code type Stereo Enhancement. ID[9:0] Identify Capability. decodes capabilities AD1886A based following: SE[4:0]
Function Dedicated Channel Modem Line Codec support Bass Treble Control Simulated Stereo (Mono Stereo) Headphone Support Loudness (Bass Boost) Support 18-Bit Resolution 20-Bit Resolution 18-Bit Resolution 20-Bit Resolution
AD1886A*
*The AD1886A contains none optional features identified these bits.
Stereo Enhancement. stereo enhancement identifies Analog Devices stereo enhancement.
Master Volume Registers (Index 02h)
Name Master Volume Default
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
RMV[5:0] LMV[5:0]
Right Master Volume Control. least significant represents This register controls output from maximum attenuation -94.5 Left Master Volume Control. least significant represents This register controls output from maximum attenuation -94.5 Master Volume Mute. When this "1," channel muted. xMV5 xMV0 0000 1111 1111 xxxx Function Attenuation -46.5 Attenuation -94.5 Attenuation Attenuation
-12-
REV.
AD1886A
Headphones Volume Registers (Index 04h)
Name Headphone Volume LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 Default RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h
RHV[5:0] LHV[5:0]
Right Headphone Volume Control. least significant represents This register controls output from maximum attenuation -88.5 Left Headphone Volume Control. least significant represents This register controls output from maximum attenuation -88.5 Headphones Volume Mute. When this "1," channel muted. xHV5 xHV0 0000 1111 1111 xxxx Function Gain -40.5 Attenuation -88.5 Attenuation Attenuation
Master Volume Mono (Index 06h)
Name Master Volume Mono Default
MMV5 MMV4 MMV3 MMV2 MMV1 MMV0 8000h
MMV[5:0]
Mono Master Volume Control. least significant represents This register controls output from maximum attenuation -94.5 Mono Master Volume Mute. When this "1," channel muted.
Beep Register (Index 0Ah)
Name PC_BEEP Volume Default 8000h
PCV3 PCV2 PCV1 PCV0
PCV[3:0]
Beep Volume Control. least significant represents attenuation. This register controls output from maximum attenuation Beep routed Left Right Line outputs even when AD1886A RESET State. This Power-On Self-Test (POST) codes heard user case hardware problem with Beep Mute. When this "1," channel muted. PCV3 PCV0 0000 1111 xxxx Function Attenuation Attenuation Attenuation
REV.
-13-
AD1886A
Phone Volume (Index 0Ch)
Name Phone Volume Default
PHV4 PHV3 PHV2 PHV1 PHV0 8008h
PHV[4:0]
Name Volume
Phone Volume. Allows setting Phone Volume Attenuator steps. represents range -34.5 default value mute enabled. Phone Mute. When this "1," channel muted.
Volume (Index 0Eh)
MCV4 MCV3 MCV2 MCV1 MCV0 Default 8008h
MCV[4:0]
Volume Gain. Allows setting Volume attenuator steps. represents range -34.5 default value mute enabled. Microphone Gain Block Disabled; Gain Enabled; Gain Mute. When this "1," channel muted.
Name
Line Volume (Index 10h)
RLV4 RLV3 RLV2 RLV1 RLV0 Default 8808h
Line Volume
LLV4 LLV3 LLV2 LLV1 LLV0
RLV[4:0] LLV[4:0]
Name
Right Line Volume. Allows setting Line right channel attenuator steps. represents range -34.5 default value mute enabled. Left Line Volume. Allows setting Line left channel attenuator steps. represents range -34.5 default value mute enabled. Line Mute. When this "1," channel muted.
Volume (Index 12h)
Default
Volume
LCV4 LCV3 LCV2 LCV1 LCV0
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0] LCV[4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Volume Mute. When this "1," channel muted.
-14-
REV.
AD1886A
Video Volume (Index 14h)
Name Default
Video Volume
LVV4 LVV3 LVV2 LVV1 LVV0
RVV4 RVV3 RVV2 RVV1 RVV0 8808h
RVV[4:0] LVV[4:0]
Name Volume
Right Video Volume. Allows setting Video right channel attenuator steps. represents range -34.5 default value mute enabled. Left Video Volume. Allows setting Video left channel attenuator steps. represents range -34.5 default value mute enabled. Video Mute. When this "1," channel muted.
Volume (Index 16h)
Default
LAV4 LAV3 LAV2 LAV1 LAV0
RAV4 RAV3 RAV2 RAV1 RAV0 8808h
RAV[4:0] LAV[4:0]
Name Volume
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Mute. When this "1," channel muted.
Volume (Index 18h)
Default
LOV4 LOV3 LOV2 LOV1 LOV0
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
ROV[4:0] LOV[4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Volume Mute. When this "1," channel muted.
Volume Table (Index 18h)
Mute
00000 01000 11111 xxxxx
Function Gain Gain -34.5 Gain Gain
REV.
-15-
AD1886A
Record Select Control Register (Index 1Ah)
Name Default 0000h
Record Select
RS[2:0] LS[2:0]
Right Record Select Left Record Select
Used select record source independently right left. table legend. default value 0000h, which corresponds Right Record Source CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mono PHONE_IN
Record Gain (Index 1Ch)
Name Record Gain LIM3 LIM2
Left Record Source CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mono PHONE_IN
LIM0
RIM3
RIM2
RIM1
RIM0
Default 8000h
LIM1
RIM[3:0] LIM[3:0]
Right Input Mixer Gain Control. Each represents 0000 range +22.5 Left Input Mixer Gain Control. Each represents 0000 range +22.5 Input Mute Unmuted Muted Gain xIM3 xIM0 1111 0000 xxxxx Function +22.5 Gain Gain Gain
-16-
REV.
AD1886A
General-Purpose Register (Index 20h)
Name Default
General-Purpose
LPBK
Note: This register should read before writing generate mask only bit(s) that need changed. function default value 0000h, which off. LPBK Loopback Control. ADC/DAC digital loopback mode. Select Mic1 Mic2 Mono Output Select Phat Stereo Enhancement Phat Stereo off. Phat Stereo Output Path Mute. controls optional bypass path (the post paths mutually exclusive). post
Control Register (Index 22h)
Name Control Default 0000h
DP[3:0]
Depth Control. Sets "Depth" Phat Stereo enhancement according table below. Depth 6.67% 93.33% 100%
REV.
-17-
AD1886A
Subsection Ready Register (Index 26h)
Name Default
Power-Down Cntrl/Stat
Note: ready bits read only; writing REF, ANL, DAC, will have effect. These bits indicate status AD1886A subsections. one, that subsection "ready." Ready defined subsection able perform nominal state. PR[6:0] section ready transmit data. section ready accept data. Analog gainuators, attenuators, mixers ready. Voltage References, VREF VREFOUT nominal level. AD1886A Power-Down Modes. first three bits used individually rather than combination with each other. last bit, PR3, used combination with itself. mixer reference cannot powered down unless ADCs DACs also powered down. Nothing else powered until reference PR0-Power-Down PR1-Power-Down PR2-Power-Down Analog Mixer PR3-Power-Down VREF VREFOUT PR4-Power-Down AC-Link PR5-Power-Down Internal Clock PR6-Power-Down Headphone effect unless ADCs, DACs, AC-Link powered down. reference mixer either down, power-up sequences must allowed completion before both set. multiple-codec systems, master codec's bits control slave codec. also effective slave codec master's clear, effect except enable disable PR5. Power-Down State Power-Down Power-Down Power-Down Mixer Power-Down Mixer Power-Down Mixer Power-Down Mixer Power-Down Standby
Extended Audio Register (Index 28h)
Name Extended Audio SPDF Default 0001h
Note: Extended Audio read only register. SPDF ID[1:0] Variable Rate Audio. indicates support Variable Rate Audio. indicates SPDIF support, indicates SPDIF support. ID1, 2-bit field which indicates codec configuration.
-18-
REV.
AD1886A
Extended Audio Status Control Register (Index 2Ah)
Name SPSA1 SPSA0 Default 0000h
Ext'd Audio Stat/Ctrl
SPCV
SPDIF
Note: Extended Audio Status Control Register read/write register that provides status control extended audio features. SPDIF SPSA[1,0] Variable Rate Audio. enables Variable Rate Audio mode (sample rate control registers SLOTREQ signaling. SPDIF transmitter subsystem enable/disable bit: indicates SPDIF enabled, indicates SPDIF disabled. SPDIF Slot Assignment: SPSA[1, SPDIF uses AC-LINK slots SPSA[1, SPDIF uses AC-LINK slots SPSA[1, SPDIF uses AC-LINK slots SPSA[1, Reserved. SPDIF Configuration Valid: (Read Only) indicates current SPDIF configuration (SPA, SPR, DAC-Rate) supported. indicates current SPDIF configuration (SPA, SPR, DAC-Rate) supported.
SPCV
Rate Register (Index 2Ch)
Name SR15 SR14 SR13 SR12 SR11 SR10 Default
2Ch/(7Ah) Rate
BB80h
Note: alias 7Ah. register must alias work; zero written VRA, both sample rates reset kHz. SR[15:0] Writing this register allows programming sampling frequency from (1B58h) (BB80h) increments. Programming value outside range 7040 (1b80h) 48000 (bb80h) causes codec saturate. rates, value written register supported, that value will echoed back when read; otherwise, closest rate supported returned.
Rate Register (Index 32h)
32h/(78h) Name Rate SR15 SR14 SR13 SR12 SR11 SR10 Default
BB80h
Note: alias 78h. register must alias work; zero written then both sample rates reset kHz. SR[15:0] Writing this register allows programming sampling frequency from (1B58h) (BB80h) increments. Programming value outside range 7040 (1b80h) 48000 (bb80h) causes codec saturate. rates, value written register supported, that value will echoed back when read; otherwise, closest rate supported returned.
REV.
-19-
AD1886A
SPDIF Control Register (Index 3Ah)
Name Default
SPDIF Control
SPSR1 SPSR0
COPY 0000h
Note: Register read/write register that controls SPDIF functionality manages fields propagated channel status subframe case). With exception this register should only written when SPDIF transmitter disabled (SPDIF register "0"). This ensures that control status information startup correctly beginning SPDIF transmission. COPY CC[6-0] SPSR[1,0] Professional: indicates Professional channel status, Consumer. Non-Audio: indicates data format, data PCM. Copyright: indicates copyright asserted, copyright asserted. Preemphasis: indicates filter preemphasis 50/15 preemphasis none. Category Code: Programmed according standards, appropriate. Generation Level: Programmed according standards, appropriate. SPDIF Transmit Sample Rate: SPSR[1:0] "00" Transmit Sample Rate 44.1 kHz. SPSR[1:0] "01" Reserved. SPSR[1:0] "10" Transmit Sample Rate kHz. SPSR[1:0] "11" Transmit Sample Rate kHz. Validity: This affects "Validity flag," <28> transmitted each subframe enables SPDIF transmitter maintain connection during error mute conditions. Each SPDIF subframe <28> "1." This tags both samples valid. Each SPDIF subframe <28> valid data invalid data (error condition).
Jack Sense/SPDIF Register (Index 72h)
JSLM efau
SPRZ JSPD
0000h
Note: register bits read/write except JSI, VWI, which read only. Indicates that Jack Sense generated interrupt. Must enabled remains until software clears bit. Indicates Voice Wake Interrupt occurred. Jack Sense Mode: Interrupt Mode (Software intervention required). Jack Sense Mode Hardware asserted Mono/Line Muting). JSMM Jack Sense Mono Mute: Setting this enables Jack Sense mute Mono output. Jack Sense Clear: Setting this clears Jack Sense interrupt (only needed when Jack Sense Disabled: Setting this disables Jack Sense functionality. JSLM Jack Sense Line Mute: Setting this enables Jack Sense mute LINE_OUT output. JSOE Jack Sense Output Enable: Setting this allows operate GPIO (output mode only). JSPD Jack Sense Pull-up Disable: Setting this disables internal Jack Sense pull-up. JSOD Jack Sense Output Data: Data this transferred JSOE (otherwise effect). SPRZ SPDIF Return Zero under run. SPDIF Repeat last sample under run. SPMIX SPDIF Transmits output ADC. SPDIF Transmits AC-Link Time Slot Data.
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REV.
AD1886A
Serial Configuration (Index 74h)
Name Default
Serial SLOT REGM2 REGM1 REGM0 Configuration
DHWR
Note: This register reset when reset register (Register 00h) written. DHWR REGM0 REGM1 REGM2 SLOT16 Disable Hardware Reset Master Codec Register Mask Slave Codec Register Mask Slave Codec Register Mask Enable 16-bit slots.
your system uses only single AD1886A, ignore register mask bits. SLOT16 makes Link slots bits length, formatted into slots.
Miscellaneous Control Bits (Index 76h)
Name Default
LPMI Misc Control Bits
DLSR
ALSR
SRX10 SRX8
DRSR
ARSR 0000h
ARSR
Right Sample Generator Select Selected (32h) Selected (2Ch) Right Sample Generator Select Selected (32h) Selected (2Ch) Multiply rate Multiply rate 10/7. SRX10D7 SRX8D7 mutually exclusive; SRX10D7 priority both set. Modem filter enable (left channel only). Change only when DACs powered down. Left Sample Generator Select Selected (32h) Selected (2Ch) Left Sample Generator Select Selected (32h) Selected (2Ch) Digital Mono Select Mixer Left Right Digital Audio Mode. Outputs bypass analog mixer sent directly codec output. Low-Power Mixer Zero-fill (vs. repeat) starved data.
DRSR
SRX8D7 SRX10D7 MODEN ALSR
DLSR
LPMIX DACZ
REV.
-21-
AD1886A
Sample Rate (Index 78h)
Name Default
(32h)/78h Sample Rate SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h
Note: alias 78h. register must alias work; zero written then both sample rates reset kHz. SR0[15:0] Writing this register allows user program sampling frequency from (1B58h) (BB80h) Hertz increments. Programming value greater than less than cause unpredictable results.
Sample Rate (Index 7Ah)
Name Default
(2Ch)/7Ah Sample Rate SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: alias 7Ah. register must alias work; zero written then both sample rates reset kHz. SR1[15:0] Writing this register allows user program sampling frequency from (1B58h) (BB80h) Hertz increments. Programming value greater than less than cause unpredictable results.
Vendor Register (Index 7Ch)
Name Vendor Default 4144h
S[7:0] F[7:0]
This register ASCII encoded `A.' This register ASCII encoded `D.'
Vendor Register (Index 7Eh)
Name Vendor REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 Default 5363h
T[7:0]
This register ASCII encoded `S.'
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REV.
AD1886A
AVDD NOTE USED, GROUND JACK SENSE PIN. (PIN
DVDD
SPDIF AVSS3 AVDD3
22pF
24.576MHz 22pF
HP_OUT_R AVSS2 HP_OUT_L AVDD2 MONO_OUT
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP
AD1886A
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
SDATA_OUT SDATA_IN SYNC RESET BIT_CLK 47pF
PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R
47nF 270pF
270pF
AVDD
CONNECT 600Z NOTE UNUSED ANALOG INPUTS (LINE_IN_L/R, VIDEO_L/R, MIC1, MIC2, PC_BEEP, PHONE_IN, CD_L/R/GND) MUST LEFT UNCONNECTED.
Figure Recommended Power Connections, Decoupling Support Components
SPDIF TRANSMITTER OUTPUT CONNECTION
codec SPDIF output located This weak internal pull-up that allows detection SPDIF connector hardware power-up automatically enables disables SPDIF transmitter. This feature allows system manufacturers populate depopulate SPDIF connector hardware according their requirements. When output simply left open (NC) strapped high pull-up resistor, internal sense circuitry disables SPDIF transmitter. This condition prevents SPDIF enable Register from being enabled. When output strapped pull-down resistor less), SPDIF transmitter enabled SPDIF enable Register asserted. following circuits (Figure Figure describe ways provide SPDIF connection codec.
SPDIF (CODEC 8.2k INPUT SPDIF (CODEC JACK
(LOGIC)
3.3V BUFFER (CAPABLE 12mA DRIVE)
TOTX173 TOSLINK
CONNECT
Figure SPDIF Output Connection Using Optical Link
Figure SPDIF Output Connection Using Electrical Link
REV.
-23-
AD1886A
first option consists optical link using TOSLINK fiber-optic transmitting module. typical offering TOSHIBA TOTX173 module mounted applications. This module drive fiber optic cables meters long, depending cable hardware used. This solution offers compatibility with state audio systems provides excellent common-mode rejection noise immunity. sets current level internal allows SPDIF transmitter enabled power-up. Note that TOSLINK module requires logic supply). second method uses electrical connection matching requirements IEC958 "Digital Audio Interface" consumer products. This method uses coax cable connecting medium, with type connectors both ends. transmission distance least meters depending hardware used. nominal electrical levels with required bandwidth MHz. ratio transformer used galvanic isolation improved common-mode noise rejection. provide proper signal amplitude impedance matching. allows SPDIF transmitter enabled power-up.
JACK SENSE OPERATION
AD1886A features Jack Sense (JS) that used with HP_OUT LINE_OUT jacks automatically mute other audio outputs. When Jack Sense connected output jacks, AD1886A sense whether audio plug been inserted into jack automatically mute LINE_OUT MONO_OUT both outputs. should normally connected HP_OUT jack automatically mute MONO_OUT LINE_OUT audio signals, alternatively connected LINE_OUT jack automatically mute MONO_OUT signal. action programmed setting JSLM JSMM bits Jack Sense Register (72h). following table summarizes Jack Sense operation:
Table Jack Sense Operation Table
JSLM (Reg 72h, Bit)
JSMM (Reg 72h, Bit)
State HIGH (PLUG INSERTED) LINE_OUT MONO_OUT LINE_OUT MONO_OUT MUTE LINE_OUT MUTE MONO_OUT LINE_OUT MUTE MONO_OUT MUTE
State (PLUG REMOVED) LINE_OUT MONO_OUT LINE_OUT MONO_OUT LINE_OUT MONO_OUT LINE_OUT MONO_OUT
Jack Sense functionality enabled default codec power-up (JSD however JSLM JSMM bits zero, therefore muting action enabled both outputs. JSLM JSMM bits have configured software configuration file desired muting action. Jack Sense active high contains active internal pull-up. Jack Sense input going used, should pulled down digital ground using resistors.
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REV.
AD1886A
CONNECTING JACK SENSE OUTPUT JACKS Headphone Jack
diagram Figure shows preferred method connect Jack Sense line HP_OUT jack. This scheme requires stereo jack with normally closed isolated single switch. switch holds Jack Sense line (grounded) until audio plug inserted, causing switch open Jack Sense line high codec internal pull-up. resistors keep electrolytic output caps properly polarized while HP_OUT jack used.
NOTE: LOCATE CLOSE CODEC. JACK SENSE LINE
CODEC (PIN
FROM CODEC HP_OUT_R (PIN FROM CODEC HP_OUT_L (PIN
OPTIONAL COMPONENTS 600Z
ISOLATED SWITCH
600Z 470pF 470pF
HEADPHONE
Figure Jack Sense Connection HP_OUT Jack, Using Isolated Switch
Alternatively, when audio output jack containing isolated switch available, circuit shown Figure used. While audio plug out, this circuit keeps Jack Sense line state low, pull-down effect (with audio present) tracking lower peaks HP_OUT audio signal. Once audio plug inserted jack switch opens, Jack Sense line switches high state codec internal pull-up, which quickly charges DVDD. resistors also keep electrolytic output caps properly polarized while HP_OUT jack used.
NOTE: LOCATE CLOSE CODEC. JACK SENSE CODEC (PIN CERAMIC MMBD914 OPTIONAL COMPONENTS FROM CODEC HP_OUT_R (PIN FROM CODEC HP_OUT_L (PIN 470pF 470pF 600Z 600Z
HEADPHONE
Figure Jack Sense Connection HP_OUT Jack, Using Nonisolated Switch
LINE JACK
Although shown, LINE_OUT jack used Jack Sense functionality desired with this jack, LINE_OUT jack should wired similar configuration shown above HP_OUT jack (preferably Figure 12). recommend that this case output coupling caps (C2, other values should kept same.
REV.
-25-
AD1886A
APPLICATION CIRCUITS
CD-ROM CONNECTIONS
Typical CD-ROM drives generate output require voltage divider compatibility with Codec input range). recommended circuit group divide-by-two voltage dividers shown Figure CD_GND_REF used cancel differential ground noise from CD-ROM. optimal noise cancellation, this section divider should have approximately half impedance Right Left channel section dividers.
VOLTAGE DIVIDER 4.7k 4.7k HEADER AUDIO (LGGR) 2.7k 2.7k 4.7k 4.7k AC-COUPLING 0.33 CODEC CD_L INPUT
0.33 CODEC CD_GND_REF INPUT
0.33 CODEC CD_R INPUT
Figure Typical CD-ROM Audio Connections
LINE_IN, AUX, VIDEO INPUT CONNECTIONS
Most audio sources also generate audio level require input voltage divider compatible with Codec inputs. Figure shows recommended application circuit. applications requiring compliance, components should configured selected provide adequate immunity emissions control.
COMPONENTS LINE/AUX/VIDEO INPUT 600Z 470pF 600Z 470pF 4.7k 4.7k VOLTAGE DIVIDER 4.7k 4.7k AC-COUPLING 0.33 CODEC RIGHT CHANNEL INPUT
0.33 CODEC LEFT CHANNEL INPUT
Figure LINE_IN, VIDEO Input Connections
MICROPHONE CONNECTIONS
AD1886A contains internal microphone preamp with gain; most cases direct microphone connection shown Figure adequate. microphone level low, external preamp added shown Figure either case microphone bias derived from codec's internal reference (VREFOUT) using resistor. preamp circuit, VREFOUT signal also provide midpoint bias amplifier. meet PC99 1.0A requirements, signal should placed microphone jack bias ring. This configuration supports electret microphones with three conductor plugs well dynamic microphones with conductor plugs (ring sleeve shorted together). Additional filtering required limit microphone response audio band interest.
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REV.
AD1886A
COMPONENTS INPUT 600Z 470pF 600Z 470pF BIAS 2.2k FROM CODEC VREFOUT AC-COUPLING 0.22 CODEC MIC1 MIC2 INPUT
Figure Recommended Microphone Input Connections
PREAMP COMPONENTS INPUT 600Z 470pF 600Z 470pF BIAS 2.2k AC-COUPLING 0.22 AD8531 100k AVDD
AC-COUPLING 0.22 CODEC MIC1 MIC2 INPUT
FROM CODEC VREFOUT
Figure Microphone with Additional External Preamp Gain)
LINE OUTPUT CONNECTIONS
AD1886A Codec provides stereo LINE_OUT signals standard level. These signals must ac-coupled before they connected external load. After ac-coupling, minimal resistive load recommended keep capacitors properly biased reduce clicks pops when plugging stereo equipment into output jack. capacitor values should selected provide desired frequency response, taking into account nominal impedance external load. meet PC99 specification PCs, testing must performed with load, therefore minimum value recommended achieve less than roll-off
STEREO LINE_OUT JACK 600Z 470pF 600Z 470pF
FROM CODEC LINE_OUT_R
FROM CODEC LINE_OUT_L
Figure Recommended LINE_OUT Connections
BEEP INPUT CONNECTIONS
recommended BEEP input circuit shown below. Under most cases PC_BEEP signal should attenuated, filtered then ac-coupled into Codec.
PC_BEEP (FROM ICH)
CODEC PC_BEEP INPUT
Figure Recommended PC_BEEP Connections
REV.
-27-
AD1886A
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48)
0.063 (1.60) 0.030 (0.75) 0.018 (0.45)
0.354 (9.00)
VIEW
(PINS DOWN)
0.276 (7.00)
COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09)
0.019 (0.5) 0.011 (0.27) 0.006 (0.17) 0.006 (0.15) SEATING 0.002 (0.05) PLANE 0.057 (1.45) 0.053 (1.35)
CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
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REV.
PRINTED U.S.A.
C02411-0-10/01(0)

AC'97 SoundMAX Codec AD1886A Stereo Line Level Outputs Mono Outpu

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