AC'97 SoundMAX® Codec AD1885 ENHANCED FEATURES Full Duplex Variab

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AC'97 SoundMAX® Codec AD1885 ENHANCED FEATURES Full Duplex Variab

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AC'97 FEATURES Variable Sample Rate Audio Multiple Codec Configuration Options External Audio Power-Down Control
AC'97 SoundMAX® Codec AD1885
ENHANCED FEATURES Full Duplex Variable Sample Rates from 7040 with Resolution Jack Sense Pins Provide Automatic Output Switching Software-Enabled VREFOUT Output Microphones External Power Split Power Supplies (3.3 Digital/5 Analog) Mobile Low-Power Mixer Mode Extended 6-Bit Master Volume Control Extended 6-Bit Headphone Volume Control Digital Audio Mixer Mode PHATStereo Stereo Enhancement
AC'97 FEATURES AC'97 2.1-Compliant Greater than Dynamic Range Stereo Headphone Amplifier Multibit Converter Architecture Improved Ratio Greater than 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs for: LINE-IN, VIDEO, Analog Line-Level Mono Inputs Speakerphone BEEP Mono Input w/Built-In Preamp, Switchable from External Sources High Quality Input with Ground Sense Stereo Line-Level Outputs Mono Output Speakerphone Internal Speaker Power Management Support 48-Terminal LQFP Package FUNCTIONAL BLOCK DIAGRAM
JS0/EAPD
AD1885
CHIP SELECT MIC1 MIC2 LINE
SELECTOR
JACK SENSES EAPD CTRL
VREF
VREFOUT
0dB/ 20dB
VIDEO PHONE_IN
16-BIT CONVERTER
16-BIT CONVERTER
RESET
SYNC MONO_OUT PHAT STEREO 16-BIT CONVERTER
LINK
SAMPLE RATE GENERATORS
BIT_CLK
HP_OUT_L
SDATA_OUT
LINE_OUT_L
SDATA_IN
LINE_OUT_R
PHAT STEREO GAIN ATTENUATE MUTE MASTER VOLUME HEADPHONE VOLUME
16-BIT CONVERTER
HP_OUT_R
OSCILLATOR
PC_BEEP
XTL_OUT XTL_IN
SoundPort registered trademark PHAT trademark Analog Devices, Inc.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
AD1885-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (DVDD) Analog Supply (AVDD) Sample Rate (FS) Input Signal Analog Output Passband 1008 Test Conditions Calibrated Attenuation Relative Full Scale Input Output Load (LINE_OUT) Output Load (HP_OUT) Test Conditions Calibrated Gain Input -3.0 Relative Full Scale ANALOG INPUT Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, VIDEO, PHONE_IN, PC_BEEP with Gain (M20 with Gain (M20 Input Impedance* Input Capacitance*
MASTER VOLUME
2.83 0.283 2.83
Unit
Parameter Step Size -94.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range Span* Step Size -46.5 dB); MONO_OUT Output Attenuation Range Span* Step Size -88.5 dB); HP_OUT_R, HP_OUT_L Output Attenuation Range Span* Mute Attenuation Fundamental*
PROGRAMMABLE GAIN AMPLIFIER-ADC
-94.5 -46.5 -94.5
Unit
Parameter Step Size 22.5 Gain Range Span
ANALOG MIXER-INPUT GAIN/AMPLIFIERS/ATTENUATORS
22.5
Unit
Parameter Signal-to-Noise Ratio (SNR) LINE_OUT Other LINE_OUT Step Size (+12 -34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, VIDEO, PHONE_IN, Input Gain/Attenuation Range: MIC, LINE, AUX, VIDEO, PHONE_IN, Step Size dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP
Guaranteed, tested.
-46.5
Unit
REV.
AD1885
DIGITAL DECIMATION INTERPOLATION FILTERS*
Parameter Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband
ANALOG-TO-DIGITAL CONVERTERS
0.09 12/FS
Unit
Parameter Resolution Total Harmonic Distortion (THD Dynamic Range (-60 Input THD+N Referenced Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Crosstalk* Line Inputs (Input Ground Read Input Ground Read LINE_IN Other Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Offset Error
DIGITAL-TO-ANALOG CONVERTERS
-100
Unit Bits
Parameter Resolution Total Harmonic Distortion (THD) LINE_OUT Total Harmonic Distortion (THD) HP_OUT (With Load) Dynamic Range LINE_OUT (-60 Input THD+N Referenced Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Crosstalk* (Input Zero Measure R_OUT; Input Zero Measure L_OUT) Total Audible Out-of-Band Energy (Measured from kHz)*
ANALOG OUTPUT
Unit Bits
-100
Parameter Full-Scale Output Voltage; LINE_OUT Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance Full-Scale Output Voltage; HP_OUT Gain) Output Capacitance* External Load Capacitance VREF VREFOUT VREFOUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale Output)
*Guaranteed, tested.
2.83
Unit
2.45
2.05
2.25 2.25
REV.
AD1885-SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS*
Parameter High-Level Input Voltage (VIH): Digital Inputs Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH), Low-Level Output Voltage (VOL), Input Leakage Current Output Leakage Current
POWER SUPPLY
0.65 DVDD DVDD
Unit
0.35 DVDD DVDD
Parameter Power Supply Range-Analog (AVDD) Power Supply Range-Digital (DVDD) Power Dissipation-5 V/3.3 Analog Supply Current-5 (AVDD) Digital Supply Current-3.3 (DVDD) Power Supply Rejection (100 Signal kHz)* Both Analog Digital Supply Pins, Both ADCs DACs)
CLOCK SPECIFICATIONS
4.75 3.15
5.25 3.45
Unit
Parameter Input Clock Frequency Recommended Clock Duty Cycle
POWER-DOWN MODE*
24.576
Unit
Parameter Mixer (Analog Mixer Mixer Mixer Mixer Analog Only (AC-Link Analog Only (AC-Link Off) Standby Headphone Standby
Bits PR1, LPMIX, PR1, PR2, PR2, PR2, PR1, LPMIX, PR5, PR1, LPMIX, PR1, PR0, PR4, PR5, PR4, PR3, PR2, PR1,
DVDD (3.3
AVDD
Unit
NOTES *Guaranteed, tested. Output jitter directly dependent crystal input jitter. Specifications subject change without notice.
REV.
AD1885
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter RESET Active Pulsewidth RESET Inactive BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Pulsewidth SYNC Inactive BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Pulsewidth SYNC Frequency SYNC Period Setup Falling Edge BIT_CLK Hold from Falling Edge BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time Slot BIT_CLK, SDATA_IN Setup Trailing Edge RESET (Applies SYNC, SDATA_OUT) Rising Edge RESET HI-Z Delay Propagation Delay RESET Rise Time Output Valid Delay from Rising Edge BIT_CLK Valid
NOTES *Output jitter directly dependent crystal input jitter. Specifications subject change without notice.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
162.8
19.5
Unit
162.8 12.288 81.4 32.56 32.56 48.0 20.8 48.84 48.84
REV.
AD1885
tRST_LOW
RESET
tRST2CLK
BIT_CLK
tRISECLK
SYNC
tFALLCLK
BIT_CLK
Figure Cold Reset
tRISESYNC
SDATA_IN
tFALLSYNC
tSYNC_HIGH
SYNC BIT_CLK
tRST2CLK
SDATA_OUT
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
Figure Warm Reset
Figure Signal Rise Fall Time
tCLK_LOW
BIT_CLK
tCLK_HIGH tCLK_PERIOD
SYNC
SLOT
SLOT
BIT_CLK
tSYNC_LOW
SYNC
SDATA_OUT
WRITE 0x26
DATA
DON'T CARE
tSYNC_HIGH tSYNC_PERIOD
SDATA_IN
tS2_PDOWN
NOTE: BIT_CLK SCALE
Figure Clock Timing
Figure AC-Link Power Mode Timing
tSETUP
RESET
BIT_CLK
SDATA_OUT
SYNC SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK HI-Z
tHOLD
tOFF
Figure Data Setup Hold
Figure Test Mode
REV.
AD1885
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter Power Supplies Digital (AVDD) Analog (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
-0.3 -0.3 -0.3 -0.3
+3.6 +6.0 AVDD DVDD +150
Unit Model AD1885JST
Temperature Range 70°C
Package Description 48-Lead LQFP
Package Option* ST-48
Thin Quad Flatpack.
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Ambient Temperature Rating TAMB TCASE TCASE Case Temperature Power Dissipation Thermal Resistance (Case-to-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Package LQFP
76.2°C/W
17°C/W
59.2°C/W
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD1885 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
CONFIGURATION
MONO_OUT
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
(EAPD)
HP_OUT_R AVSS2 CD_GND_REF CD_R MIC1
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP
IDENTIFIER
AD1885
VIEW (Not Scale)
VIDEO_R CD_L
PHONE_IN AUX_L
AUX_R VIDEO_L
MIC2
CONNECT
REV.
LINE_IN_L LINE_IN_R
HP_OUT_L AVDD2
AVSS3 AVDD3
AD1885-SPECIFICATIONS
FUNCTION DESCRIPTIONS Digital
Name XTL_IN XTL_OUT SDATA_OUT BIT_ SDATA_IN SYNC RESET
CHIP SELECTS
LQFP
Description Crystal Clock) Input, 24.576 MHz. Crystal Output. AC-Link Serial Data Output, AD1885 Input Stream. AC-Link Clock. 12.288 Serial Data Clock. Daisy Chain Input Clock. AC-Link Serial Data Input. AD1885 Output Stream. AC-Link Frame Sync. AC-Link Reset. AD1885 Master Reset.
Name
LQFP
Type
Description Chip Select Input (Active Low). Chip Select Input (Active Low).
JACK SENSES/EAPD/GENERAL-PURPOSE DIGITAL OUTPUTS
These signals sense presence audio jacks line-out headphones outputs, automatically mute other audio outputs. also programmed EAPD control. Alternatively, both pins programmed general-purpose digital outputs. Name
Analog
LQFP
Type
Description JACK Sense Input (Mutes Mono Output). JACK Sense Input (Mutes Line_Out Mono Outputs, Line_Out Only).
These signals connect AD1885 component analog sources sinks, including microphones speakers. Name PC_BEEP PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R LQFP Description Beep. speaker beep passthrough. Phone Input. From telephony subsystem speakerphone handset. Auxiliary Input Left Channel. Auxiliary Input Right Channel. Video Audio Left Channel. Video Audio Right Channel. Audio Left Channel. Audio Analog Ground Reference Differential Input. Audio Right Channel. Microphone Desktop microphone input. Microphone Second microphone input. Line Left Channel. Line Right Channel. Line Left Channel. Line Right Channel. Monaural Output Telephony Subsystem Speakerphone. Headphones Left Channel. Headphones Right Channel.
REV.
AD1885
Filter/Reference
These signals connected resistors, capacitors, specific voltages. Name VREF VREFOUT AFILT1 AFLIT2 FILT_R FILT_L RX3D CX3D LQFP Description Voltage Reference Filter. Voltage Reference Output Drive (Intended Bias). Antialiasing Filter Capacitor-ADC Right Channel. Antialiasing Filter Capacitor-ADC Left Channel. AC-Coupling Filter Capacitor-ADC Right Channel. AC-Coupling Filter Capacitor-ADC Left Channel. PHAT Stereo Enhancement-Resistor. PHAT Stereo Enhancement-Capacitor.
Power Ground Signals
Name DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3
Connects
LQFP
Type
Description Digital Digital Digital Digital Analog Analog Analog Analog Analog Analog
Name
LQFP
Type
Description Connect
JS0/EAPD
CHIP SELECT MIC1 MIC2 LINE VIDEO PHONE_IN STEREO MONO STEREO 0x20 0x0C 0x0C 0x02 LINE_OUT_L 0x02 LINE_OUT_R 0x02 0x02 0x22 0x22 PHAT 0x20 PHAT 0x20 0x04 HP_OUT_R 0x04 0x0A 0x0A PC_BEEP 0x0E 0x0E 0dB/20dB 0x0E
JACK SENSE EAPD CTRL LS/RS LS/RS LS/RS 0x10 0x10 0x12 0x12 0x16 0x16 0x14 0x14 0x1A
VREF
VREFOUT
0x1C
0x1C RESET
MONO_OUT
AC-LINK
SYNC BIT_CLK SDATA_OUT SDATA_IN
AD1885
0x04 HP_OUT_L
0x04
0x20 SWITCH
0x18
0x18
GAIN ATTENUATION MUTE SELECTOR
OSCILLATORS
XTL_OUT
XTL_IN
Figure Block Diagram Register
REV.
AD1885
PRODUCT OVERVIEW Sample Rates
AD1885 Codec meets Audio Codec Extensions, adding support multiple Codecs variable sample rates. addition, AD1885 SoundPort Codec designed meet requirements Audio Codec '97, Component Specification, Revision 1.03, 1996, Intel Corporation, found www.Intel.com. AD1885 also includes other Codec enhanced features such communicating three Codecs same link, integrated headphone driver built-in PHAT Stereo enhancement. AD1885 analog front high-performance audio, modem, applications. AC'97 architecture defines 2-chip audio solution comprising digital audio controller, plus high-quality analog component that includes Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs), mixer, I/O. main architectural features AD1885 high quality analog mixer section, channels conversion, channels conversion Data Direct Scrambling (D2S) rate generators.
FUNCTIONAL DESCRIPTION
AD1885 default mode sets Codec operate sample rates. converter pairs process left right channel data different sample rates. AD1885 sample rate generator allows Codec instantaneously change process sample rates from 7040 with resolution in-band integrated noise distortion artifacts introduced rate conversions below AD1885 uses 4-bit structure enhance noise immunity motherboards enclosures, suppress idle tones below device's quantization noise floor. process pushes noise distortion artifacts caused errors multibit frequencies beyond auditory response human then filters them.
Digital-to-Analog Signal Path
analog output gained attenuated from -34.5 steps, summed with analog input signals. summed analog signal enters Master Volume stage where each channel mixer output attenuated from -94.5 steps muted.
Analog Outputs
This section overviews functionality AD1885 intended general introduction capabilities device. Detailed reference information found descriptions Indexed Control Registers.
Analog Inputs
AD1885 offers line output controlled Master Volume control integrated headphone driver with independent control.
Host-Based Echo Cancellation Support
Codec contains stereo pair ADCs. Inputs selected from following analog signals: telephony (PHONE_IN), mono microphone (MIC1 MIC2), stereo line (LINE_IN), auxiliary line input (AUX), stereo (CD), stereo audio from video source (VIDEO) post-mixed stereo mono line output (LINE_OUT).
Analog Mixing
AD1885 supports time correlated data format presenting data left channel mono summation left right output right channel. splittable; left right data sampled different rates.
Telephony Modem Support
PHONE_IN, MIC1 MIC2, LINE_IN, AUX, VIDEO mixed analog domain with stereo output from DACs. Each channel stereo analog inputs independently gained attenuated from -34.5 steps. summing path mono inputs (PHONE_IN, MIC1, MIC2 LINE_OUT HP_OUT) duplicates mono channel data both left right LINE_OUT HP_OUT. Additionally, attention signal (PC_BEEP) mixed with line output headphone. switch allows output DACs bypass PHAT Stereo enhancement.
Digital Audio Mode
AD1885 contains V.34-capable analog front supporting host-based data pump modems. modem typical dynamic range over analog output passband where 12.8 kHz. left channel used convert modem data same sample rate range between 7040 kHz. programmed sample rates have resolution AD1885 supports irrational V.34 sample rates with 10/7 selectable multiplier coefficients.
Power Management Modes
AD1885 designed with Digital Audio Mode (DAM) that allows mixing analog inputs, independent output signal path. Mixed analog input signals sent ADCs processing controller host, used during simultaneous capture playback different sample rates.
Analog-to-Digital Signal Path
AD1885 designed meet notebook ACPI power consumption requirements through flexible power management control internal resources. following subsections independently controlled: ADCs Input Power-Down DACs Power-Down Analog Mixer Power-Down Digital Interface Power-Down Internal Clocks Disabled Power-Down VREF Standby Mode Low-Power Mixer Mode-CD Mixer Alive Only Mode Mixer Bypass Mode (Digital Audio) Headphone
selector sends left right channel information programmable gain amplifier (PGA). following selector allows independent gain control each channel entering from +22.5 steps. Each channel independent, process left right channel data different sample rates.
-10-
REV.
AD1885
Indexed Control Registers
Name Reset Master Volume Headphones Volume Master Volume Mono LMV5 LHV5 RMV5 RHV5 RMV4 RHV4 2Ch/ (7Ah)* 32h/ (78h)* Reserved Jack Sense/Audio Interrupt/Status Serial Configuration JS1_ JS0_ 7000h 0000h Rate (SR0) SR15 SR14 SR13 SR12 SR11 SR10 BB80h Reserved Beep Volume Phone Volume Volume Line Volume Volume Video Volume Volume Volume Record Select Record Gain Reserved General Purpose Control Power-Down Cntrl/Stat Extended Audio LLV4 LLV1 LCV1 LVV1 LAV1 LOV1 LIM1 LLV0 LCV0 LVV0 LAV0 LOV0 LIM0 PCV3 PHV4 Default 0410h 8000h 8000h 8000h
LMV4 LMV3 LMV2 LMV1 LHV4 LHV3 LHV2 LHV1
LMV0 LHV0
RMV3 RMV2 RMV1 RMV0 RHV3 RHV2 PCV2 PCV1 RHV1 RHV0 PCV0
8000h 8008h
PHV3 PHV2
PHV1 PHV0
MCV4 MCV3 MCV2 MCV1 MCV0 8008h RLV4 RCV4 RVV4 RAV4 ROV4 RLV3 RLV2 RLV1 RLV0 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Xh 0001h 0000h BB80h
LLV3 LLV2
LCV4 LCV3 LCV2 LVV4 LAV4 LVV3 LVV2 LAV3 LAV2
RCV3 RCV2 RVV3 RVV2
RCV1 RCV0 RVV1 RVV0
RAV3 RAV2 ROV3 ROV2 RIM3 RIM2
RAV1 RAV0 ROV1 ROV0 RIM1 RIM0
LOV4 LOV3 LOV2 SR12
LIM3 LIM2 SR11 SR10
LPBK
Extended Audio Stat/Ctrl Rate (SR1) SR15
SR14 SR13
JS1_OUT JS0_ FUNCT SLOT
PUDIS PUDIS
MODE MODE
DHWR
Miscellaneous Control Bits
LPMI
DLSR
ALSR
SRX1 SRX8
DRSR
ARSR
0404h
Vendor Vendor
REV4
REV3
REV2
REV1
REV0
4144h 5360h
REV7 REV6 REV5
NOTES registers shown bits containing assumed reserved. register addresses aliased next lower even address. Reserved registers should written. Zeros should written reserved bits. *Indicates Aliased register AD1819B backward compatibility.
REV.
-11-
AD1885
Reset (Index 00h)
Name Reset Default 0410h
Note: Writing value this register performs register reset, which causes registers revert their default values (except 74h, which forces serial configuration). Reading this register returns code part code type Stereo Enhancement. ID[9:0] Identify Capability. decodes capabilities AD1885 based following: Function Dedicated Channel Modem Line Codec Support Bass Treble Control Simulated Stereo (Mono Stereo) Headphone Support Loudness (Bass Boost) Support 18-Bit Resolution 20-Bit Resolution 18-Bit Resolution 20-Bit Resolution AD1885
SE[4:0] Stereo Enhancement. stereo enhancement identifies Analog Devices stereo enhancement.
Master Volume Registers (Index 02h)
Name Master Volume Default
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
RMV[5:0] LMV[5:0]
Right Master Volume Control. least significant represents This register controls output from maximum attenuation -94.5 Left Master Volume Control. least significant represents This register controls output from maximum attenuation -94.5 Master Volume Mute. When this "1," channel muted. xMV5 xMV0 0000 1111 1111 xxxx Function Attenuation -46.5 Attenuation -94.5 Attenuation Attenuation
-12-
REV.
AD1885
Headphones Volume Registers (Index 04h)
Name Default
Headphones Volume
LHV5 LHV4 LHV3 LHV2 LHV1 LHV0
RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 8000h
RHV[5:0] LHV[5:0]
Right Headphone Volume Control. least significant represents This register controls output from maximum attenuation -88.5 Left Headphone Volume Control. least significant represents This register controls output from maximum attenuation -88.5 Headphone Volume Mute. When this "1," channel muted. xHV5 xHV0 0000 1111 1111 xxxx Function Gain -40.5 Attenuation -88.5 Attenuation Attenuation
Master Volume Mono (Index 06h)
Name Default
Master Volume Mono
MMV4 MMV3 MMV2 MMV1 MMV0 8000h
MMV[4:0]
Mono Master Volume Control. least significant represents This register controls output from maximum attenuation 46.5 Mono Master Volume Mute. When this "1," channel muted.
Beep Register (Index 0Ah)
Name PC_BEEP Volume Default 8000h
PCV3 PCV2 PCV1 PCV0
PCV[3:0]
Beep Volume Control. least significant represents attenuation. This register controls output from maximum attenuation Beep routed Left Right Line outputs even when AD1885 RESET state. This that Power-On Self-Test (POST) codes heard user case hardware problem with Beep Mute. When this "1," channel muted. PCV3 PCV0 0000 1111 xxxx Function Attenuation Attenuation Attenuation
REV.
-13-
AD1885
Phone Volume (Index 0Ch)
Name Phone Volume Default
PHV4 PHV3 PHV2 PHV1 PHV0 8008h
PHV[4:0]
Phone Volume. Allows setting Phone Volume Attenuator steps. represents range -34.5 default value mute enabled. Phone Mute. When this "1," channel muted.
Volume (Index 0Eh)
Name Volume MCV4 MCV3 MCV2 MCV1 MCV0 Default 8008h
MCV[4:0]
Volume Gain. Allows setting Volume attenuator steps. represents range -34.5 default value mute enabled. Microphone Gain Block Disabled; Gain Enabled; Gain Mute. When this "1," channel muted.
Line Volume (Index 10h)
Name RLV4 RLV3 RLV2 RLV1 RLV0 Default 8808h
Line Volume
LLV4 LLV3 LLV2 LLV1 LLV0
RLV[4:0] LLV[4:0]
Right Line Volume. Allows setting Line right channel attenuator steps. represents range -34.5 default value mute enabled. Line Volume Left. Allows setting Line left channel attenuator steps. represents range -34.5 default value mute enabled. Line Mute. When this "1," channel muted.
Volume (Index 12h)
Name Default
Volume
LCV4 LCV3 LCV2 LCV1 LCV0
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0] LCV[4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Volume Mute. When this "1," channel muted.
-14-
REV.
AD1885
Video Volume (Index 14h)
Name Default
Video Volume
LVV4 LVV3 LVV2 LVV1 LVV0
RVV4 RVV3 RVV2 RVV1 RVV0 8808h
RVV[4:0] LVV[4:0]
Right Video Volume. Allows setting Video right channel attenuator steps. represents range -34.5 default value mute enabled. Left Video Volume. Allows setting Video left channel attenuator steps. represents range -34.5 default value mute enabled. Video Mute. When this "1," channel muted.
Volume (Index 16h)
Name Volume Default
LAV4 LAV3 LAV2 LAV1 LAV0
RAV4 RAV3 RAV2 RAV1 RAV0 8808h
RAV[4:0] LAV[4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Mute. When this "1," channel muted.
Volume (Index 18h)
Name Volume Default
LOV4 LOV3 LOV2 LOV1 LOV0
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
ROV[4:0] LOV[4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Volume Mute. When this "1," channel muted.
Volume Table
00000 01000 11111 xxxxx
Function Gain Gain -34.5 Gain Gain
REV.
-15-
AD1885
Record Select Control Register (Index 1Ah)
Name Default 0000h
Record Select
RS[2:0] LS[2:0]
Right Record Select Left Record Select.
Used select record source independently right left. table legend. default value 0000h, which corresponds
Record Gain (Index 1Ch)
Name Record Gain LIM3 LIM2 LIM1 LIM0 RIM3 RIM2 RIM1 RIM0 Default 8000h
Right Record Source CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mono PHONE_IN Left Record Source CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mono PHONE_IN
RIM[3:0] LIM[3:0]
Right Input Mixer Gain Control. Each represents 0000 range +22.5 Left Input Mixer Gain Control. Each represents 0000 range +22.5 Input Mute. Unmuted, Muted gain. xIM3 xIM0 1111 0000 xxxxx Function +22.5 Gain Gain Gain
-16-
REV.
AD1885
General-Purpose Register (Index 20h)
Name General-Purpose LPBK Default 0000h
Note: This register should read before writing generate mask only bit(s) that need changed. LPBK Loopback Control. ADC/DAC Digital Loopback Mode Select MIC1 MIC2. Mono Output Select MIC. PHAT Stereo Enhancement PHAT Stereo off. PHAT Stereo Output Path Mute. controls optional bypass path (the pre- post-3D paths mutually exclusive). pre-3D post-3D.
Control Register (Index 22h)
Name Control Default 0000h
DP[2:0]
Depth Control. Sets "Depth" PHAT Stereo enhancement according table below. 0000 0001 Depth 6.67% 93.33% 100%
REV.
-17-
AD1885
Subsection Ready Register (Index 26h)
Name Default
Power-Down Cntrl/Stat EAPD
000xh
Note: ready bits read only, writing REF, ANL, DAC, will have effect. These bits indicate status AD1885 subsections. one, then that subsection "ready." Ready defined subsection able perform nominal state. PR[5:0] section ready transmit data. section ready accept data. Analog gainuators, attenuators, mixers ready. Voltage References, VREF VREFOUT nominal level. AD1885 Power-Down Modes. first three bits used individually rather than combination with each other. last used combination with itself. mixer reference cannot powered down unless ADCs DACs also powered down. Nothing else powered until reference Power-Down Power-Down Power-Down Analog Mixer Power-Down VREF VREFOUT Power-Down AC-Link Power-Down Internal Clock Power-Down Headphone EAPD External Power-Down Control Signal effect unless ADCs, DACs, AC-Link powered down. reference mixer either down, power-up sequences must allowed completion before both set. multiple-codec systems, master codec's bits control slave codec. also effective slave codec master's clear, effect except enable disable PR5. Power-Down State Power-Down Power-Down Power-Down Mixer Power-Down Mixer Power-Down Mixer Power-Down Mixer Power-Down Standby
Extended Audio Register (Index 28h)
Name Extended Audio Default 0001h
EAPD
Note: Extended Audio read only register. ID[1:0] Variable Rate Audio. indicates support Variable Rate Audio. ID1, 2-bit field that indicates codec configuration: Primary Secondary
-18-
REV.
AD1885
Extended Audio Status Control Register (Index 2Ah)
Name Extended Audio St/Ctrl Default 0000h
Note: Extended Audio Status Control Register read/write register that provides status control extended audio features. Variable Rate Audio. enables support Variable Rate Audio mode (sample rate control registers SLOTREQ signaling).
Rate Register (Index 2Ch)
Name SR15 SR14 SR13 SR12 SR11 SR10 Default
2Ch/(7Ah) Rate
BB80h
Note: alias 7Ah. register must alias work; zero written VRA, both sample rates reset kHz. SR[15:0] Writing this register allows programming sampling frequency from 7040 (1B80h) (BB80h) increments. Programming value outside range 7040 (1b80h) 48000 (BB80h) causes codec saturate. rates, value written register supported, that value will echoed back when read, otherwise closest rate supported returned.
Rate Register (Index 32h)
32h/(78h) Name Rate SR15 SR14 SR13 SR12 SR11 SR10 Default
BB80h
Note: alias 78h. register must alias work; zero written VRA, both sample rates reset kHz. SR[15:0] Writing this register allows programming sampling frequency from 7040 (1B80h) (BB80h) increments. Programming value outside range 7040 (1b80h) 48000 (BB80h) causes codec saturate. rates, value written register supported, that value will echoed back when read; otherwise, closest rate supported returned.
Jack Sense/Audio Interrupt/Status Register (Index 72h)
Name
JS0_
Default
Jack Sense/Audio JS1_OUT/ Interrupt/Status FUNCT
JS1_ JS0_ PUDIS PUDIS
MODE MODE
0000h
Note: register bits read/write except AUDINT, JSINT, JS1, which read only. JSINT AUDINT JS0MODE JS1MODE JS0CLR JS1CLR JS0DIS JS1DIS REV. Indicates that jack sense interrupt been generated JS1. Remains until enabled interrupts cleared. Indicates state. Indicates state. Indicates Codec generated audio interrupt. Remains until software clears pending interrupts. Sets input mode, Interrupt Jack Sense. Sets input mode, Interrupt Jack Sense. This Codec when there pending interrupt. Software must clear this clear interrupt status bit. This Codec when there pending interrupt. Software must clear this clear interrupt status bit. JS0DIS set, Codec ignores Jack Sense JS0. JS1DIS set, Codec ignores Jack Sense JS1. -19-
AD1885
JS0_OE JS1_OE JS0PUDIS JS1PUDIS JS0_OUT Enables general-purpose output. Enables general-purpose output. Setting JS0PUDIS disables internal pull-up. Setting JS1PUDIS disables internal pull-up. When enabled GPO, reflects state JS0_OUT bit.
JS1_OUT/FUNCT When enabled GPO, reflects state JS1_OUT bit, otherwise this change functionality that only LINE_OUT muted when high.
Serial Configuration (Index 74h)
Name Serial Configuration SLOT Default
REGM2
REGM1
REGM0
DHWR
Note: this register reset when reset register (register 00h) written. DHWR REGM0 REGM1 REGM2 SLOT16 Disable Hardware Reset. Master Codec register mask. Slave Codec register mask. Slave Codec register mask. Enable 16-bit slots.
your system uses only single AD1885, ignore register mask. SLOT16 makes AC-Link slots bits length, formatted into slots.
Miscellaneous Control Bits (Index 76h)
Name Misc Control Bits LPMI ALSR DRSR ARSR Default 0000h
DLSR
SRX10 SRX8
ARSR
right sample generator select Selected (32h) Selected (2Ch). right sample generator select Selected (32h) Selected (2Ch). Multiply rate 8/7. Multiply rate 10/7. SRX10D7 SRX8D7 mutually exclusive. Modem filter enable (left channel only). Change only when DACs ADCs powered down. left sample generator select Selected (32h) Selected (2Ch). left sample generator select Selected (32h) Selected (2Ch). Digital Mono Select. Mixer Left Right DAC. Digital Audio Mode. Outputs bypass analog mixer sent directly codec output. Power Mixer. Zero fill (vs. repeat) starved data.
DRSR
SRX8D7 SRX10D7 MODEN ALSR
DLSR
LPMIX DACZ
-20-
REV.
AD1885
Sample Rate (Index 78h)
Name Default
(32h)/78h Sample Rate SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80h
Note: alias 78h. register must alias work; zero written VRA, both sample rates reset kHz. SR0[15:0] Writing this register allows user program sampling frequency from (1B58h) (BB80h) Hertz increments. Programming value greater than less than cause unpredictable results.
Sample Rate (Index 7Ah)
Name Default
(2Ch)/7Ah Sample Rate SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: alias 7Ah. register must alias work; zero written VRA, both sample rates reset kHz. SR1[15:0] Writing this register allows user program sampling frequency from (1B58h) (BB80h) Hertz increments. Programming value greater than less than cause unpredictable results.
Vendor Registers (Index 7Ch-Eh)
Name Vendor Default 4144h
S[7:0] F[7:0]
Name
This register ASCII encoded "S." This register ASCII encoded "D."
Default
Vendor
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5360h
T[7:0] REV[7:0]
This register ASCII encoded "S." Revision Register field contains revision number.
These bits read-only should verified before accessing vendor defined features.
REV.
-21-
AD1885
APPLICATIONS CIRCUITS
AD1885 been designed require minimum amount external circuitry. recommended applications circuits shown Figures 9-18. Reference designs AD1885 available obtained contacting your local Analog Devices sales representative authorized distributor. Example shell programs establishing communications path between AD1885 ADSP-21xx ADSP-21xxx also available.
AVDD NOTE: USED, GROUND JACK SENSE PINS.
22pF
JSO/EAPD AVSS3 AVDD3 HP_OUT_R AVSS2 HO_OUT_L AVDD2 MONO_OUT
DVDD
22pF
24.576MHz
47pF PC_BEEP
PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R
SDATA_OUT SDATA_IN SYNC RESET BIT_CLK
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP
AD1885
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1 AVDD1
47nF
270pF 270pF
AVDD
600Z
NOTE: "UNUSED" ANALOG INPUTS (LINE_IN_L/R, AUX_L/R, VIDEO_L/R, MIC1, MIC2, PC_BEEP, PHONE_IN CD_L/R/GND) MUST LEFT UNCONNECTED.
Figure Recommended One-Codec PWR/Decoupling AC`97 Connections
-22-
REV.
AD1885
JACK SENSE OPERATION
AD1885 features Jack Sense pins (JS0 JS1) that used automatically mute LINE_OUT and/or MONO_OUT audio outputs. When Jack Sense pins connected output jacks, AD1885 sense whether audio plug been inserted into particular output jack automatically mute other unnecessary audio outputs. should normally connected HP_OUT jack automatically mute MONO_OUT LINE_OUT audio signals, while should normally connected LINE_OUT jack automatically mute MONO_OUT signal. also possible Jack Sense Index Register (72h), which causes only mute LINE_OUT signal. This option desirable certain audio configurations. Table summarizes Jack Sense operation.
Table Jack Sense Operation Table
HP_OUT Plug (JS1)
LINE_OUT Plug (JS0)
Audio Output States (REG 72h, HP_OUT LINE_OUT MONO_OUT HP_OUT LINE_OUT MONO_OUT MUTE HP_OUT LINE_OUT MUTE MONO_OUT MUTE HP_OUT LINE_OUT MUTE MONO_OUT MUTE
Audio Output States (REG 72h, HP_OUT LINE_OUT MONO_OUT HP_OUT LINE_OUT MONO_OUT MUTE HP_OUT LINE_OUT MUTE MONO_OUT HP_OUT LINE_OUT MUTE MONO_OUT MUTE
NOTE: PLUG JACK SENSE HIGH, PLUG JACK SENSE LOW.
Jack Sense inputs active high their functionality enabled default CODEC power-up. necessary, Jack Sense inputs individually disabled writing bits CODEC Jack Sense Index Register (72h). Jack Sense pins contain active internal pull-ups. Jack Sense inputs being used, they should pulled down digital ground using resistors. This prevents LINE_OUT MONO_OUT from becoming muted while Jack Senses enabled.
CONNECTING JACK SENSES OUTPUT JACKS Headphone Jack
diagram Figure shows preferred method connect Jack Sense line HP_OUT jack. This scheme requires stereo jack with normally closed isolated single switch. switch holds Jack Sense line (grounded) until audio plug inserted, causing switch open Jack Sense line high CODEC internal pull-up. resistors keep electrolytic output caps properly polarized while HP_OUT jack used.
NOTE: LOCATE CLOSE CODEC. JACK SENSE LINE
CODEC (PIN
OPTIONAL COMPONENTS FROM CODEC HP_OUT_R (PIN 600Z FROM CODEC HP_OUT_L (PIN
ISOLATED SWITCH
470pF
600Z 470pF
HEADPHONE
Figure Jack Sense Connection HP_OUT Jack, Using Isolated Switch
Alternatively, when audio output jack containing isolated switch available, circuit shown Figure used. While audio plug out, this circuit keeps Jack Sense line state low, pull-down affect (with audio present) tracking lower peaks HP_OUT audio signal. Once audio plug inserted jack switch opens, Jack Sense line switches high state CODEC internal pull-up, which quickly charges DVDD. resistors also keep electrolytic output caps properly polarized while HP_OUT jack used. REV. -23-
AD1885
NOTE: LOCATE CLOSE CODEC. JACK SENSE CODEC (PIN MMBD914 OPTIONAL COMPONENTS 600Z FROM CODEC HP_OUT_R (PIN 470pF 600Z FROM CODEC HP_OUT_L (PIN 470pF
HEADPHONE
Figure Jack Sense Connection HP_OUT Jack, Using Nonisolated Switch
LINE_ Jack
Although shown, LINE_OUT jack used jack sense functionality desired, LINE_OUT jack should wired similar configuration shown above HP_OUT jack (preferably Figure 10). LINE_OUT jack should normally connected input, order mute MONO_OUT signal. recommend that this case output coupling caps (C2, other values should kept same.
APPLICATION CIRCUITS
CD-ROM CONNECTIONS
Typical CD-ROM drives generate output require voltage divider compatibility with Codec input range). recommended circuit basically group divide-by-two voltage dividers shown Figure CD_GND_REF used cancel differential ground noise from CD-ROM. optimum noise cancellation, this section divider should have approximately half impedance right left channel section dividers.
VOLTAGE DIVIDER AC-COUPLING
CODEC CD_L INPUT
HEADER AUDIO (LGGR)
CODEC CD_GND_REF INPUT
CODEC CD_R INPUT
Figure Typical CD-ROM Audio Connections
LINE_IN, VIDEO INPUT CONNECTIONS
Most these audio sources also generate audio level require input voltage divider compatible with Codec inputs. Figure shows recommended application circuit. applications requiring compliance, components should configured selected provide adequate immunity emissions control.
COMPONENTS LINE/AUX/VIDEO INPUT 600Z CODEC RIGHT CHANNEL INPUT 470pF 600Z CODEC LEFT CHANNEL INPUT 470pF VOLTAGE DIVIDER AC-COUPLING
Figure LINE_IN, AUX, Video Input Connections
-24-
REV.
AD1885
MICROPHONE CONNECTIONS
AD1885 contains internal microphone preamp with gain; most cases direct microphone connection shown Figure adequate. microphone level low, external preamp added shown Figure either case microphone bias derived from Codec's internal reference (VREFOUT) using resistor. preamp circuit, VREFOUT signal also provide midpoint bias amplifier. meet PC99 1.0A requirements, signal should placed microphone jack bias ring. This configuration supports electret microphones with three conductor plugs, well dynamic microphones with conductor plugs (ring sleeve shorted together). Additional filtering required limit microphone response audio band interest.
COMPONENTS INPUT 600Z 470pF 600Z 470pF BIAS CODEC MIC1 MIC2 INPUT AC-COUPLING
FROM CODEC VREFOUT
Figure Recommended Microphone Input Connections
PREAMP COMPONENTS INPUT 600Z 470pF 600Z 470pF BIAS AD8531 AC-COUPLING
AVDD CODEC MIC1 MIC2 INPUT
FROM CODEC VREFOUT
Figure Microphone with Additional External Preamp Gain)
LINE OUTPUT CONNECTIONS
AD1885 Codec provides stereo LINE_OUT signals standard level. These signals must ac-coupled before they connected external load. After ac-coupling, minimal resistive load recommend keep capacitors properly biased reduce click when plugging stereo equipment into output jack. capacitor values should selected provide desired frequency response, taking into account nominal impedance external load. meet PC99 specification PCs, testing must performed with load, therefore value recommended achieve less than roll-off
COMPONENTS STEREO LINE_OUT JACK 600Z 470pF 600Z 470pF FROM CODEC LINE_OUT_L NOTE: OUTPUT USED, AC-COUPLING VALUES WILL DEPENDEND DESIGN. FROM CODEC LINE_OUT_R AC-COUPLING
Figure Recommended LINE_OUT Connections
REV.
-25-
AD1885
PC_BEEP INPUT CONNECTIONS
recommended PC_BEEP input circuit shown below. Under most cases PC_BEEP signal should attenuated, filtered then ac-coupled into Codec.
PC_BEEP (FROM ICH)
CODEC PC_BEEP INPUT
Figure Recommended PC_BEEP Connections
GROUNDING LAYOUT
reduce noise emissions, Analog Devices recommends split ground plane shown Figure purpose splitting ground plane create noise analog area that somewhat isolated from digital ground current noise generated system's logic. analog circuitry should placed analog ground plane area. reference purposes, return power supply currents, analog digital ground planes must connected some point, ideally small bridge under near Codec should provided. resistor ferrite bead should also considered since these allow some flexibility optimizing layout meet requirements.
DIGITAL GROUND PLANE
CONNECT SPLIT GROUND PLANES NEAR CODEC.
ISOLATION TRENCH
AD1885
ANALOG GROUND PLANE
Figure Recommended Split Ground Plane
ANALOG POWER SUPPLY
minimize audio noise, Codec analog power supply (AVDD) should well decoupled regulated. systems recommended that analog supply derived from power supply using localized linear voltage regulator. Preferably, analog power supply should connected Codec's analog section using ferrite bead. power plane layer being used system design, recommended that analog power plane Codec also split (mirroring analog ground plane). this case, analog power supply ferrite bead should bridge isolation trench, close Codec location.
-26-
REV.
AD1885
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48)
0.063 (1.60) 0.030 (0.75) 0.018 (0.45) SEATING PLANE VIEW
(PINS DOWN)
0.354 (9.00) 0.276 (7.0)
0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
0.006 (0.15) 0.002 (0.05)
0.007 (0.18) 0.004 (0.09)
0.019685 (0.5)
0.011 (0.27) 0.006 (0.17)
0.354 (9.00)
0.276 (7.0)
REV.
-27-
PRINTED U.S.A.
C00753-2.5-7/00 (rev.

AC'97 SoundMAX® Codec AD1885 ENHANCED FEATURES Full Duplex Variab

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