AC'97 SoundPort® Codec AD1819B ENHANCED FEATURES Support Multiple

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AC'97 SoundPort® Codec AD1819B ENHANCED FEATURES Support Multiple

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AC'97 FEATURES Fully Compliant AC'97 Analog Component 48-Terminal LQFP Package Multibit Converter Architecture Improved Ratio 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs Connection from LINE, VIDEO, Analog Line-Level Mono Inputs Speakerphone BEEP Mono Input Switchable from External Sources High Quality Input with Ground Sense Stereo Line Level Output Mono Output Speakerphone Power Management Support
AC'97 SoundPort® Codec AD1819B
ENHANCED FEATURES Support Multiple Codec Communications 16-Bit Serial Port Format Variable Sampling Rate with Resolution Supports Modem Sample Rates Filtering PhatStereo Stereo Enhancement VHDL Verilog Models Serial Port Available
FUNCTIONAL BLOCK DIAGRAM
CHAIN_IN CHAIN_CLK
AD1819B
MIC1 MIC2 LINE_IN VIDEO PHONE_IN SYNC
LINK
0dB/ 20dB
MASTER/SLAVE SYNCHRONIZER
SELECTOR
16-BIT CONVERTER
16-BIT CONVERTER
RESET
SAMPLE RATE GENERATORS
BIT_CLK
SDATA_OUT LINE_OUT_L MONO_OUT LINE_OUT_R
PHAT STEREO
16-BIT CONVERTER
SDATA_IN
PHAT STEREO GAIN ATTENUATE MUTE MASTER VOLUME
16-BIT CONVERTER
OSCILLATORS
PC_BEEP
XTALO
XTALI
SoundPort registered trademark Analog Devices, Inc. Phat trademark Analog Devices, Inc.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
AD1819B
PRODUCT OVERVIEW
AD1819B SoundPort Codec designed meet requirements Audio Codec '97, Component Specification, Revision 1.03, 1996, Intel Corporation, found www.Intel.com. addition, AD1819B supports multiple codec configurations three AC-Link), serial mode, variable sample rates, modem sample rates filtering, built-in Phat Stereo enhancement. AD1819B analog front high performance audio, modem, applications. AC'97 architecture defines 2-chip audio solution comprising digital audio controller, plus high quality analog component that includes Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs) mixer I/O. main architectural features AD1819B high quality analog mixer section, channels conversion, channels conversion Data Direct Scrambling (D2S) rate generators. AD1819B's left channel compatible modem applications supporting irrational sample rates modem filtering requirements.
FUNCTIONAL DESCRIPTION
Each channel independent, process left right channel data different sample rates. programmed sample rates from have resolution AD1819B also supports irrational V.34 sample rates.
Sample Rates
AD1819B default mode sets codec operate sample rates. converter pairs process left right channel data different sample rates. AD1819B sample rate generator allows codec instantaneously change process sample rates from with resolution in-band integrated noise distortion artifacts introduced rate conversions below AD1819B uses 4-bit structure Data Directed Scrambling (D2S) enhance noise immunity motherboards enclosures, suppress idle tones below device's quantization noise floor. process pushes noise distortion artifacts caused errors multibit conversion process frequencies beyond audible range human then filters them.
Digital-to-Analog Signal Path
This section overviews functionality AD1819B intended general introduction capabilities device. Detailed reference information found descriptions Indexed Control Registers. codec contains stereo pair ADCs. Inputs selected from following analog signals: telephony (PHONE_IN), mono microphone (MIC1 MIC2), stereo line (LINE_IN), auxiliary line input (AUX), stereo (CD), stereo audio from video source (VIDEO) post-mixed stereo mono line output (LINE_OUT).
Analog Mixing Analog Inputs
analog output gained attenuated from -34.5 steps, summed with analog input signals. summed analog signal enters Master Volume stage where each channel mixer output attenuated from -46.5 steps muted.
Host-Based Echo Cancellation Support
AD1819B supports time correlated data format presenting data left channel mono summation left right output right channel. splittable; left right data sampled different rates.
Telephony Modem Support
PHONE_IN, MIC1 MIC2, LINE_IN, AUX, VIDEO mixed analog domain with stereo output from DACs. Each channel stereo analog inputs independently gained attenuated from -34.5 steps. summing path mono inputs (PHONE_IN, MIC1, MIC2 LINE_OUT) duplicates mono channel data both left right LINE_OUT. Additionally, attention signal (PC_BEEP) mixed with line output. switch allows output DACs bypass Phat Stereo enhancement.
Analog-to-Digital Signal Path
AD1819B contains V.34-capable analog front supporting host-based data pump modems. modem typical dynamic range over analog output passband where 12.8 kHz. left channel used convert modem data same sample rate range between kHz. programmed sample rates have resolution AD1819B supports irrational V.34 sample rates with 10/7 selectable sample rate multiplier coefficients.
Differences Between AD1819A AD1819B
selector sends left right channel signals programmable gain amplifier (PGA). following selector allows independent gain each channel entering from +22.5 steps.
voltage reference (VREF) AD1819B remains active while RESET asserted. This eliminates audible artifacts associated with RESET transitions that occur during Windows boot (power-up) Windows warm restart (reset).
REV.
SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
AD1819B
1008 Test Conditions Calibrated Attenuation Input Output Load Mute Test Conditions Calibrated Gain Input Relative Full Scale Line Input Selected 2.83 0.283 2.83 Units
Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Input Signal Analog Output Passband (AC-Link) (AC-Link) (CS0, CS1, CHAIN_IN) (CHAIN_CLK)
ANALOG INPUT
Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, VIDEO, PHONE_IN, PC_BEEP MIC1, MIC2 with Gain (M20 MIC1, MIC2 with Gain (M20 Input Impedance* Input Capacitance*
PROGRAMMABLE GAIN AMPLIFIER-ADC
Parameter Step Size 22.5 Gain Range Span
ANALOG MIXER- INPUT GAIN/AMPLIFIERS/ATTENUATORS
22.5
Units
Parameter
Units
Dynamic Range (-60 Input THD+N, Referenced Full Scale, A-Weighted) LINE_OUT Other LINE_OUT* Step Size (+12 -34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, VIDEO, PHONE_IN, Input Gain/Attenuation Range MIC, LINE_IN, AUX, VIDEO, PHONE_IN, Step Size dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP
DIGITAL DECIMATION INTERPOLATION FILTERS*
46.5
Parameter Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband
*Guaranteed, tested. Specifications subject change without notice.
0.09
Units
12/FS
REV.
AD1819B-SPECIFICATIONS
ANALOG-TO-DIGITAL CONVERTERS
Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 Input THD+N Referenced Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Crosstalk* Line Inputs (Input Ground Read Input Ground Read Line Other Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Offset Error
DIGITAL-TO-ANALOG CONVERTERS
0.02
Units Bits
-100
Parameter Resolution Total Harmonic Distortion (THD) LINE_OUT Dynamic Range (-60 Input THD+N Referenced Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Crosstalk* (Input Zero Measure LINE_OUT_R; Input Zero Measure LINE_OUT_L) Total Out-of-Band Energy (Measured from kHz)*
MASTER VOLUME
0.02
Units Bits
Parameter Step Size -46.5 LINE_OUT_L, LINE_OUT_R, MONO_OUT Output Attenuation Range Span Mute Attenuation Fundamental*
ANALOG OUTPUT
46.5
Units
Parameter Full-Scale Output Voltage Output Impedance* External Load Impedance Output Capacitance* External Load Capacitance VREF VREF Current Drive VREFOUT VREFOUT Current Drive Mute Click (Muted Output Minus Unmuted Midscale Output)*
*Guaranteed, tested. Specifications subject change without notice.
2.83
Units
2.00 2.25 2.25 2.50
REV.
AD1819B
STATIC DIGITAL SPECIFICATIONS
Parameter High-Level Input Voltage (VIH): Digital Inputs Low-Level Input Voltage (VIL) High-Level Output Voltage (VOH), Low-Level Output Voltage (VOL), Input Leakage Current Output Leakage Current
POWER SUPPLY
DVDD DVDD
DVDD DVDD
Units
Parameter Power Supply Range-Analog Power Supply Range-Digital Power Supply Current Power Dissipation Analog Supply Current Digital Supply Current Power Supply Rejection (100 Signal kHz)* Both Analog Digital Supply Pins, Both ADCs DACs)
CLOCK SPECIFICATIONS*
Units
Parameter Input Clock Frequency Recommended Clock Duty Cycle
POWER-DOWN STATES
24.576
Units
Parameter ADCs Input Power-Down DACs Power-Down Analog Mixer Power-Down (VREF VREFOUT Analog Mixer Power-Down (VREF VREFOUT Off) Digital Interface Power-Down* Internal Clocks Disabled* Power-Down VREF Standby Mode* Total Power-Down RESET (Low)
*Guaranteed, tested. Specifications subject change without notice.
Bits PR1, PR0, PR1, PR0, PR1, PR4, PR0, PR0, PR1, PR2, PR4, PR0, PR1, PR2, PR3, PR4,
Units
REV.
AD1819B
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter RESET Active Pulsewidth RESET Inactive BIT_CLK Start-Up Delay SYNC Active High Pulsewidth SYNC Pulsewidth SYNC Inactive BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter* BIT_CLK High Pulsewidth BIT_CLK Pulsewidth SYNC Frequency SYNC Period Setup Falling Edge BIT_CLK Hold from Falling Edge BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time Slot BIT_CLK, SDATA_IN Setup Trailing Edge RESET (Applies SYNC, SDATA_OUT) Rising Edge RESET HI-Z Delay
*Output Jitter directly dependent crystal input jitter.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISE tFALL tRISE SYNC tFALL SYNC tRISE tFALL tRISE DOUT tFALL DOUT tS2_PDOWN tSETUP2RST tOFF
162.8 0.0814 162.8
Units
19.5 12.288 81.4
32.56 32.56
40.7 40.7 48.0 20.8
48.84 48.84
15.0 15.0
tRST_LOW
RESET
tRST2CLK
BIT_CLK
Figure Cold Reset
tSYNC_HIGH
SYNC BIT_CLK
tRST2CLK
Figure Warm Reset
tCLK_LOW
BIT_CLK
tCLK_HIGH tCLK_PERIOD
tSYNC_LOW
SYNC
tSYNC_HIGH tSYNC_PERIOD
Figure Clock Timing
REV.
AD1819B
tSETUP
SYNC BIT_CLK SYNC SDATA_OUT BIT_CLK SLOT SLOT
SDATA_OUT
WRITE 0x26
DATA
DON'T CARE
tHOLD
tS2_PDOWN
SDATA_IN NOTE: BIT_CLK SCALE
Figure Data Setup Hold
BIT_CLK
Figure AC-Link, Link Power Mode Timing
tRISECLK tFALLCLK
RESET
SYNC
tRISESYNC
SDATA_IN
tFALLSYNC
SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK HI-Z
tRISEDIN
SDATA_OUT
tFALLDIN
tOFF
Figure Test Mode
tFALLDOUT
tRISEDOUT
Figure Signal Rise Fall Time
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Parameter Power Supplies Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
-0.3 -0.3 -0.3 -0.3
10.0 AVDD DVDD +150
Units Model
Temperature Range
Package Description
Package Option*
AD1819BJST -40°C +85°C 48-Terminal LQFP ST-48
Thin Quad Flatpack.
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Ambient Temperature Rating TAMB TCASE TCASE Case Temperature Power Dissipation Thermal Resistance (Case-to-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Package LQFP
76.2°C/W
17°C/W
59.2°C/W
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD1819B features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD1819B
CONFIGURATION 48-Terminal LQFP (ST-48)
CHAIN_CLK MONO_OUT
CHAIN_IN
AVSS2
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP
IDENTIFIER
AVDD2
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1
AD1819B
VIEW (Not Scale)
VREFOUT VREF
AVSS1 AVDD1
PHONE_IN AUX_L AUX_R
MIC1
VIDEO_R CD_L
VIDEO_L
CD_GND
CD_R
MIC2
LINE_IN_L
CONNECT
FUNCTION DESCRIPTIONS Digital
Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET
LQFP
O/I*
Description 24.576 Crystal Clock Input 24.576 Crystal Output Serial Data Output. Serial, Time Division Multiplexed, AD1819B Input Stream Clock Input, 12.288 Serial Data Clock. Daisy Chain Output Clock Serial Data Input. Serial, Time Division Multiplexed, AD1819B Output Stream Fixed Rate Sample Sync Clock Reset. AC-Link Master Hardware Reset
*Input AD1819B configured Slave Slave
Daisy Chain Connections
Name CHAIN_IN CHAIN_CLK
LQFP
I/O*
Description Daisy Chain Codec Select Daisy Chain Codec Select Daisy Chain Data Input 24.576 Buffered Clock Input/Output
*Output when configured Master. Input when configured Slave Slave
LINE_IN_R
REV.
AD1819B
Analog
These signals connect AD1819B component analog sources sinks, including microphones speakers. Name PC_BEEP PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT
Filter/Reference
LQFP
Description Beep. Speaker Beep Pass-Through Phone. From Telephony Subsystem Speakerphone Handset Auxiliary Input Left Channel Auxiliary Input Right Channel Video Audio Left Channel Video Audio Right Channel Audio Left Channel Audio Analog Ground Sense Differential Input Audio Right Channel Microphone Desktop Microphone Input Microphone Second Microphone Input Line Left Channel Line Right Channel Line Left Channel Line Right Channel Monaural Output Telephony Subsystem Speakerphone
Name VREF VREFOUT AFILT1 AFILT2 FILT_R FILT_L RX3D CX3D
LQFP
Description Voltage Reference Filter Voltage Reference Output Drive (Intended Bias) Antialiasing Filter Capacitor-ADC Right Channel Antialiasing Filter Capacitor-ADC Left Channel AC-Coupling Filter Capacitor-ADC Right Channel AC-Coupling Filter Capacitor-ADC Left Channel Phat Stereo Enhancement-Capacitor Phat Stereo Enhancement-Capacitor
Power Ground Signals
Name DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2
Connects
LQFP
Description Digital VDD-5.0 Digital Digital Digital VDD-5.0 Analog VDD-5.0 Analog Analog VDD-5.0 Analog
Name
LQFP
Description Connect Connect Connect Connect Connect
REV.
AD1819B
MIC1
MIC2
0dB/20dB 0x0E 0x20
LS/RS 0x1C 0x1C LS/RS LS/RS RESET
LINE_IN
VIDEO PHONE_IN
0X1C
16-BIT
STEREO MONO STEREO
0X1C
16-BIT
0x1A
SYNC 0x0C 0x0C 0x0E 0x10 0x16 0x12 0x14 0x18 SDATA_IN 16-BIT 0x7A LPBK 0x20 0x0E 0x10 0x16 0x12 0x14 0x78
LINK
0X74
BIT_CLK
SDATA_OUT
0x02
0x02 0x06 0x02 0x22
LINE_OUT_L
0x06
0x20
0x22
MONO_OUT
0x02
0x20
0x18 16-BIT
LINE_OUT_R
0x0A 0x0A PC_BEEP GAIN ATTENUATE MUTE MASTER VOLUME
AD1819B
OSCILLATORS
XTL_OUT
XTL_IN
Figure Block Diagram Register
-10-
REV.
AD1819B
Indexed Control Registers
Name Reset Master Volume Reser Master Volume Mono Reser Beep Volume Phone Volume Volume Line Volume Volume Video Volume Volume Record Select Record Gain Reser General Purpose Control Reser Power-Down Contr/Stat Reser LMV5 LMV4 LLV4 LCV4 LVV4 LAV4 LOV4 LMV3 LLV3 LCV3 LVV3 LAV3 LOV3 LIM3 LMV2 LLV2 LCV2 LVV2 LAV2 LOV2 LIM2 LMV1 LLV1 LCV1 LVV1 LAV1 LOV1 LIM1 LMV0 LLV0 LCV0 LVV0 LAV0 LOV0 LIM0 LPBK RMV5 MMV5 RMV4 MMV4 PCV3 PHV4 MCV4 RLV4 RCV4 RVV4 RAV4 ROV4 RMV3 MMV2 PCV2 PHV3 MCV3 RLV3 RCV3 RVV3 RAV3 ROV3 RIM3 RMV2 MMV2 PCV1 PHV2 MCV2 RLV2 RCV2 RVV2 RAV2 ROV2 RIM2 RMV1 MMV1 PCV0 PHV1 MCV1 RLV1 RCV1 RVV1 RAV1 ROV1 RIM1 RMV0 MMV0 PHV0 MCV0 RLV0 RCV0 RVV0 RAV0 ROV0 RIM0 Default 0400h 8000h 8000h 8000h 8008h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 0000h
Reser Serial Configuration
SLOT
REGM
REGM
REGM
DRQE
DLRQ
DLRQ
DLRQ
DRRQ
DRRQ
DRRQ
7000h
Misc Control Bits Sample Rate Sample Rate Vendor Vendor
DACZ SR015 SR115
SR014 SR114
SR013 SR113
SR012 SR112
SR011 SR111
DLSR SR010 SR110
SR09 SR19
ALSR SR08 SR18
SR07 SR17 REV7
SRX1 SR06 SR16 REV6
SRX8 SR05 SR15 REV5
SR04 SR14 REV4
SR03 SR13 REV3
DRSR SR02 SR12 REV2
SR01 SR11 REV1
ARSR SR00 SR10 REV0
0000h BB80h BB80h 4144h 5303h
NOTES registers shown bits containing reserved. register addresses aliased next lower even address. Reserved registers should written. Zeros should written reserved bits.
REV.
-11-
AD1819B
Reset (Index 00h)
Name Reset Default 0400h
Note: Writing value this register performs register reset, which cause registers revert their default values (except 74h, which controls serial configuration). Reading this register returns code part code type Stereo Enhancement. [9:0] Identify Capability. field decodes capabilities AD1819B following: Function Dedicated Channel Modem Line Codec Support Bass Treble Control Simulated Stereo (Mono Stereo) Headphone Support Loudness (Bass Boost) Support 18-Bit Resolution 20-Bit Resolution 18-Bit Resolution 20-Bit Resolution AD1819B*
*The AD1819B contains none optional features identified these bits.
[4:0]
Stereo Enhancement. stereo enhancement field identifies Analog Devices Phat Stereo enhancement.
Master Volume (Index 02h)
Name Master Volume LMV5 LMV4 LMV3 LMV2 LMV1 LMV0 RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 Default 8000h
[4:0] RMV5 [4:0] LMV5
Right Master Volume Control. least significant represents This register controls output from maximum attenuation -46.5 Right Master Volume Maximum Attenuation. Forces [4:0] "1s," -46.5 Left Master Volume Control. least significant represents This register controls output from maximum attenuation -46.5 Left Master Volume Maximum Attenuation. Forces [4:0] "1s," -46.5 Master Volume Mute. When this "1," left right channels muted. xMV5 xMV0 0000 1111 xxxx xxxx Function Attenuation -46.5 Attenuation -46.5 Attenuation Attenuation
Master Volume Mono (Index 06h)
Name Master Volume Mono MMV5 MMV4 MMV3 MMV2 MMV1 MMV0 Default 8000h
[4:0] MMV5
Mono Master Volume Control. least significant represents This register controls output from maximum attenuation -46.5 Mono Master Volume Maximum Attenuation -46.5 Mono Master Volume Mute. When this "1," mono channel muted.
-12-
REV.
AD1819B
Beep (Index 0Ah)
Name Beep Volume PCV3 PCV2 PCV1 PCV0 Default 8000h
MMV5 MMV0 0000 1111 xxxx xxxx
Function Attenuation -46.5 Attenuation -46.5 Attenuation Attenuation
[3:0]
Beep Volume Control. least significant represents attenuation. This register controls output from maximum attenuation Beep routed Left Right Line outputs even when AD1819B RESET State. This that Power-On Self Test (POST) codes heard user case hardware problem with Beep Mute. When this "1," channel muted. PCV3 PCV0 0000 1111 xxxx Function Attenuation Attenuation Attenuation
Phone Volume (Index 0Ch)
Name Phone Volume PHV4 PHV3 PHV2 PHV1 PHV0 Default 8008h
[4:0]
Phone Volume. Allows setting Phone Volume Attenuator steps. represents range -34.5 default value mute enabled. Phone Mute. When this "1," channel muted.
Volume (Index 0Eh)
Name Volume MCV4 MCV3 MCV2 MCV1 MCV0 Default 8008h
[4:0]
Volume Gain. Allows setting Volume attenuator steps. represents range -34.5 default value mute enabled. Microphone Gain Block Disabled; Gain Enabled; Gain Mute. When this "1," channel muted.
Line Volume (Index 10h)
Name LINE_IN Volume LLV4 LLV3 LLV2 LLV1 LLV0 RLV4 RLV3 RLV2 RLV1 RLV0 Default 8808h
[4:0] [4:0]
Right Line Volume. Allows setting Line right channel attenuator steps. represents range -34.5 default value mute enabled. Left Line Volume. Allows setting Line left channel attenuator steps. represents range -34.5 default value mute enabled. Line Mute. When this "1," channel muted.
REV.
-13-
AD1819B
Volume (Index 12h)
Name Volume LCV4 LCV3 LCV2 LCV1 LCV0 RCV4 RCV3 RCV2 RCV1 RCV0 Default 8808h
[4:0] [4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Volume Mute. When this "1," channel muted.
Video Volume (Index 14h)
Name Video Volume LVV4 LVV3 LVV2 LVV1 LVV0 RVV4 RVV3 RVV2 RVV1 RVV0 Default 8808h
[4:0] [4:0]
Right Video Volume. Allows setting Video right channel attenuator steps. represents range -34.5 default value mute enabled. Left Video Volume. Allows setting Video left channel attenuator steps. represents range -34.5 default value mute enabled. Video Mute. When this "1," channel muted.
Volume (Index 16h)
Name Volume LAV4 LAV3 LAV2 LAV1 LAV0 RAV4 RAV3 RAV2 RAV1 RAV0 Default 8808h
[4:0] [4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Mute. When this "1," channel muted.
Volume (Index 18h)
Name Volume LOV4 LOV3 LOV2 LOV1 LOV0 ROV4 ROV3 ROV2 ROV1 ROV0 Default 8808h
[4:0] [4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Volume Mute. When this "1," channel muted. Volume Table (Index 18h) Mute 00000 01000 11111 xxxxx Function Gain Gain -34.5 Gain Gain
-14-
REV.
AD1819B
Record Select Control (Index 1Ah)
Name Record Select Default 0000h
[2:0] [2:0]
Right Record Select. Left Record Select. Used select record source independently right left. table legend. default value 0000h, which corresponds Right Record Source CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mono PHONE_IN Left Record Source CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mono PHONE_IN
Record Gain (Index 1Ch)
Name Record Gain LIM3 LIM2 LIM1 LIM0 RIM3 RIM2 RIM1 RIM0 Default 8000h
[3:0] [3:0]
Right Input Mixer Gain Control. Each represents 0000 range +22.5 Left Input Mixer Gain Control. Each represents 0000 range +22.5 Input Mute. Unmuted, Muted gain. xIM3 xIM0 1111 0000 xxxxx Function +22.5 Gain Gain Gain
General Purpose (Index 20h)
Name General Purpose
LPBK
Default 0000h
LPBK
Loopback Control. ADC/DAC digital loopback mode. Select. MIC1. MIC2. -15-
REV.
AD1819B
Mono Output Select. Mix. Mic. Phat Stereo Enhancement. Phat Stereo off. Phat Stereo Output Path. controls optional bypass path (the pre- post3D outpaths mutually exclusive). Pre-3D. Post-3D. register should read before writing generate mask only bit(s) that need changed. default value 0000h.
Control (Index 22h)
22h* Name Control Default 0000h
[2:0]
Depth Control. Sets "Depth" Phat Stereo enhancement according table below. Depth 6.67% 93.33% 100%
Power-Down Control/Status (Index 26h)
Name Power-Down Cntrl/Stat Default 0000h
[5:0]
Ready Bits: ready bits read only, writing REF, ANL, DAC, will have effect. These bits indicate status AD1819B subsections. then that subsection "ready." Ready defined subsection able perform nominal state. section ready transmit data. section ready accept data. Analog gainuators, attenuators, mixers ready. Voltage References, VREF REFOUT nominal level. Power-Down Bits. Bits used individually rather than combination with each other. last used combination with itself. Power-Down State ADCs Input Power-Down DACs Power-Down Analog Mixer Power-Down (VREF VREFOUT Analog Mixer Power-Down (VREF VREFOUT Off) AC-Link Interface Power-Down Internal Clocks Disabled Power-Down VREF Standby Mode Total Power-Down Bits PR1, PR0, PR1, PR0, PR1, PR4, PR0, PR0, PR1, PR2, PR4, PR0, PR1, PR2, PR3, PR4,
-16-
REV.
AD1819B
Serial Configuration (Index 74h)
Name Serial Configuration SLOT REGM REGM REGM DRQE DLRQ DLRQ DLRQ DRRQ DRRQ Default
DRRQ 7000h
DRRQ0 DRRQ1 DRRQ2 DLRQ0 DLRQ1 DLRQ2 DRQEN REGM0 REGM1 REGM2 SLOT16
Master AC'97 Codec Right Request. Slave Codec Right Request. Slave Codec Right Request. Master AC'97 Codec Left Request. Slave Codec Left Request. Slave Codec Left Request. Fills idle status slots with request reads, stuffs requests into output address slot. (AC-Link Slot Master Codec Register Mask. Slave Codec Register Mask. Slave Codec Register Mask. Enable 16-Bit Slots. your system uses only single AD1819B, ignore register mask slave 1/slave request bits. write this register, write ones register mask bits. request bits read-only. codec asserts each request when corresponding channel accept data next frame. These bits snapshots codec state taken when current frame began (effectively, rising edge SYNC), they also take notice samples sent current frame. DRQEN bit, AD1819B will fill otherwise unused AC-Link status address data slots with contents register 74h. That makes somewhat simpler access information, because don't need continually issue AC-Link read commands register contents. Also, requests reflected Slot Bits These bits active SLOT16 makes AC-Link slots bits length, formatted into slots.
Miscellaneous Control Bits (Index 76h)
Name Misc Control Bits DACZ DLSR ALSR SRX10 SRX8 DRSR ARSR Default 0000h
ARSR
Right Sample Generator Select. Connects right channel SR1. Selected. Selected. Right Sample Generator Select. Connects right channel SR1. Selected. Selected. Multiply Rate 8/7. Multiply Rate 10/7. SRX10D7 SRX8D7 mutually exclusive; SRX10D7 priority both set. Modem Filter Enable (left channel only). Change only when DACs powered down. Left Sample Generator Select. Connects left channel SR1. Selected. Selected. Left Sample Generator Select. Connects left channel SR1. Selected. Selected. Zero-Fill (vs. repeat sample) starved.
DRSR
SRX8D7 SRX10D7 MODEN ALSR
DLSR
DACZ
REV.
-17-
AD1819B
Sample Rate (Index 78h)
Name Sample Rate SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 Default BB80h
[15:0]
Writing this register allows user program sampling frequency from (1B58h) (BB80h) increments. Programming value greater than less than cause unpredictable results.
Sample Rate (Index 7Ah)
Name Sample Rate SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 Default BB80h
[15:0]
Writing this register allows user program sampling frequency from (1B58h) (BB80h) increments. sample rate multiplied 10/7 setting Bits Register 76h.
Vendor (Index 7Ch-7Eh)
Name Vendor Default 4144h
[7:0] [7:0]
Name Vendor
This register ASCII encoded "A." This register ASCII encoded "D."
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 Default 5303h
[7:0] [7:0]
This register ASCII encoded "S." Revision Register field contains revision number. These bits read-only should verified before accessing vendor-defined features.
DIGITAL INTERFACE AD1819B AC-Link Digital Serial Interface Protocol
AD1819B incorporates AC'97 5-pin digital serial interface that links digital controller. AC-Link bidirectional, fixed rate, serial digital stream. handles multiple input, output audio streams, well control register accesses employing time division multiplexed (TDM) scheme. AC-Link architecture divides each audio frame into outgoing incoming data streams, 20-bit sample resolution. AD1819B uses 16-bit samples. data streams include: Protocol Control Control Register Write Port Status Control Register Read Port Playback 2-Channel Composite Output Stream Record Data 2-Channel Composite Input Stream Input Output Output Slots Input Slots Output Slots Input Slots
Synchronization AC-Link data transactions signaled AC'97 controller. AD1819B drives serial clock onto AC-Link, which AC'97 controller then qualifies with synchronization signal construct audio frames. SYNC, which fixed kHz, derived dividing down serial clock (BIT_CLK) 256. BIT_CLK fixed 12.288 MHz. AC-Link serial data updated each rising edge BIT_CLK. receiver AC-Link data, AD1819B outgoing data AC'97 controller incoming data, samples each serial falling edge BIT_CLK. SYNC must remain high minimum BIT_CLK maximum duration BIT_CLKs beginning each audio frame. first bits audio frame defined "Tag Phase." remainder audio frame "Data Phase." AD1819B uses SYNC define beginning audio frame.
-18-
REV.
AD1819B
AC-Link protocol provides special 16-bit time slot (Slot wherein each conveys valid corresponding time slot within current audio frame. given position Slot indicates that corresponding time slot within current audio frame been assigned data stream, contains valid data. slot "tagged" invalid, responsibility source data, (AD1819B input stream, AC'97 controller output stream), stuff positions with during that slot's active time. AD1819B stuffs invalid slots with zeros ignores invalid input slots. Additionally, power savings, clock, sync, data signals halted. multiple codec operations, AD1819B supports enhanced mode communicating with additional codecs. Slave AD1819B codec uses Slots while Slave uses Slots shown following diagram.
ENHANCED MODE SLOT
SYNC
DATA LEFT LEFT RIGHT RIGHT LEFT LEFT RIGHT RIGHT LEFT LEFT RIGHT RIGHT
OUTGOING STREAMS INCOMING STREAMS
RSRVD
RSRVD
RSRVD
RSRVD
STATUS STATUS DATA
RSRVD
RSRVD
RSRVD
RSRVD
PHASE
SLAVE
SLAVE
DATA PHASE
Figure Standard Bidirectional Audio Frame
AC-Link Audio Output Frame (SDATA_OUT)
audio output frame data streams correspond multiplexed bundles digital output data targeting AD1819B's inputs control registers. briefly mentioned earlier, each audio output frame supports twelve 20-bit outgoing data time slots. Slot special reserved time slot containing bits that used AC-Link protocol infrastructure. Within Slot first global (SDATA_OUT Slot 15), which flags validity entire audio frame. "Valid Frame" this indicates that current audio frame contains least slot time valid data. next 12-bit positions sampled AC'97 indicate which corresponding time slots contain valid data. this input data streams differing sample rates transmitted across AC-Link fixed audio frame rate. following diagram illustrates time-slot-based AC-Link protocol.
PHASE 20.8 (48kHz) 12.2888MHz 81.4ns BIT_CLK SDATA_IN
CODEC READY SLOT(1) SLOT(2)
SLOT(12)
DATA PHASE
SYNC
PREVIOUS AUDIO FRAME
TIME SLOT "VALID" BITS TIME SLOT CONTAINS VALID DATA
SLOT
SLOT
SLOT
SLOT
Figure AC-Link Audio Output Frame
audio output frame begins with low-to-high transition SYNC. SYNC synchronous rising edge BIT_CLK. immediately following falling edge BIT_CLK, AD1819B samples assertion SYNC. This falling edge marks time when both sides AC-Link aware start audio frame. next rising edge BIT_CLK, AC'97 controller transitions SDATA_OUT into first position Slot (Valid Frame Bit). Each position presented AC-Link rising edge BIT_CLK, subsequently sampled AD1819B following falling edge BIT_CLK. This sequence ensures that data transitions, subsequent sample points both incoming outgoing data streams time aligned.
REV.
-19-
AD1819B
AD1819A SAMPLES SYNC ASSERTION HERE SYNC AC'97 CONTROLLER SAMPLES FIRST SDATA_OUT FRAME HERE
BIT_CLK
SDATA_OUT
VALID FRAME PREVIOUS AUDIO FRAME
SLOT SLOT
Figure Start Audio Output Frame
SDATA_OUT's composite stream justified (MSB first) with nonvalid slots' positions stuffed with AC'97 controller. AD1819B ignores invalid slots. event that there less than valid bits within assigned valid time slot, AC'97 controller always stuffs trailing nonvalid positions 20-bit slot with AD1819B ignores unused bits. example, consider 8-bit sample stream being played AD1819B's DACs. first 8-bit positions presented (MSB justified), followed next positions, which stuffed with AC'97 controller. When mono audio sample streams output from AC'97 controller, necessary that BOTH left right stream time slots filled with same data.
Slot Command Address Port
command port used control features request status (see Audio Input Frame Slots AD1819B functions including, limited mixer settings power management (refer control register section this specification). control interface architecture supports sixty-four 16-bit read/write registers, addressable even byte boundaries. Only even registers (00h, 02h, etc.) valid, register (01h, 03h, etc.) accesses discouraged (defaulting preceding even byte boundary-i.e., read will return 16-bit contents 00h). Note that shadowing control register file AC'97 controller option left open implementation AC'97 controller. AD1819B's control register file readable well writable. Audio output frame Slot communicates control register address, write/read command information AD1819B.
Command Address Port Assignments:
(19) (18:12) (11:0)
Read/Write Command Control Register Index Reserved
Read, Write) 16-Bit Locations, Addressed Even Byte Boundaries) (Stuffed with
first (MSB) sampled AD1819B indicates whether current control transaction read write operation. following 7-bit positions communicate targeted control register address. trailing 12-bit positions within slot reserved.
Slot Command Data Port
command data port used deliver 16-bit control register write data event that current command port operation write cycle indicated Slot 19). (19:4) (3:0) Control Register Write Data Reserved (Stuffed with Current Operation Write) (Stuffed with
current command port operation write, entire slot time should stuffed with AC'97 controller.
Slot Playback Left Channel
Audio output frame Slot composite digital audio left playback stream. typical "Games Compatible" this slot composed standard (.wav) output samples digitally mixed AC'97 controller host processor) with music synthesis output samples. sample stream resolution less than bits transferred, AC'97 controller should stuff trailing nonvalid positions within this time slot with
Slot Playback Right Channel
Audio output frame Slot composite digital audio right playback stream. typical "Games Compatible" this slot composed standard (.wav) output samples digitally mixed AC'97 controller host processor) with music synthesis output samples. sample stream resolution less than bits transferred, AC'97 controller should stuff trailing nonvalid positions within this time slot with
-20-
REV.
AD1819B
Slot 5-Slot Multicodec Communication
Slot Slave Playback Left Channel Slot Slave Playback Right Channel Slot Slave Playback Left Channel Slot Slave Playback Right Channel
Slot 6-Slot Reserved
Audio output frame Slot Slot reserved future should always stuffed with digital controller.
AC-Link Audio Input Frame (SDATA_IN)
audio input frame data streams correspond multiplexed bundles digital input data targeting AC'97 controller. case audio output frame, each AC-Link audio input frame consists twelve 20-bit time slots. Slot special reserved time slot containing bits used AC-Link protocol infrastructure. Within Slot first global (SDATA_IN Slot which flags whether AD1819B "Codec Ready" state. "Codec Ready" this indicates that AD1819B ready normal operation. This condition normal following deassertion power-on reset, example, while AD1819B's voltage references settle. When AC-Link "Codec Ready" indicator indicates that AC-Link AD1819B control status registers fully operational state subsections ready. Prior attempts putting AD1819B into operation AC'97 controller should poll first audio input frame (SDATA_IN Slot indication that AD1819B asserted "Codec Ready." Once AD1819B sampled, "Codec Ready" asserted next 12-bit positions sampled AC'97 controller indicate which corresponding time slots assigned input data streams that they contain valid data. following diagram illustrates time-slot-based AC-Link protocol.
PHASE 20.8 (48kHz) SYNC 12.288MHz 81.4ns BIT_CLK
CODEC READY
DATA PHASE
SDATA_IN
SLOT(1) SLOT(2)
SLOT(12)
PREVIOUS AUDIO FRAME
TIME SLOT "VALID" BITS TIME SLOT CONTAINS VALID DATA
SLOT
SLOT
SLOT
SLOT
Figure AC-Link Audio Input Frame
audio input frame begins with low-to-high transition SYNC. SYNC synchronous rising edge BIT_CLK. immediately following falling edge BIT_CLK, AD1819B samples assertion SYNC. This falling edge marks time when both sides AC-Link aware start audio frame. next rising BIT_CLK, AD1819B transitions SDATA_IN into first position Slot ("Codec Ready" bit). Each position presented AC-Link rising edge BIT_CLK, subsequently sampled AC'97 controller following falling edge BIT_CLK. This sequence ensures that data transitions, subsequent sample points both incoming outgoing data streams, time aligned.
AD1819A SAMPLES SYNC ASSERTION HERE SYNC AC'97 CONTROLLER SAMPLES FIRST SDATA_IN FRAME HERE
BIT_CLK
SDATA_IN
CODEC READY PREVIOUS AUDIO FRAME
SLOT SLOT
Figure Start Audio Input Frame
SDATA_IN's composite stream justified (MSB first) with nonvalid positions (for assigned and/or unassigned time slots) stuffed with AD1819B.
Slot Phase SDATA_IN
AD1819B capable sampling data from with resolution kHz. enable sample rate other than default kHz, DRQEN (Register 11). This allows request bits (these active) output SDATA_IN stream. digital controller should monitor valid bits determine when codec valid data ready send.
REV.
-21-
AD1819B
Phase Assignments:
(15) (14) (13) (12) (11) (10) (6:0)
Codec Ready Slot Valid Slot Valid Slot Valid/ADC Left Data Valid Slot Slot Valid/ADC Right Data Valid Slot Slot Valid/ADC Left Data Slave Valid Slot Slot Valid/ADC Right Data Slave Valid Slot Slot Valid/ADC Left Data Slave Valid Slot Slot Valid/ADC Right Data Slave Valid Slot Used
Slot Status Address Port
status port used monitor status AD1819B functions including, limited mixer settings power management. Audio input frame Slot stream echoes control register index, historical reference, data returned Slot (assuming that Slots been tagged "valid" AD1819B during Slot
Status Address Port Assignments:
(19) (18:12) (11) (10) (5:0)
RESERVED Control Register Index Request Slot Request Slot Request Slot Request Slot Request Slot Request Slot RESERVED
(Stuffed with (Echo Register Index Which Data Being Returned) Request, Request) Request, Request) Request, Request); Slave Request, Request); Slave Request, Request); Slave Request, Request); Slave (Stuffed with
first (MSB) generated AD1819B always stuffed with following 7-bit positions communicate associated control register address, trailing 12-bit positions stuffed with AD1819B.
Slot Status Data Port
status data port delivers 16-bit control register read data. (19:4) (3:0) Control Register Read Data RESERVED (Stuffed with Tagged "Invalid" AD1819B) (Stuffed with
Slot tagged "invalid" AD1819B, entire slot will stuffed with AD1819B.
Slot Record Left Channel
Audio input frame Slot left channel output AD1819B's input MUX, post-ADC. AD1819B transmits output data (MSB first), stuffs trailing nonvalid positions with fill 20-bit time slot.
Slot Record Right Channel
Audio input frame Slot right channel output AD1819B's input MUX, post-ADC. AD1819B transmits output data (MSB first), stuffs trailing nonvalid positions with fill 20-bit time slot.
Slot 5-Slot Multicodec Communication
Slot Slave Record Left Channel Slot Slave Record Right Channel Slot Slave Record Left Channel Slot Slave Record Right Channel
Slot 9-Slot Reserved
Audio input frame Slots 9-12 reserved future always stuffed with AD1819B.
AC-Link Power Mode
AC-Link signals placed power mode. When AD1819B's Power-Down Register (26h) programmed appropriate value, both BIT_CLK SDATA_IN will brought logic voltage level.
-22-
REV.
AD1819B
SYNC
BIT_CLK
SDATA_OUT
SLOT PREVIOUS FRAME
WRITE 0x26
DATA
SDATA_IN
SLOT PREVIOUS FRAME
NOTE: BIT_CLK SCALE
Figure AC-Link Power-Down Timing
BIT_CLK SDATA_IN transitioned immediately following decode write Power-Down Register (26h) with PR4. When AC'97 controller driver point where ready program AC-Link into power mode, Slots must only valid stream audio output frame. AC'97 controller should also drive SYNC SDATA_OUT after programming AD1819B this power "halted" mode. Once AD1819B been instructed halt BIT_CLK, special "wake-up" protocol must used bring AC-Link active mode, since normal audio output input frames communicated absence BIT_CLK.
Waking AC-Link
There methods bringing AC-Link power, halted mode. Regardless method, AC'97 controller that performs wake-up task. AC-Link protocol provides "Cold AC'97 Reset," "Warm AC'97 Reset." current power-down state would ultimately dictate which form AC'97 reset appropriate. Unless "cold" "register" reset write Reset Register) performed, wherein AD1819B registers initialized their default values, registers required keep state during powerdown modes. Serial Configuration Register (0x74) maintains state during register reset. Once powered down, reactivation AC-Link reassertion SYNC signal immediate. When AD1819B powers indicates readiness Codec Ready (Input Slot 15).
Cold AC'97 Reset
cold reset achieved asserting RESET least minimum specified time. SYNC SDATA_IN should held during rising edge RESET. driving RESET, BIT_CLK SDATA_IN will activated, AD1819B control registers will initialized their default power-on reset values. RESET asynchronous AD1819B input.
Warm AC'97 Reset
warm AC'97 reset will reactivate AC-Link without altering current AD1819B register values. warm reset signaled driving SYNC high minimum absence BIT_CLK. Within normal audio frames SYNC synchronous AD1819B input. absence BIT_CLK, however, SYNC treated asynchronous input used generation warm reset AD1819B.
REV.
-23-
AD1819B
MULTIPLE CODE CONFIGURATION Setting Multiple Codecs Configure Codec Resources
AD1819B used with additional AD1819 AD1819B codecs. order configure codecs Master, Slave Slave refer following table.
Ground;
Programing REGM (2:0) bits Serial Configuration Register (74h) allows digital controller read write access internal registers each codec according following table.
REGM2 REGM1 REGM0 Read Master Slave Master Slave Master Slave Master Write Master Slave Master, Slave Slave Master, Slave Slave Slave Master, Slave Slave
Configuration Slave Codec Slave Codec Master Codec AC'97 Mode Codec
XTAL_IN Slave Codecs "must" tied ground CHAIN_IN "must" tied ground last codec Slave 2-codec design) Slave 3-codec design). Figures
-24-
REV.
AD1819B
APPLICATIONS CIRCUITS
AD1819B been designed require minimum amount external circuitry. recommended applications circuits shown Figures 15-18. Reference designs AD1819B available obtained contacting your local Analog Devices' sales representative authorized distributor. Example shell programs establishing communications path between AD1819B ADSP-21xx also available.
+5AVDD TANT
+5AVDD TANT
+5DVDD TANT
+5DVDD TANT
100nF
100nF
100nF
100nF
1.37k 4.99k 100nF
100nF PC_BEEP
AVDD2 AVSS2
AVDD1 AVSS
DVSS1 DVDD1
DVSS2 DVDD2
CD_R
LINE_IN_R LINE_IN_L RESET MIC1 MIC2 SDATA_OUT SDATA_IN SYNC BIT_CLK DIGITAL CONTROLLER
CD_L CD_GND VIDEO_L VIDEO_R AUX_L AUX_R PHONE_IN MONO_OUT LINE_OUT_R LINE_OUT_L CHAIN_IN CHAIN_CLK
AD1819B
DVDD
AFILT1 AFILT2
FILT_L
FILT_R
CX3D
RX3D
VREFOUT
VREF
XTAL_IN
XTAL_OUT
100nF 270pF 270pF 47nF 600Z ANALOG GROUND 2.25VDC 100nF TANT 22pF
24.576MHz 22pF
DIGITAL GROUND
Figure Recommended Codec Application Circuit
REV.
-25-
AD1819B
RESET SDATA_OUT SDATA_IN SYNC RESET SDATA_OUT SDATA_IN SYNC BIT_CLK RFS0 SCLK0 SPORT0 DVDD DIGITAL CONTROLLER (ADSP-2181)
AD1819B
MASTER
BIT_CLK CHAIN_IN CHAIN_CLK
XTAL_IN
XTAL_OUT
24.576MHz 22pF 22pF
RESET SDATA_OUT SDATA_IN SYNC
AD1819B
SLAVE
BIT_CLK CHAIN_IN CHAIN_CLK
XTAL_IN
XTAL_OUT
RESET SDATA_OUT SDATA_IN SYNC
AD1819B
SLAVE
BIT_CLK CHAIN_IN CHAIN_CLK DVDD
XTAL_IN
XTAL_OUT
Figure Three Codec System Example
-26-
REV.
AD1819B
RESET SDATA_OUT SDATA_IN SYNC RESET SDATA_OUT SDATA_IN SYNC BIT_CLK RFS0 SCLK0 SPORT0 DVDD DIGITAL CONTROLLER (ADSP-2181)
AD1819B
MASTER
BIT_CLK CHAIN_IN CHAIN_CLK
XTAL_IN
XTAL_OUT
24.576MHz 22pF 22pF
RESET SDATA_OUT SDATA_IN SYNC
AD1819B
SLAVE
BIT_CLK CHAIN_IN CHAIN_CLK
XTAL_IN
XTAL_OUT
Figure Codec System Example
AD1819B
2.21k VREFOUT INPUT 100pF 10mV (mean) 200Hz FREQUENCY RESPONSE 5kHz -3dB NOTES: *MAY NEED OPTIMIZE SUIT MICROPHONE **SELECT MIC1 GAIN 20dB +12dB 10mV MICROPHONE OUTPUT. 10nF* MIC2 100nF MIC1**
Figure Microphone Input
REV.
-27-
AD1819B
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
48-Terminal LQFP (ST-48)
C3681-2-10/99
0.063 (1.60) 0.030 (0.75) 0.018 (0.45) SEATING PLANE VIEW
(PINS DOWN)
0.354 (9.00) 0.276 (7.0)
0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
0.006 (0.15) 0.002 (0.05)
0.007 (0.18) 0.004 (0.09)
0.0197 (0.5)
0.011 (0.27) 0.006 (0.17)
0.354 (9.00)
0.276 (7.0)
-28-
REV.
PRINTED U.S.A.

AC'97 SoundPort® Codec AD1819B ENHANCED FEATURES Support Multiple

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