ST62 ST63 PROGRAMMING MANUAL INTRODUCTION This manual deals

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ST62 ST63
PROGRAMMING MANUAL
INTRODUCTION This manual deals with description instruction addressing modes ST62,63 microcontroller series. manual divided main sections. first includes, after general family description, addressing modes description. second section includes detailed description ST62,63 instruction set. Each instruction described detail with differences between each series. software been designed fully hardware most efficient possible while keeping byte usage minimum; short provide byte efficient programming capability.
PROGRAMMING MODEL useful this stage outline programming model ST62,63 series, which mean available memory spaces, their relation another, interrupt philosophy Memory Spaces. devices have three different memory spaces: data, program stack. addressing modes memory space specific there need user specify which space being used more complex systems. stack space, which used automatically with subroutine interrupt management program counter storage, accessible user.
Table ST62,63 Series Core Characteristics
ST62,63 Series Stack Levels Interrupt Vectors Flags Sets Program Data Data
Figure Family Programming Model
REG. POINTER REG. POINTER
REGISTER REGISTER SHORT DIRECT ADDRESSING MODE
INDEX REGISTER
byte byte pages Reset Source
ACCUMULATOR
PROGRAM COUNTER
LEVELS STACK REGISTER
Carry Flag Instruction Carry Flag Instruction
NORMAL FLAGS
VA00 0423
Source
INTERRUPT FLAGS FLAGS
March 1993
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PROGRAMMING MODEL (Continued) Figure ST62 Data Space Example
Figure ST62 Program Memory Example
000h IMPLEMENTED 03Fh DATA ROM/EPROM WINDOW BYTE REGISTER REGISTER REGISTER REGISTER DATA BYTES 0BFh PORT DATA REGISTER PORT DATA REGISTER PORT DATA REGISTER RESERVED PORT DIRECTION REGISTER PORT DIRECTION REGISTER PORT DIRECTION REGISTER RESERVED INTERRUPT OPTION REGISTER DATA WINDOW REGISTER RESERVED PORT OPTION REGISTER PORT OPTION REGISTER PORT OPTION REGISTER RESERVED DATA REGISTER CONTROL REGISTER TIMER REGISTER TIMER DATA REGISTER TIMER TSCR REGISTER RESERVED 0D7h WATCHDOG REGISTER RESERVED 0FEh ACCUMULATOR 0FFh 0D8h 0D9h 0C0h 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h INTERRUPT VECTOR INTERRUPT USER RESET VECTOR 040h 07Fh 080h 081h 082h 083h 084h INTERRUPT VECTOR INTERRUPT INTERRUPT VECTOR TIMER INTERRUPT INTERRUPT VECTOR PORT INTERRUPT INTERRUPT VECTOR PORT INTERRUPT RESERVED RESERVED USER PROGRAM 1828 BYTES RESERVED IMPLEMENTED
0000h 07FFh 0800h 087Fh 0880h
0F9Fh 0FA0h 0FEFh 0FF0h 0FF1h 0FF2h 0FF3h 0FF4h 0FF5h 0FF6h 0FF7h 0FF8h 0FFBh 0FFCh 0FFDh 0FFEh 0FFFh
EPROM versions there reserved areas. These reserved bytes present ROM/OTP versions.
Data Memory Space. following registers data space have fixed addresses which hardware selected decrease access times reduce addressing requirements hence program length. Accumulator register location 0FFh. registers have addresses 80h-83h respectively. These used short direct addressing, reducing byte requirements program while first two, also used index registers indirect addressing mode. These registers part data space. ST62 ST63 data space bytes addressing) window multiplexing program available through dedicated data banking register.
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PROGRAMMING MODEL (Continued) data expansion lowest bytes data space (00h-03Fh) paged through data banking register. Self-check Interrupt Vector FF8h FF9h: (self-check interrupt routine) jump instruction reset interrupt routines must written into these locations. ST62 ST63 Program Memory Space. ST62 ST63 devices directly address bytes (program counter 12-bit wide). greater size obtained paging lower program through dedicated banking register located data space. higher program seen static contains reset, interrupt vectors following fixed locations: Reset Vector FFEh FFFh: (reset routine) Interrupt Vector FFCh FFDh: (NMI routine) user Vector FFAh FFBh user Vector FF8h FF9h Interrupt Vector FF6h FF7h (Int routine) Interrupt Vector FF4h FF5h (Int routine) Interrupt Vector FF2h FF3h (Int routine) Interrupt Vector FF0h FF1h (Int routine) Program Counter Stack Area. program counter twelve counter register since cover direct addressing byte program memory space. When interrupt subroutine occurs current value forward "pushed" into deep LIFO stacking area. return from routine (last value "popped" becomes current value. ST60/61 series offer 4-word deep stack program counter storage during interrupt sub-routines calls. ST62 ST63 series stack 6-word deep. Status Flags. Three pairs status flags, each pair consisting Zero flag Carry flag, available. ST62 ST63 additional third available. pair monitors normal status while second monitors state during interrupts; third flags monitors status during Maskable interrupt servicing. switching from another automatic interrupt requests request ST62,ST63 only) acknowledged when program returns after interrupt service routine. After reset, active, until first RETI instruction executed. ST62 ST63 Interrupt Description. ST62 ST63 devices have user interrupt vectors (plus vector testing purposes). Interrupt vector connected maskable interrupt input core. Interrupts from connected different on-chip external sources (see individual datasheets detailed information). interrupts globally disabled through interrupt option register. After reset ST62 ST63 devices mode, other interrupts accepted flags use, until RETI instruction performed. interrupt detected, special cycle will executed, during this cycle program counter loaded with related interrupt vector address. interrupt other interrupt routines time while normal interrupt can't interrupt each other. more then interrupt waiting service, they will accepted according their priority. Interrupt highest priority while interrupt lowest. This priority relationship fixed. Figure ST62/ST63 Stack Area
PROGRAM COUNTER
STACK LEVEL WHEN RETI OCCURS STACK LEVEL STACK LEVEL STACK LEVEL STACK LEVEL STACK LEVEL
WHEN CALL INTERRUPT REQUEST OCCURS
VA000424
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ADDRESSING MODES family gives user nine addressing modes access data locations. Some these specifically tailored particular instruction types groups while others designed reduce program length operating time using hardware facilities such registers. data locations either program memory space data memory space when operating user software. addition stack space program counter this controlled internal programming accessible user. This section will describe addressing modes which provided user. following complete list available addressing modes: Inherent Direct Short Direct Indirect Immediate Program Counter Relative Extended Direct Test Branch Inherent. instructions using inherent addressing mode opcode contains information necessary execution. instructions using this mode Byte instructions.
Example:
Instruction WAIT STOP Comments Puts into power WAIT mode Puts into lowest power mode Returns from interrupt. Pops from stack.Sets normal flags
RETI
Direct. direct addressing mode address data given program memory byte immediately following opcode. This data location data memory space. instructions using this mode Bytes instructions, lasting Four Cycles.
Program Memory
Data Memory
O.A. OPERAND
Program Memory
Data Memory
Opcode Operand Address
Example:
Instruction A,0A3h Comments Loads accumulator with value found location data space. value found locations data memory subtracted from value accumulator.
Opcode
A,11h
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ADDRESSING MODES (Continued) Short Direct. core four fixed location registers data space which addressed short direct manner. addresses names these registers (X), (Y), (W). When using this addressing mode data these registers address part opcode. instructions using this mode Byte instructions, lasting Four Cycles.
Program Memory Data Memory Program Memory Data Memory
R.A.
O.A.
Opcode R.A. Register Address
Example:
Instruction A,(X) Comments value registers pointed register loaded into accumulator. value register pointed register added accumulator value. value register pointed register incremented.
A,(Y)
Opcode Operand Address
Example:
Instruction Comments value register (80h) loaded into accumulator. register incremented.
Immediate. immediate addressing mode operand found program byte which last byte instruction. This addressing mode used initializing data space registers supplying constants. Instructions using this mode Three Bytes instructions, lasting Four Cycles.
Indirect. indirect mode must either (80h) (81h) register. This register contains address data. operand data space address pointed content registers. instructions using this mode Byte instructions, lasting Four Cycles.
Program Memory
Data Memory
D.A. OPERAND DESTINATION
Opcode D.A. Destination Address
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ADDRESSING MODES (Continued) Example:
Instruction 34h,DFh Comments Loads immediate value into data space location 34h. immediate value substracted from acc. ADDRESS CURRENT Program Memory Stack
SUBI A,22h
Program Counter Relative. This addressing mode used only with conditional branches within program. opcode byte contains data which fixed offset value. This offset added program counter give address next instruction. offset have value range +16. determined last five bits opcode. instructions using this mode Byte Instructions, lasting Cycles.
Opcode
Example:
Instruction 3FAh Comments Loads 3FAh into program counter continues with instruction 3FAh. current pushed onto stack loaded with value associated ROU1 label
Program Memory
D.A.
CURRENT
CALL ROU1
NEXT INSTRUC.
Opcode D.A. Destination Address
Example:
Instruction Comments carry flag then PC+3 zero flag (i.e result previous instruction zero) then PC-7
absolute jump address also label that automaticallyhandled assembler. Direct. This addressing mode allows user clear specified data memory register. address given form: "b,R" where number address register. determined three bits opcode register address given second byte. instructions using this mode Byte instructions, lasting Four Cycles.
Program Memory Data Memory
JRNZ
D.A.
relative jump address also label that automatically handled assembler. Extended. extended addressing mode used make long jumps within program memory space (4K). data requires bits provided half opcode byte second byte. instructions using this mode Bytes instructions, lasting Four Cycles.
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Opcode D.A. Destination Address
ST62,63 Programming Manual
ADDRESSING MODES (Continued) Example:
Instruction 0,PORT Comments Sets accumulator Clears PORT register
structions using this mode Three Byte instructions, lasting Five Cycles. Example:
Instruction Comments three data memory register associated PORT label then PC=PC+LAB1 (where LAB1 jump displacement associated label data memory register reset then PC=PC-72.
register address associated label that automatically handled assembler. Test Branch. test addressing mode used conditional jump instructions which jump depends result test. opcode specifies tested, byte following opcode register address data space, third byte jump displacement, which range -126 +129. This displacement determined using label, which converted assembler. state tested also copied into carry flag.
3,PORT,LAB1
0,0Ah,-72
register address jump displacement associated labels that automatically handled assembler.
Program Memory R.A. J.D.
Data Memory
INSTRUCTION
Opcode R.A. Relative Address J.D. Jump Displacement
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ST62 ST63 INSTRUCTION ST62,63 instructions divided functionally into following seven groups. LOAD STORE ARITHMETIC LOGIC CONDITIONAL BRANCH JUMP CALL MANIPULATION CONTROL IMPLIED following summary shows instructions belonging each group, number operands required each instructions number machine cycles. flag behaviour usually same both ST62 ST63. only difference present instructions specified detailed description. Note: following tables: Affected Affected Table Load Store Instructions
Instruction Bytes Cycles Flags JRNC Bytes Instruction (X,Y) A/rr A/rr (X,Y) SUBI Cycles Flags
Table Conditional Branch Insructions
Instruction Bytes Cycles Flags
Table Arithmetic Logic Instructions
Bytes Instruction (X,Y) ADDI (X,Y) ANDI Cycles Flags
JRNZ
Table Jump Call Instructions
Instruction Bytes Cycles CALL Flags
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ST62 ST63 INSTRUCTION (Continued) Table Manipulation Instructions
Instruction Bytes Cycles Flags
Table Control Instructions
Instruction RETI STOP WAIT Bytes Cycles Flags
Table Addressing Modes/Instruction Table
Instruction CALL JRC, JRNC JRZ, JRNZ JRR, RES, RETI STOP, WAIT
Notes: INH. Inherent, DIR: Direct, Sh.DIR: Short Direct, IND. Indirect, IMM: Immediate, PCR: Program Counter Relative EXT. Extended, DIR: Direct, TEST.: Test Affected Affected
Test
Flags
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ST62 ST63 INSTRUCTION (Continued) Table Opcode
0000 JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ 0001 CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC 0011 b0,rr,ee b0,rr,ee b4,rr,ee b4,rr,ee b2,rr,ee b2,rr,ee b6,rr,ee b6,rr,ee b1,rr,ee b1,rr,ee b5,rr,ee b5,rr,ee b3,rr,ee b3,rr,ee b7,rr,ee b7,rr,ee 0110 a,(x) a,nn a,(x) a,nn a,(x) ADDI a,nn (x),a a,(x) ANDI a,nn a,(x) SUBI a,nn 1000 JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ JRNZ 1001 JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC JRNC b0,rr b0,rr b4,rr b4,rr b2,rr b2,rr b6,rr b6,rr b1,rr b1,rr b5,rr b5,rr b3,rr b3,rr b7,rr b7,rr 1100 1101 rr,nn RETI STOP 1111 a,(y) a,rr a,(y) a,rr a,(y) a,rr (y),a rr,a a,(y) a,rr a,(y) a,rr
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
WAIT
Abbreviations Addressing Modes: Direct Short Direct Immediate Inherent Extended Direct Test Program Counter Relative Indirect
Legend: Indicates Illegal Instructions Displacement Address 1byte dataspace address byte immediate data address Displacement
Cycles Operand Bytes Addressing Mode
Mnemonic
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ST62 ST63 INSTRUCTION (Continued) Table Instruction Cycle-by-Cycle Summary
Instruction Cycles Cycles(#) Address Data Activity Notes
Indirect Addressing Mode ADD, AND, DEC, INC, ADD, AND, DEC, INC, Opcode Opcode Opcode Opcode Address(*) Address Address Address Opcode Next Instruction Next Instruction Next Instruction Opcode Next Instruction Next Instruction Data Decode Opcode Read Operand Address Read Operand Execute Instruction Decode Opcode Read Operand Address Read Operand Execute Instruction Data Space Addressed Data Space Addressed
Opcode Address(*) Opcode Address Opcode Address Data Space
Direct Addressing Mode ADD, AND, DEC, INC, RES, SET, LSA, SUB, ADD, AND, DEC, INC, RES, SET, LSA, SUB, Opcode Opcode Opcode Opcode Address(*) Address Address Address Opcode Operand Address Operand Address(*) Next Instruction Opcode Operand Address Operand Address(#) Data Decode Opcode Address Data Space Read Operand Execute Instruction Decode Opcode Address Data Space Read Operand Execute Instruction Data Space Addressed Data Space Addressed
Opcode Address(*) Opcode Address Opcode Address Data Space Add.
Immediate Addressing Mode ADDI, ANDI, CPI, LDI, SUBI Opcode Opcode Opcode Opcode Opcode Opcode Opcode Opcode Address(*) Address Address +1(*) Address +2(*) Address(*) Address Address AdDress Opcode Immediate Operand Immediate Operand Next Instruction Opcode Register Address Immediate Operand Next Opcode Opcode Register Address Immediate Operand Operand Decode Opcode Idle Read Operand Execute Instruction Decode Opcode Read Register Address Read Immediate Operand Write Operand Reg. Decode Opcode Read Register Address Read Immediate Operand Write Operand Reg. Data Space Addressed Data Space Addressed
Opcode Address(*) Opcode Address Opcode Address Data Space Add.
Short Direct Addressing Mode Opcode Opcode Opcode Opcode Address(*) Address Address Address Opcode Next Opcode Next Opcode Next Opcode Decode Opcode Define Data Space Add. Read Operand Execute Instruction
DEC, INC,
Other Instructions
Notes:*. Valid only beginning cycle Valid only until cycle
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ST62 ST63 INSTRUCTION (Continued) Table Instruction Cycle-by-Cycle Summary (Continued)
Instruction Cycles Cycles(#) Address Opcode Opcode Opcode Opcode Opcode Opcode Opcode Opcode Address(*) Address Address Address +2(*) Address(*) Address Address Address Data Opcode Subroutine Address Subroutine Address Next Instruction Opcode Next Opcode Next Opcode Next Opcode Next Opcode Opcode Jump Address Following Instr. Following Instr. Opcode Following Instr. Opcode Operand Address Branch Value Branch Value Following Instr. Opcode Operand Address Data Branch Value Data Opcode Next Opcode Opcode Next Opcode Opcode Next Opcode Next Opcode Next Opcode Opcode Next Opcode Activity Decode Opcode Increment Stack Pointer Push Return Address Calculate Subroutine Add. Decode Opcode Calculate Acc. Address Read Accumulator Complement Accumulator Calculate Interrupt Add. Push Return Address Switch Flag Decode Opcode Idle Read Jump Address Calculate Jump Address Decode Opcode Calculate Offset Decode Opcode Read Operand Test Operand Fetch Branch Value Calculate Address Decode Opcode Read Operand Test Operand Fetch Branch Value Calculate Address Decode Opcode Return Address Decode Opcode Return Address Switch Flag Decode Opcode Calculate Acc. Address Read Accumulator Shifted Decode Opcode Stop/Wait Oscillator Data Space Addressed Data Space Addressed Note Notes
CALL
INTERRUPT
Next opcode address Opcode Opcode Opcode Opcode Address(*) Address Address Address
JRC, JRNC, JRZ, JRNZ
Opcode Address(*) Opcode Address Opcode Opcode Opcode Opcode Opcode Address(*) Address +1(*) Address +2(*) Address +2(*) Address +3(*)
JRR,
JRR,
Opcode Address(*) Opcode Address +1(*) Data Space Add.(#) Opcode Address +2(*) Data Space Add.(#) Opcode Address(*) Return Address Opcode Address(*) Return Address Opcode Opcode Opcode Opcode Address(*) Address Address Address
RETI
STOP, WAIT
Opcode Address(*) Opcode Address
Notes: Valid only beginning cycle Valid only until cycle oscillator build time plus oscillator clocks stop instruction been executed before interrupt occured
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Addition
Mnemonic: Function: Description: Addition contents source byte added accumulator leaving result accumulator. source register remains unaltered. destination must accumulator.
Operation:
Instruction Format dst,src A,(X) A,(Y) A,rr
Opcode (Hex)
Bytes
Cycles
Flags
Notes: rr.1 Byte dataspace address. result zero. Cleared otherwise. cleared before operation than there overflow from 8-bit result.
Example:
data space register contains value accumulator holds value then instruction, A,22h will cause accumulator hold (i.e. 33+20).
Addressing Modes:
Source: Destination:
Direct, Indirect Accumulator
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ADDI
Addition Immediate
Mnemonic: Function: Description: ADDI Addition Immediate immediately addressed data (source) added accumulator leaving result accumulator. destination must accumulator.
Operation:
Instruction Format ADDI dst,src ADDI A,nn
Opcode (Hex)
Bytes
Cycles
Flags
Notes: nn.1 Byte immediate data result zero. Cleared otherwise cleared before operation than there overflow from 8-bit result
Example:
accumulator holds value then instruction, ADDI A,22h will cause accumulator hold (i.e. 22+20).
Addressing Modes:
Source: Destination:
Immediate Accumulator
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Logical
Mnemonic: Function: Description: Logical This instruction logically ANDs source register accumulator. result left destination register source unaltered. destination must accumulator.
Operation:
Inst. Format dst,src A,(X) A,(Y) A,rr
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: rr.1 Byte dataspace address unaffected
result zero. Cleared otherwise.
Example:
data space register contains binary value11110000 accumulator contains binary value 11001100 then instruction, A,54h will cause accumulator altered to11000000.
Addressing Modes:
Source: Destination:
Direct, Indirect. Accumulator
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ANDI
Logical Immediate
Mnemonic: Function: Description: ANDI Logical Immediate This instruction logically ANDs immediate data byte accumulator. result left accumulator. source immediate data destination must accumulator.
Operation:
Inst. Format ANDI dst,src ANDI A,nn
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: nn.1 Byte immediate data unaffected
result zero. Cleared otherwise.
Example:
accumulator contains binary value 00001111 then instruction, ANDI A,33h will cause accumulator hold value 00000011.
Addressing Modes:
Source: Destination:
Immediate Accumulator
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CALL
Call Subroutine
Mnemonic: Function: Description: CALL Call Subroutine CALL instruction used call subroutine. "pushes" current contents program counter (PC) onto stack. specified destination address then loaded into points first instruction procedure. procedure RETurn instruction used return original program flow. pops stack back into Because stack levels deep (ST60) levels deep (ST62,ST63), maximum four/six calls interrupts nested. more calls nested, values stacked latest will lost. this case returns will return values stacked first. dst; stack
Operation:
Inst. Format CALL CALL
OPCODE (Hex) c0001
Bytes
Cycles
Flags
Notes: abc.the three half bytes twelve address, start location subroutine. affected
Example:
current 345h then instruction, CALL 8DCh current 345h pushed onto stack will beloaded with value 8DCh. next instruction executed will instruction 8DCh, first instruction called subroutine.
Addressing Modes:
Extended
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Clear
Mnemonic: Function: Description: Operation: Clear destination register cleared 00h.
Inst. Format
OPCDE (Hex)
Bytes
Cycles
Flags
Notes: Byte dataspace address
set, reset
unaffected
Example:
data space register contains value 33h, will cause register hold 00h.
Addressing Modes:
Direct
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Complement
Mnemonic: Function: Description: Complement This instruction complements each accumulator; bits which cleared vice-versa. destination must accumulator.
Operation:
Inst. Format
OPCODE (Hex)
Bytes
Cycles
Flags
Note
result zero. Cleared otherwise.
will contain value before operation.
Example:
accumulator contains binary value 10111001 then instruction will cause accumulator changed 01000110 carry flag (since original
Addressing Modes:
Inherent
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Compare
Mnemonic: Function: Description: Compare This instruction compares source byte (subtracted from) with destination byte, which must accumulator. carry zero flags record result this comparison. destination must accumulator, will changed.
Operation:
Inst. Format dst,src A,(X) A,(Y) A,rr
OPCODE (Hex)
Bytes
Cycles
Flags
Note: Byte dataspace address
ST60
result zero. Cleared otherwise.
src, cleared src.
ST62/63
result zero. Cleared otehrwise.
src, cleared src.
Example:
accumulator contains value 11111000 register contains value 00011100 then instruction, A,34h will clear Zero flag Carry flag indicating that ST60)
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Compare Immediate
Mnemonic: Function: Description: Compare Immediate This instruction compares immediately addressed source byte (subtracted from) with destination byte, which must accumulator. carry zero flags record result this comparison. dst-src source must immediately addressed data destination must accumulator, that will changed.
Operation:
Inst. Format dst,src A,nn
OPCODE (Hex)
Bytes
Cycles
Flags
Note: nn.1 Byte immediate data.
ST60
result zero. Cleared otherwise.
src, cleared src.
ST62/63
result zero. Cleared otherwise.
src, cleared src.
Example:
accumulator contains value 11111000 then instruction, A,00011100B will clear Zero flag Carry flag indicating that ST60).
Addressing Modes:
Source: Destination:
Immediate Accumulator
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Decrement
Mnemonic: Function: Description: Operation: Decrement destination register's contents decremented one. dst-1
Inst. Format
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: rr.1 Byte dataspace address unaffected
result zero. Cleared otherwise.
Example:
register contains value data space register contains value then instruction, will cause data space register contain value 15h.
Addressing Modes:
Short direct, Direct, Indirect.
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Increment
Mnemonic: Function: Description: Operation: Increment destination register's contents incremented one. dst+1
Inst. Format
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: rr.1 Byte dataspace address unaffected
result zero. Cleared otherwise.
Example:
register contains value data space register contains value then instruction will cause data space register contain value 17h.
Addressing Modes:
Short direct, Direct, Indirect.
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Jump
Mnemonic: Function: Description: Jump (Unconditional) instruction replaces value with twelve value thus causing simple jump another location program memory. previous value lost, stacked.
Operation:
Inst. Format
OPCODE (Hex) c1001
Bytes
Cycles
Flags
Notes: abc.the three half bytes twelve address. affected
Example:
instruction, 5CDh will cause loaded with 5CDh program will continue from that location.
Addressing Modes:
Extended
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Jump Relative Carry Flag
Mnemonic: Function: Description: Jump Relative Carry Flag This instruction causes carry flag tested this flag then jump performed within program memory. This jump range relative value. displacemente five bits. than next instruction executed. C=1, where displacement
Operation:
Inst. Format e110
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: displacement range *.C,Z affected
Example:
carry flag then instruction, will cause branch forward PC+8. user labels asindentifiers assembler will automatically allow jump range +16.
Addressing Modes:
Program Counter Relative
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JRNC
Jump Relative Carry Flag
Mnemonic: Function: Description: JRNC Jump Relative Carry Flag This instruction causes carry flag tested this flag cleared zero then jump performed within program memory. This jump range relative value. dispacement five bits. then next instruction executed. C=0, where displacement
Operation:
Inst. Format JRNC e010
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: displacement range *:C,Z affected
Example:
carry flag cleared then instruction, JRNC will cause branch backward PC-5. user labels identifiers assembler will automatically allow jump range +16.
Addressing Modes:
Program Counter Relative
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JRNZ
Jump Relative Zero Flag
Mnemonic: Function: Description: JRNZ Jump Relative Zero Flag This instruction causes zero flag tested this flag cleared zero then jump performed within program memory. This jump range relative value. displacement five bits. then next instruction executed. Z=0, where displacement
Operation:
Inst. Format JRNZ e000
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: displacement range +16. *.C,Z affected
Example:
zero flag cleared then instruction, JRNZ will cause branch backward PC-5. user labels identifiers assembler will automatically allow jump range +16.
Addressing Modes:
Program Counter Relative
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Jump Relative Reset
Mnemonic: Function: Description: Jump Relative RESET This instruction causes specified given dataspace register tested. this reset (=0) then value will changed relative jump will performed within program. relative jump range -126 +129. tested reset then next instruction executed. bit=0, where displacement
Operation:
Inst. Format b,rr,ee
OPCODE (Hex) b00011
Bytes
Cycles
Flags
Notes: bit-address rr.1 Byte dataspace address ee.8 displacement range -126 +129
affected .The tested shifted into carry.
Example:
dataspace register reset PC=110 then instruction, 70h, will cause changed (110-20) instruction starting that address program memory next instruction executed. user advised labels conditional jumps. relative jump will calculated assembler. jump must range -126 +129.
Addressing Modes:
Test
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Jump Relative
Mnemonic: Function: Description: Jump Relative This instruction causes specified given dataspace register tested. this (=1) then value will changed relative jump will performed within program. relative jump range -126 +129. tested then next instruction executed. bit=1, where displacement
Operation:
Inst. Format b,rr,ee
OPCODE (Hex) b10011
Bytes
Cycles
Flags
Notes: bit-address rr.1 Byte dataspace address ee.8 displacement range -126 +129
affected .The tested shifted into carry.
Example:
dataspace register PC=123 then instruction, 7,AFh,+25 will cause changed (123+25) instruction starting that address program memory next instruction executed. user advised labels conditional jumps. relative jump will calculated assembler. jump must range -126 +129.
Addressing Modes:
Test
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Jump Relative Zero Flag
Mnemonic: Function: Description: Jump Relative Zero Flag This instruction causes zero flag tested this flag then jump performed within program memory. This jump range relative value. displacement five bits. then next instruction executed. Z=1, where displacement
Operation:
Inst. Format e100
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: displacement range +16. *.C,Z affected
Example:
zero flag then instruction, will cause branch forward PC+8. user labels identifiers assembler will automatically allow jump range +16.
Addressing Modes:
Program Counter Relative
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Load
Mnemonic: Function: Description: Load contents source register loaded into destination register. source register remains unaltered previous contents destination register lost. Either source destination must accumulator.
Operation:
Inst. Format dst,src A,(X) (X), A,(Y) (Y),A A,rr rr,A
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: rr.1 Byte dataspace address affected
result zero. Cleared otherwise.
Example:
data space register contains value then instruction; A,34h will cause accumulator loaded with value 45h. Register will keep value 45h.
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Load Immediate
Mnemonic: Function: Description: Load Immediate immediately addressed data (source) loaded into destination data space register. source always immediate data while destination accumulator, X,Y,V,W registers available data space registers.
Operation:
Inst. Format dst,src A,nn X,nn Y,nn V,nn W,nn rr,nn
OPCODE (Hex)
Bytes
Cycles
Flags
Notes: rr.1 Byte dataspace address nn.1 Byte immediate value
*.Z, affected
result zero. Cleared otherwise.
Example:
instruction 34h,45h will cause value loaded into data register location 34h.
Addressing Modes:
Source: Destination:
Immediate Direct
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Operation
Mnemonic: Function: Description: Operation: Operation action performed this instruction. typically used timing delay. Operation
Inst. Format
OPCODE (Hex)
Bytes
Cycles
Flags
Note: affected
Addressing Modes:
Program Counter Relative
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Reset
Mnemonic: Function: Description: Reset RESET instruction used reset specified given register data space.
Operation:
Inst. Format bit,dst b,rr
OPCODE (Hex) b01011 b01011
Bytes
Cycles
Flags
Notes: bit-address rr.1 Byte dataspace address *.C,Z affected
Example:
register dataspace contains 11111111 then instruction, 4,23h will cause register hold 11101111.
Addressing Modes:
Direct
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Return from Subroutine
Mnemonic: Function: Description: Return From Subroutine This instruction normally used subroutine return previously executed procedure. previously stacked program counter (stacked during CALL) popped back from stack. next statement executed that addressed contents stack already reached highest level more stacked) before executed, program execution will continued next instruction after RET. Stacked
Operation:
Inst. Format
OPCODE (Hex)
Bytes
Cycles
Flags
Note: affected
Example:
current value 456h value stack 3DFh then instruction, will cause value 456h lost current value 3DFh.
Addressing Modes:
Inherent
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RETI
Return from Interrupt
Mnemonic: Function: Description: RETI Return from Interrupt This instruction marks interrupt service routine returns ST60/62/63 state before interrupt. "pops" (last value from stack into current This instruction also causes ST60/62/63 switch from interrupt flags normal flags. RETI instruction also applies routine ST62/63 devices; this case instruction causes switch from flags normal flags acknowledged inside normal routine) standard interrupt flags acknowledged inside standard interrupt service routine). addition RETI instruction also clears interrupt mask (also mask ST62/63) which when interrupt occurred. stack already reached highest level more stacked) before RETI executed, program execution will continued with next instruction after RETI. Because ST60 interrupt mode after reset (NMI mode ST62/63), RETI executed switch normal flags enable interrupts starting routine. call executed during starting routine, program execution will continue with instruction after RETI (supposed interrupt active). Operation: Actual Flags Normal Flags Stacked Standard Interrupt flags acknowledged inside standard interrupt service (ST62/63 only).
Inst. Format RETI
OPCODE (Hex)
Bytes
Cycles
Flags
Note: normal flag will used from
Example:
current value 456h value stack 3DFh then instruction RETI
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Rotate Left Through Carry
Mnemonic: Function: Description: Rotate Left through Carry This instruction moves each accumulator place left (i.e. towards MSBit. MSBit (bit moved into carry flag carry flag moved into LSBit (bit0) accumulator.
Operation:
ACCUMULATOR
dst(0) dst(7) dst(n+1) dst(n), This instruction only performed accumulator.
Inst. Format OPCODE (Hex) Bytes Cycles Flags
Note result zero. Cleared otherwise. will contain value before operation.
Example:
accumulator contains binary value 10001001 carry flag then instruction, will cause accumulator have binary value 00010010 carry flag
Addressing Modes:
Inherent
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Mnemonic: Function: Description: instruction used specified given register data space.
Operation:
Inst. Format bit,dst b,rr
OPCODE (Hex) b11011 b11011
Bytes
Cycles
Flags
Notes: bit-address Byte dataspace address affected
Example:
register dataspace contains 00000000 then instruction, 4,23h will cause register hold 00010000.
Addressing Modes:
Direct
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Shift Left Accumulator
Mnemonic: Function: Description: Shift Left Accumulator This instruction implements addition accumulator itself (i.e adoubling accumulator) causing arithmetic left shift value register. A,FFh This instruction only performed accumulator.
Operation:
Inst. Format
OPCPDE (Hex)
Bytes
Cycles
Flags
Note: result zero. Cleared otherwise. will contain value before operation.
Example:
accumulator contains binary value 11001101 then instruction, will cause accumulator have binary value 10011010 carry flag
Addressing Modes:
Inherent
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STOP
Stop Operation
Mnemonic: Function: Description: STOP Stop operation This instruction used putting ST60/62/63 into stand-by mode which power consumption reduced minimum. on-chipperipherals oscillator stopped (for some peripherals,A/D example, necessary individually turn-off macrocell before entering STOP instruction). restart processor external interrupt reset needed. Stop Processor
Operation:
Inst. Format STOP
OPCODE (Hex)
Bytes
Cycles
Flags
Note affected
Addressing Mode:
Inherent
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Subtraction
Mnemonic: Function: Description: Operation: Subtraction This instruction subtracts source value from destination value. dst-src destination must accumulator.
Inst. Format dst,src A,(X) A,(Y) A,rr
OPCODE (Hex)
Bytes
Cycles
Flags
Note: rr.1 Byte dataspace address
ST60
result zero. Cleared otherwise.
src, cleared src.
ST62/63
result zero. Cleared otherwise.
src, cleared src.
Example:
register contains value 23h, dataspace register contains value accumulator contains value then instruction, A,(Y) will cause accumulator hold value (i.e. 78-53). zero flag cleared carry flag ST60), indicating that result
Addressing Modes:
Source:
Indirect,Direct
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SUBI
Subtraction Immediate
Mnemonic: Function: Description: SUBI Subtraction Immediate This instruction causes immediately addressed source data subtracted from accumulator. destination must accumulator.
Operation:
Inst. Format SUBI dst,src SUBI A,nn
Note: Byte immediate data
OPCODE (Hex)
Bytes
Cycles
Flags
ST60
result zero. Cleared otherwise.
src, cleared src.
ST62/63
result zero. Cleared otherwise.
src, cleared src.
Example:
accumulator contains value then instruction, SUBI A,25 will cause accumulator contain value 31h. zero flag cleared carry flag ST60), indicating that result
Addressing Modes:
Source: Destination:
Immediate Accumulator
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WAIT
Wait Processor
Mnemonic: Function: Description: WAIT Wait Processor This instruction used putting ST60/62/63 into stand-by mode which power consumption reduced minimum. Instruction execution stopped, oscillator some on-chip peripherals continue work. restart processor interrupt from active on-chip peripheral (eg. timer), external interrupt reset needed. on-chip peripherals active during wait, ST60/62/63 data sheets. stand-by mode
Operation:
Inst. Format WAIT
OPCODE (Hex)
Bytes
Cycles
Flags
Note affected
Addressing Modes:
Inherent
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsability consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics rights reserved. Purchase Components SGS-THOMSON Microelectronics conveys license under Philips Patent. Rights these components system granted provided that system conforms Standard Specification defined Philips. SGS-THOMSON Microelectronics Group Companies Australia Brazil France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
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ST62 ST63 PROGRAMMING MANUAL INTRODUCTION This manual deals

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