PIAFE PROGRAMMABLE ISDN AUDIO FRONT FEATURES: Complete CODEC FILT

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

PIAFE PROGRAMMABLE ISDN AUDIO FRONT FEATURES: Complete CODEC FILT

Datasheet Thumbnail

Top Searches for this datasheet

ST5088
PIAFE PROGRAMMABLE ISDN AUDIO FRONT
FEATURES: Complete CODEC FILTER system including: ANALOG DIGITAL DIGITAL ANALOG CONVERTERS POWERFUL ANALOG FRONT CAPABLE INTERFACE DIRECTLY: Microphone Dynamic, Piezo Electrete Earpiece down 150nF Loudspeaker down Buzzer 600nF. TRANSMIT BAND-PASS FILTER ACTIVE NOISE FILTER RECEIVE LOW-PASS FILTER WITH CORRECTION MU-LAW A-LAW SELECTABLE COMPANDING CODER DECODER PRECISION VOLTAGE REFERENCE Phones Features: DUAL SWITCHABLE MICROPHONE AMPLIFIER INPUTS. GAIN PROGRAMMABLE: RANGE, STEP. LOUDSPEAKER AMPLIFIER OUTPUT. SWITCHABLE MAXIMUM GAIN: +9dB/+27dB WITH AUTOMATIC DIGITAL ANTICLIPPING SYSTEM. aTTENUATION PROGRAMMABLE: 30dB RANGE, STEP. SEPARATE EARPIECE AMPLIFIER OUTPUT. ATTENUATION PROGRAMMABLE: RANGE, STEP. AUXILIARY TAPE RECORDER ANALOG INTERFACE: COMBINED OUTPUT. AUXILIARY SWITCHABLE EXTERNAL RING INPUT (EAIN). TRANSIENT SUPRESSION SIGNAL DURING POWER INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. ATTENUATION PROGRAMMABLE: RANGE, STEP, INDEPENDENT FROM CONTROL. INTERNAL RING TONE GENERATOR INCLUDING DTMF TONES, SINEWAVE SQUAREWAVE WAVEFORMS. ATTENUATION PROGRAMMABLE: RANGE, STEP. RINGER CONTROL PROGRAMMABLE INDecember 1994
SO28
PLCC28
ORDERING NUMBERS: ST5088D ST5088FN
TERNALLY (µP) EXTERNALLY (pin COMPATIBLE WITH HANDS-FREE CIRCUIT TEA7540. CHIP SWITCHABLE ANTI-ACOUSTIC FEED-BACK CIRCUIT (ANTI-LARSEN). General Features: EXTENDED TEMPERATURE RANGE OPERATION 25°C +85°C. EXTENDED POWER SUPPLY RANGE 5V±10%. OPERATING POWER (TYPICAL). STANDBY POWER (TYPICAL). CMOS DIGITAL INTERFACES. SINGLE SUPPLY. DIGITAL LOOPBACK TEST MODE. PROGRAMMABLE DIGITAL CONTROL INTERFACES: Digital Interface associated with separate serial Control Interface MICROWIRE compatible. interface compatible.
Functionality guaranteed range 25°C +85°C; Timing Electrical Specifications guaranteed range +70°C.
APPLICATIONS: ISDN TERMINALS. DIGITAL TELEPHONES APPLICATIONS
1/33
This advanced information product development undergoing evaluation. Details subject change without notice.
ST5088
CONNECTION (Top view)
VFR+ VFRVCC LSLS+ CO/A2 CI/A1
D93TL047
EAIN GNDA 2VCCA 1MIC CS-/A3 CCLK/A0 N.C. MCLK
SO28
PLCC28
BLOCK DIAGRAM
2/33
ST5088
TYPICAL ISDN TELEPHONE APPLICATION
3/33
ST5088
GENERAL DESCRIPTION ST5088 PIAFE combined CODEC/FILTER device optimized ISDN Terminals Digital Telephone applications. This device A-law Mu-law selectable offers number programmable functions accessed through serial control channel. Depending mode selected, channel control provided means separate serial channel control MICROWIRE compatible multiplexed with voice data channel compatible format requiring only digital interface pins. When separate serial control interface selected, interface compatible with Combo Combo families devices such ETC5057/54, TS5070/71. PIAFE built using SGS-THOMSON's advanced HCMOS process. Transmit section PIAFE consists amplifier with switchable high impedance inputs followed programmable gain amplifier, active antialiasing pre-filter provide attenuationof high frequency noise, order switched capacitor band pass transmit filter A-law/Mu-law selectable compandig encoder. Receive section consist A-law/Mu-law selectable expanding decoder which reconstructs analog sampled data signal, 3400 pass filter with correction followed separate programmable attenuation blocks power amplifiers: used drive earpiece, other drive loudPIN FUNCTIONS
PLCC
speaker piezo transducer 600nF. When loudspeaker section with maximum gain (+27dB) device provide internally programmable digital anticlipping system avoid output distortion. Programmable functions PIAFE include Ring/Tone generator which provides tones directed earpiece loudspeaker buzzer). simple ringer control interface bypass control sweep frequency ring ON/OFF phases. separate programmable gain amplifier allows gain control signal injected. Ring/Tone generator provides sinewave squarewave signal with precise frequencies which also directed input Transmit amplifier DTMF tone generation. auxiliary analog input (EAIN) also provided enable example output external band limited Ring signal Loudspeaker. Transmit signal back into receive ampifier with programmable attenuation provide sidetone circuitry. switchable anti-accoustic feed-back system cancels larsen effect speech monitoring application. additional pins provided insertion external Handfree function Loudspeaker receive path. output latch controlled register programming permits external device control.
Name
HFI,
Description
Hands free I/Os: These pins used insert external Handfree circuit such 7540 receive path. output which provides signal issued from output receive pass filter while high impendance input which connected directly inputs Loudspeaker amplifier. Receive analog earpiece amplifier complementary outputs, capable driving load impedances between piezo ceramic transducer 150nF. These outputs drive directly earpiece transductor. signal this output drive summ Receive Speech signal from Internal Tone Generator, Sidetone signal. Positive power supply input digital section. 10%. Receive analog loudspeaker amplifier complementary outputs, intended driving Loudspeaker: load impedance provided distorsion meeting specifications. Alternatively this stage drive piezo transducer 600nF. signal these outputs Receive Speech signal from Internal Tone generator, External input signal from EAIN input.
VFr+, VFr-
LS-,LS+
4/33
ST5088
FUNCTIONS (continued)
PLCC
Name
Description
Ground: digital signals referenced this pin. Mode Select: This input selects COMBO I/II interface mode with separate MICROWIRE Control interface when tied high mode when tied low. Transmit Data ouput: Data shifted this during assigned transmit time slots. Elsewhere output high impendance state. COMBO I/II mode, voice data byte shifted from TRISTATE output MCLK frequency rising edge MCLK. mode, voice data byte control bytes shifted from OPEN-DRAIN output half MCLK. external pull resistor needed. Alternate Tone: Ring frequency controlled without intervention. Tri-state logic controls: (Vcc), (GND), pause (High Impedance). Receive data input: Data shifted during assigned Received time slots. COMBO I/II mode, voice data byte shifted MCLK frequency falling edges MCLK. mode, data byte contol byte shifted half MCLK frequency receive rising edges MCLK. There period delay between transmit rising edge receive rising edge MCLK. Frame Sync input: This signal 8kHz clock which defines start transmit receive frames. Either three formats used this signal: delayed timing mode, delayed timing compatible timing mode. Master Clock Input: This signal used switched capacitor filters encoder/decoder sequencing logic. Values must kHz, 1.536 MHz, 2.048 2.56 selected means Control Register CRO. MCLK used also shift-in data. mode, 2.56 allowed. Open drain output: logic written into (CR1) appears logic logic written into puts high impedance. connected. Alternative positive high impedance input transmit preamplifier. Positive high impedance input transmit pre-amplifier microphone symetrical connection. Negative high impedance input transmit pre-amplifier microphone symetrical connection. Tape Recorder Output: This provides analog combination voice signal voice signal. Positive power supply input analog section. 10%. must directly connected together. Alternative negative high impedance input transmit preamplifier. Analog Ground: analog signals referenced this pin. GNDA must connected together close device. External Auxiliary input: This input used provide alternate signals Loudspeaker place Internal Ring generator. Input signal should voice band limited.
MCLK
MIC2+ MIC1+ MIC1TRO VCCA
MIC2GNDA
EAIN
5/33
ST5088
Following definitions used only when COMBO I/II mode with separate MICROWIRE compatible serial control port selected. input equal one) FUNCTIONS (continued)
PLCC
Name
Description
Control data Output: Serial control/status information shifted from PIAFE this when falling odges CCLK. Control data Input: Serial Control information shifted into PIAFE this when rising edges CCLK. Control Clock input: This clock shifts serial control information into from when input low, depending current instruction. CCLK asynchronous with other system clocks. Chip Select input: When this low, control information written into from PIAFE pins.
CCLK
Following definitions used only when mode selected. input equal zero) FUNCTIONS (continued)
19,13,12,20 PLCC 19,14,13,20
Name
A0,A1,A2,A3
Description
These pins select address PIAFE interface must hardwired either GND. A0,A1,A2,A3 refer C4,C5,C6,C7 bits first address byte respectively.
FUNCTIONAL DESCRIPTION Power initialization: When power first applied, power reset cicuitry initializes PIAFE puts into power down state. Gain Control Registers various programmable gain amplifiers programmable switches initialized indicated Control Register description section. CODEC functions disabled. Digital Interface configured mode COMBO I/II mode depending Mode Select connection. desired selection programmable functions intialized prior power command using Monitor channel mode MICROWIRE port COMBO I/II mode. Power up/down control: Following power-on initialization, power power down control accomplished writing control instructions listed Table into PIAFE with power power down. Normally, recommended that programmable functions initially programmed while device powered down. Power state control then included with last programming instruction separate single byte instruction. programmable registers also modified while ST5088 powered down setting indicated. When power down control entered single byte instruction, must
6/33
When power command given, de-activated circuits activated, output will remain high impedance state time slots until second pulse after power even channel selected. Power down state: Following period activity, power down state reentered writing power down instruction. Control Registers remain their current state changed either MICROWIRE control interface control channel depending mode selected. addition power down instruction, detection loss MCLK transition detected) automatically enters device "reset" power down state with output high impedance state high impedance state. Transmit section: Transmit analog interface designed stages enable gains realized. Stage noise differential amplifier providing gain. microphone capacitevely connected MIC1+, MIC1- inputs, while MIC2+ MIC2- inputs used capacitively connect second microphone (for digital handsfree operation) auxiliary audio circuit such 7540 Hands-free circuit. MIC1 MIC2 source selected with register CR4. Following first stage programmable gain
ST5088
amplifier which provides from additional gain step. total transmit gain should adjusted that, reference point Block Diagram description, internal dBmO voltage 0.739 (overload level 1.06 Vrms). Second stage amplifier programmed with bits CR5. temporarily mute transmit input, CR4) low. this case, analog transmit signal grounded sidetone path also disabled. active prefilter then precedes order band pass switched capacitor filter. converter compressing characteristic according CCITT mu255 coding laws, which must selected setting bits register CR0. precision chip voltage reference ensures accurate highly stable transmission levels. offset voltage arising gain-set amplifier, filters comparator cancelled internal autozero circuit. Each encode cycle begins immediatly beginning selected Transmit time slot. total signal delay referenced start time slot approximatively (due transmit filter) plus (due encoding delay), which totals Voice data shifted during selected time slot transmit rising adges MCLK. Receive section: Voice Data shifted into decoder's Receive voice data Register during selected time slot receive edges MCLK. decoder consists expanding with either MU255 decoding characteristic which selected same control instruction used select Encode during intitialization. Following Decoder 3400 order pass switched capacitor filter with integral correction sample hold. dBmO voltage this reference point (see Block Diagram description) 0.49 Vrms. transcient suppressing circuitry ensure interference noise suppression power analog speech signal output routed either earpiece (VFR+, VFR- outputs) loudspeaker (LS+, outputs) setting bits CR4). Total signal delay approximatively (filter plus decoding delay) plus 62.5 (1/2 frame) which gives approximatively Differential outputs VFR+,VFR- intended directly drive earpiece. Preceding outputs programmable attenuation amplifier, which must writing bits register CR6. Attenuations range relative maximum level step programmed. input this programmable amplifier summ several signals which selected writing register CR4.: Receive speech signal which been decoded filtered, Internally generated tone signal, (Tone amplitude programmed with bits register CR7), Sidetone signal, amplitude which programmed with bits register VFR+ VFR- outputsare capable driving output power level 14mW into differentially connected load impedance between Differential outputs LS+,LS- intended directly drive Loudspeaker. Preceding outputs programmable attenuation amplifier, which must writing bits register CR6. Attenuations range relative maximum level step programmed. input this programmable amplifier summ signals which selected writing register CR4: Receive speech signal which been decoded filtered, Internally generated tone signal, (Tone amplitude programmed with bits register CR7), EAIN input which alternate Ring signal voice frequency band limited signal. external decoupling capacitor about 0.1µF necessary). Receive voice signal directed output means Register CR4. After processing, signal must re-entered through input Loudspeaker amplifier input. external decoupling capacitor about 0.1µF necessary). output loudspeaker section switchable gains +9dB +27dB. +9dB Gain This gain mode fully equivalent PIAFE ST5080 behaviour. outputs capable driving output power level into differentially connected load impedance distortion meeting channel specifications. When signal source Ring squarewave signal, power levels approximatively delivered. +27dB Gain Additional gain 18dB purpose increase undistorted output power 150mW typical with digital input ranging from -12dBm0 +3dBm0. Output offset limited high pass filter with 35Hz frequency (with gain +9dB frequency 9Hz) Anti-acoustic feed-back loudspeaker handset microphone loop with squelch effect: chip
7/33
ST5088
switchable anti-larsen loudspeaker handset microphone feedback implemented. 12dB depth gain control both transmit receive path provided keep constant loop gain. transmit path 12dB gain control provided starting from transmit gain definition; same time, receive path 12dB gain control provided starting from receive gain definition. DIGITAL ANTICLIPPING SYSTEM (D.A.S.) automatic anticlipping system necessary avoid distortion LS+/LS- when output swing approaches supply rails. GAIN +9dB). digital anticlipping system calculates equivalent input signal compares with selectable anticlipping threshold. D.A.S. then able reduce overall gain order avoid limit distortion. Four different thresholds programmable register:
-15dBm0 -13dBm0 -9dBm0 -7dBm0 safe margin normal operation noisy ambient very noisy ambient
croprocessor. Digital Control Interface: PIAFE provides choice either types Digital Interface both control data PCM. compatibility with systems which time slot oriented busses with separate Control Interface, used COMBO I/II families devices, PIAFE functions described next section. Alternatively, systems which control data multiplexed together using interface scheme, PIAFE functions described section following next one. PIAFE will automatically switch these types interface sensing pin. Line Transceiver clock recovery circuitry, jitter provided MCLK clocks. MCLK must always phase. ST5421S Transceiver, example, maximun value jitter amplitude step each frame (125µs). maximum jitter amplitude pk-pk. COMBO I/II mode. Digital Interface (Fig. Frame Sync input determines beginning frame. have duration from single cycle MCLK squarewave. different relationships established between Frame Sync input first time slot frame setting register CR0. delayed data mode similar long frame timing ETC5057/ TS5070 series devices (COMBO COMBO respectively): first time slot begins nominally coincident with rising edge Alternative delayed data mode, which similar short frame sync timing COMBO COMBO which input must high least half cycle MCLK earlier frame beginning. time slot assignment circuit chip used with both timing modes, allowing connection voice data channels. data formats available: Format time slot corresponds MCLK cycles following immediately rising edge while time slot corresponds MCLK cycles following immediately time slot Format time slot identical Format Time slot appears slots after time slot This bits space left available insertion channel data. Data format selected register CR0. Time slot selected Control Register CR1. control register enables disables voice data transfer appropriate. During assigned time slot,
When environment noisy, power output might more important than distortion. Gain reduction D.A.S. (Anticlipping Attack) fixed speed 8KHz. Gain recovery increase (Anticlipping Release) programmable speeds 4Hz, 8Hz, 31Hz 62Hz. TAPE RECORDER OUTPUT (TRO) This section provides combination Analog Signals external user like recordering machine. output levels relative signal 0dBm0 channel are: 0.245VRMS (for 0dBm0 0.246VRMS (for 0dBm0 single ended able drive external load 600. ALTERNATE TONE CONTROL (AT) This section allows simplify microprocessor control ringer operation. When externally high impedance state left open) control ring frequency emission totally through microprocessor, which updates real time contents various registers. When forced ring generator emits respectively frequencies (GND) (Vcc), previously defined through registers (f2) CR8(f1). This operative mode requires only start-up intervention mi8/33
ST5088
Figure Digital Interface Format
Figure Interface Frame Structure
output shifts data from voice data register rising edges MCLK. Serial voice data shifted into input during same time slot falling edges MCLK. high impedance Tristate condition when selected time slots. Control Interface: Control information data written into readback from PIAFE serial control port consisting control clock CCLK, serial data input output Chip Select input, CS-. control instructions require bytes listed
with exception single byte powerup/down command. shift control data into ST5088, CCLK must pulsed high times while low. Data input shifted into serial input register rising edge each CCLK pulse. After data shifted content input shift register decoded, indicate that byte control data will follow. This second byte either defined second byte-wide CSpulse follow first contiguously, i.e. mandatory return high between first second control bytes.
9/33
ST5088
control byte, data loaded into appropriate programmable register. must return high byte. read-back status information from PIAFE, first byte appropriate instruction strobed during first pulse, defined Table must further CCLK cycles, during which data shifted falling edges CCLK. When high, high impedance Tri-state, enabling pins several devices multiplexed together. Thus, summarise, byte READ WRITE instructions either 8-bit wide CSpulses single wide pulse. Control channel access interface: possible access channel previously selected Register CR1. byte written into Control Register will automatically transmitted from output following frame place transmit data. byte written into Control Register will automatically sent through receive path Receive amplifiers. order implement continuous data flow from Control MICROWIRE interface channel, necessary send control byte each frame. current byte received input read register CR2. order implement continuous data flow from channel MICROWIRE interface, necessary read register each frame. COMPATIBLE MODE interface European standardized interface connect ISDN dedicated components different configurations equipment Terminals, Network Terminations, PBX, etc. Terminal equipment, this interface called SCIT Special Circuit Interface Terminals allows example connection between: ST5421 (SID-GCI) ST5451 (HDLC/GCI controller) used kbit/s channel packet frames processing control, Peripheral devices connected kbit/s channel ST5451 used peripheral control. ST5088 assigned channels present interface monitored control channel which multiplexed with kbit/s Voice Data channels. Figure shows frame structure interface. kbit/s channel supported. a)GCI channel structured four subchannels: channel bits frame
10/33
channel bits frame channel bits frame ignored PIAFE channel bits frame ignored PIAFE Only channel selected PIAFE data transfer. b)GCI channel structured also four subchannels: channel bits frame channel bits frame channel bits frame which structured follows: bits ignored PIAFE associated with channel associated with channel. channel selected PIAFE data transfer. channel associated bits used PIAFE control. Thus, summarize, channel selected transmit data channel used read/write status/command peripheral device registers. Protocol byte exchange channel uses bits. Physical Interface interface physically constitued with wires: Input Data wire: Output Data wire: Clock: MCLK Frame Synchronization: Data synchronized MCLK clock inputs. insures reinitialization time slot counter each frame beginning. rising edge reference time first channel bit. Data transmitted both directions half MCLK input frequency. Data transmitted rising edge MCLK sampled period after transmit rising edge, also rising edge. Note: Transmit data sampled far-end device ST5421 falling edge period after transmit rising edge. Unused channel high impedance. Data outputs OPEN-DRAIN need external pull resistor. COMBO activation/deactivation ST5088 automatically power down mode when clocks idle. section reactivated when clocks detected. PIAFE completly reactivated after receiving power command. Exchange protocol channel
ST5088
Protocol allows bidirectional transfer bytes between ST5088 controller with acknowledgment each received byte. PIAFE, standard protocol simplified provide read write register cycles almost identical MICROWIRE serial interface. Write cycle Control Unit sends through controller following bytes: First byte chip select byte. first four bits indicate device address: (A3,A2,A1,A0). four last bits ignored. ST5088 compare validated byte received internally with address defined pins comparison true, byte acknowledged, not, ST5088 does acknowledge byte. NOTE: internal "message progress" flag remains active till complete message transmission avoid irrelevant acknowledgement further byte. Second byte structured defined Table Third byte Data byte write into Register indicated Table possible optional write several different registers single message. this case Chip Select byte sent only once beginning message, device automatically toggles between address byte data byte. Read cycle Control Unit sends bytes. First byte chip select byte defined above. Second byte structured defined Table PIAFE identifies read-back cycle, byte Table equal respond Control Unit sending single byte message which content addressed register. possible optional request several different read-back register cycles single message recommended wait answer before requesting read back avoid loss data. ST5088 responds sending single data byte message each request. Received byte validation: received byte validated detected consecutive times identical. Exchange Protocol: Exchange protocol identical both directions. Sender uses indicate that sending byte while receiver uses acknowledge received byte. When message transferred, forced inactive state. transmission initialized sender putting from inactive state active state sending first byte channel same frame. Transmission message allowed only from receiver been inactive least frames. When receiver ready, validates received byte internally when received consecutive frames identical. Then receiver sets first from inactive active state (pre-acknowlegement), maintains active least following frame (acknowledgement). validation possible, (two last bytes received identical), receiver aborts message setting active only single frame. first byte received, Abort sequence allowed. PIAFE does respond either last bytes identical byte received does meet Chip Select byte defined A0-A3 pins bias. second byte transmitted sender putting from active inactive state sending second byte channel same frame. inactive only frame. remains inactive more than frame, message (i.e. second byte available). second byte transmitted only after receiving pre-acknowledgment previous byte transmitted (see Fig. same protocol used third byte transmitted. Each byte transmitted least consecutive frames. receiver validates current received byte done first byte then next frames first from active inactive state (preacknowledgement), after from inactive active state (acknowledgement). receiver cannot validate received current byte (two bytes received identical), pre-acknowledges normally, inactive state next frame which indicates abort request. message sent ST5088 aborted, will stop message wait read cycle instruction from controller. message received ST5088 acknowledged aborted without flow Control. Figures gives timing write cycle. Most significant (MSB) Monitor byte sent first channel. bits active inactive state DOUT high impedance. PROGRAMMABLE FUNCTIONS
11/33
ST5088
Figure bits Timing
12/33
ST5088
both formats Digital Interface, programmable functions configured writing number registers using 2-byte write cycle (not including chip select byte GCI). Most these registers also read-back verification. Byte always register address, while byte Data. Table lists register their respective adresses.
Table Programmable Register Intructions
Function Single byte Power up/down Write Read-back Write Read-back Write Data receive path Read data from Write Data Write Read-back Write Read-back Write Read-back Write Read-back Write Read-back Write Read-back Write Read-back CR10 Address byte none TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE CR10 TABLE CR10 Data byte
NOTE
address byte data byte always first clocked into from: pins when MICROWIRE serial port enabled, into from pins when mode selected. reserved: write Power up/down Control bit. Means Power Down. indicates, set, presence second byte. write/read select bit.
NOTE NOTE
13/33
ST5088
Table Control Register Functions
MCLK MCLK MCLK MCLK 1.536 2.048 2.560 Function
MU-law; CCITT D3-D4 MU-law; Bare Coding A-law including even inversion A-law; Bare Coding Delayed data timing delayed data timing consecutive separated bits time-slot bits time-slot Normal operation Digital Loop-back
(1):
state power initialization significant COMBO I/II mode only
Table Control Register Functions
pins disabled pins enabled Anti-larsen disabled Anti-larsen enabled latch high impedance latch connected rec. path connected rec. path Trans path connected connected voice data transfer disable voice data transfer enable channel selected channel selected channel selected channel selected Function
(1): (2):
state power initialization significant COMBO mode only significant mode only.
14/33
ST5088
Table Control Register Functions
Function Data sent Receive path Data received from input
Table Control Registers Functions
data transmitted Function
Table Control Register Functions
MIC1 selected MIC2 selected Transmit input muted Transmit input enabled Internal sidetone disabled Internal sidetone enabled EAIN disconnected EAIN selected Loudspeaker Ring Ring Ring Ring Tone muted Tone Earpiece Tone Loudspeaker Tone Earpiece Loudspeaker Function
Receive signal muted Receive signal connected earpiece amplifer Receive signal connected loudspeaker amplifier Receive signal connected loudspeaker earpiece amplifier
state power initialization
15/33
ST5088
Table Control Register Functions
state power initialization
gain gain step gain
Transmit amplifier
Sidetone amplifier
Function
gain gain step gain
Table Control Register Functions
state power initialization
gain gain step gain
Earpiece ampifier
Loudspeaker
Function
gain gain step gain
Table Control Register Functions
(1): state power initialization value provided selected alone. selected summed mode, f1=1.34 while f2=1.06 Vpp. Output generator reserved: write
Attenuation muted selected selected summed mode Squarewave signal selected Sinewave signal selected
Function .2.4 1.70 1.20 0.85 0.60 0.43 0.30 0.21 0.15 0.10 .1.9 1.34 0.95 0.67 0.47 0.34 0.24 0.17 0.12 0.08
Tone gain
Normal operation Tone Ring Generator connected toTransmit path
16/33
ST5088
Table Control Register Functions
Function Binary equivalent decimal number used calculate
Table Control Register Functions
Function Binary equivalent decimal number used calculate
Table Control Register CR10 Functions
Default values inserted into Register Power
into Path +9dB into Path Anticlipping Anticlipping
Function
-15dm0 Anticlipping Threshold -13dm0 Anticlipping Threshold -9dm0 Anticlipping Threshold -7dm0 Anticlipping Threshold 256ms Gain Recovery Time Constant (4Hz) 128ms Gain recovery Time Constant (8Hz) 32ms Gain Recovery Time Constant (31Hz) 16ms Gain Recovery Time Constant (62Hz) Standard Frequency Tone Range Halved Frequency Tone Range Doubled Frequency Tone Range Forbidden
17/33
ST5088
CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Master Clock Frequency Selection master clock must provided PIAFE operation filter coding/decodingfunctions. COMBO I/II mode, MCLK frequency either kHz, 1.536 MHz, 2.048 2.56 MHz. must during initialization select correct internal divider. mode, MCLK must either 1.536MHz 2.048MHz. 512KHz 2.56MHz allowed. Default value 1.536 both modes. clock different from default must selected prior Power-Up instruction both modes. Coding Selection Bits permit selection Mu-255 coding with without even inversion. After power initialization, Mu-255 selected.
full scale full scale
True even inversion
without even inversion
always first shifted PIAFE.
Digital Interface timing DN=0 selects digital interface delayed timing mode while DN=1 selects delayed data timing. mode, significant. After reset COMBO I/II mode selected, delayed data timing selected. Digital Interface format FF=0 selects digital interface Format where channel consecutive. FF=1 selects Format where channel separated bits. (see digital interface format section). mode, significant. 56+8 selection 'B7' selects capability PIAFE take into account only seven most significant bits data byte selected. When 'B7' set, ignored high impedance. This function allows connection external band" data generator directly connected Digital Interface. Digital loopback Digital loopback mode entered setting bit(0) equal Digital Loopback mode, data written into Receive Data Register from selected received time-slot read-back from that Register
18/33
selected transmit time-slot Time slot selected with Register CR1. decoding encoding takes place this mode. Transmit Receive amplifier stages muted. CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Hands-free I/Os selection enables HFI, pins connection external handfree circuit such 7540. analog output that provides receive voice signal. dBMO level that output 0.491 Vrms (1.4Vpp). analog high impedance input typ.) intended send back processed receive signal Loudspeaker. dBMO level that input 0.491Vrms. Anti-larsen selection enables on-chip antilarsen squelch effect system. Latch output control controls directly logical status latch output "ZERO" written puts output high impedance, "ONE" written sets output zero.
ST5088
Microwire access channel receive path selects access from MICROWIRE Register Receive path. When high, data written register decoded each frame, sent receive path data input ignored. other direction, current data input received read from register each frame. Microwire access channel transmit path selects access from MICROWIRE write only Register output. When high, data written output every frame output encoder ignored. channel selection 'EN' enables disables voice data transfer pins. When disabled, data from decoded time-slots high impedance mode, bits 'T1' 'T0' select four channels interface. COMBO I/II mode, only channel selected according interface format selected. 'T1' ignored. CONTROL REGISTER Data sent receive path data received from input. Refer MR(4) "Control Register CR1" paragraph. CONTROL REGISTER data transmitted. Refer MX(3) "Control Rgister CR1" paragraph. CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Transmit Input Selection MIC1 MIC2 source selected with (7). Transmit input selected enabled muted with (6). Transmit gain adjusted within range step with Register CR5. Sidetone select "SI" enables disables Sidetone circuitry. When enabled, sidetone gain adjusted with Register (CR5). When Transmit path disabled, low, sidetone circuit also disabled. External Auxiliary signal select "EE" connects EAIN input loudspeaker amplifier input. Ring/Tone signal routing Bits "RTL" provide select capability connect on-chip Ring/Tone generator either loudspeaker amplifier input earpiece amplifier input both. receive data routing Bits "SL" "SE" provide select capability connect received speech signal either Loudspeaker amplifier input earpiece amplifier input both. CONTROL REGISTER First byte READ WRITE instuction Control Register shown TABLE Second byte shown TABLE Transmit gain selection Transmit amplifier programmed gain from 15dB step with bits dBmO level output transmit amplifier reference point) 0.739 Vrms (overload voltage 1.06 Vrms). Sidetone attenuation selection Transmit signal picked after switched capacitor pass filter back into Receive Earpiece amplifier. Atten uation signa output sidetone attenuator programmed from -8dB -23dB relative reference point step with bits CONTROL REGISTER First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Earpiece amplifier gain selection: Earpiece Receive gain programmed step from relative maximum with bits dBmO voltage output amplifier pins VFr+ VFr- then 824.5 mVrms when gain selected down 146.6 mVrms when gain selected. Loudspeaker amplifier gain selection: Loudspeaker Receive amplifier gain programmed step from relative maximum with bits dBmO voltage output amplifier pins then 1.384 Vrms (3.91Vpp when gain selected down 43.7 mVrms (123.6mVpp) when gain selected.
19/33
ST5088
Current limitation approximatively mApk. CONTROL REGISTER CR7: First byte READ WRITE instruction Control Register shown TABLE Second byte shown TABLE Tone/Ring amplifier gain selection Output level Ring/Tone generator, before attenuation programmable attenuator Vpkpk when generator selected alone summed with generator Vpk-pk when generatoris selected alone. Selected output level attenuated down programmable attenutator setting bits Frequency mode selection Bits 'F1' 'F2' permit selection and/or frequency generator according TABLE When selected, output Ring/Tone squarewave sinewave) signal frequency selected CR9) Register. When selected summed mode, output Ring/Tone generator signal where frequency summed. order meet DTMF specifications, output level attenuated relative output level. Frequency temporization must controlled microcontroller. switching between frequencies same channel done maintaining practically phase continuity. actual change frequency tone generator takes place within 1/16th period highest frequencies that switched between, plus internal data acquisition. Waveform selection 'SN' selects waveform output Ring/Tone generator. Sinewave squarewave signal selected. DTMF selection permits connection Ring/Tone/DTMF generator Transmit Data path instead Transmit Amplifier output. Earpiece feed-back provided sidetone circuitry setting directly setting Register CR4. Loudspeaker feed-back provided directly setting Register CR4. CONTROL REGISTERS First byte READ WRITE instruction
20/33
Control Register shown TABLE Second byte respectively shown TABLE Tone Ring signal frequency value defined formula: 0.128 0.128 (with CR10) where decimal equivalents binary values registers respectively. Thus, frequency between 1992 selected step. TABLE gives examples main frequencies usual Tone Ring generation. CONTROL REGISTER CR10 First byte READ WRITE instruction control register CR10 shown TABLE Second byte shown Table Extra +18dB Gain sets extra 18dB Gain (total Gain 27dB) sets standard Gain like ST5080 Anticlipping enable, thresholds time constants enables operation Digital anticlipping section (D.A.S.), needed avoid distortion sine wave when (extra 18dB anticlipping thresholds -15, -13, -7dBmo defined bits (VT1/VT0). Gain recovery constants (anticlipping release) selectable among four values, 256ms, 128ms, 32ms 16ms bits (FD1/FD0). Doubled Tone/Ringer Frequency Range Double frequency range tone ringer generator obtained putting (and Formula frequency generator CR8/0.064Hz CR9/0.064Hz. Maximum frequency 3984.4Hz frequency accuracy 15.6Hz. Halved Tone/Ringer Frequency Range Halved frequency double accuracy tone ringer generator obtained putting (and Formula frequency generator CR8/0.256Hz CR9/0.256Hz Frequency range from 3.9Hz 996.1Hz step 3.9Hz with improved accuracy frequencies combination. DFT= forbidden combination.
ST5088
Table Examples Usual Frequency Selection (DFT CR10)
Description Tone Tone Tone Tone Tone Tone 1330 value (decimal) Theoric value (Hz) 1330 1209 1336 1477 1633 523.25 587.33 622.25 659.25 698.5 830.6 987.8 1046.5 1174.66 1318.5 Typical value (Hz) 328.2 421.9 437.5 796.9 1328.1 695.3 773.4 851.6 937.5 1210.9 1335.9 1476.6 1632.8 390.6 437.5 492.2 523.5 586.0 625.0 656.3 695.3 742.2 781.3 828.2 882.9 984.4 1046.9 1171.9 1320.4 Error -.56 -.73 -.56 -.39 -.14 -.24 +.44 -.05 -.37 +.16 -.01 -.30 -.56 -.34 +.04 -.23 +.45 -.45 -.45 +.30 -.34 -.29 +.33 -.34 +.04 -.23 +.14
DTMF DTMF DTMF DTMF DTMF 1209 DTMF 1336 DTMF 1477 DTMF 1633 flat sharp sharp
POWER SUPPLIES While pins PIAFE device well protected against electrical misuse, recommended that standard CMOS practise applying before other connections made should always followed. applications where printed circuit card plugged into socket with power clocks already present, extra long ground connector should
used. minimize noise sources, ground connections each device should meet common point close possible order prevent interaction ground return currents flowing through common impedance. power supply decoupling capacitor should connected from this common point close possible device pins.
21/33
ST5088
TIMING DIAGRAM Delayed Data Timing Mode
Delayed Data Timing Mode
22/33
ST5088
TIMING DIAGRAM (continued) Timing Mode
Serial Control Timing (MICROWIRE MODE)
23/33
ST5088
ABSOLUTE MAXIMUM RATINGS
Parameter Current VMIC (VCC 5.5V) Current VRxO Voltage digital input (VCC 5.5V); limited ±50mA Current digital output Storage temperature range Lead Temperature (wave soldering, 10s) Value Unit
TIMING SPECIFICATIONS (unless otherwise specified, 10%, -5°C 70°C typical characteristics specified signals referenced GND, Note timing definitions) MASTER CLOCK TIMING
Symbol fMCLK Parameter Frequency MCLK Test Condition Selection frequency programmable (see table Min. Typ. 1.536 2.048 2.560 Max. Unit
tWMH tWML
Period MCLK high Period MCLK Rise Time MCLK Fall Time MCLK
Measured from Measured from Measured from Measured from
INTERFACE TIMING (COMBO modes)
Symbol tHMF tSFM tDMD tDMZ tDFD Parameter Hold Time MCLK Setup Time, high MCLK Delay Time, MCLK high data valid Delay Time, MCLK disabled Delay Time, high data valid Load Applies only rises later than MCLK rising edge Delayed Mode only Load Test Condition Min. Typ. Max. Unit
tSDM tHMD
Setup Time, valid MCLK receive edge Hold Time, MCLK invalid
24/33
ST5088
SERIAL CONTROL PORT TIMING (Usual COMBO mode only)
Symbol fCCLK tWCH tWCL tHCS tSSC tSDC tHCD tDCD tDSD tDDZ Parameter Frequency CCLK Period CCLK high Period CCLK Rise Time CCLK Fall Time CCLK Hold Time, CCLK high Setup Time, CCLK high Setup Time, valid CCLK high Hold Time, CCLK high invalid Delay Time, CCLK data valid Delay Time, CS-low data valid Delay Time CS-high CCLK high impedance whichever comes first Hold Time, CCLK high high Time, high CCLK high
signal valid above below invalid between VIH. purpoes this specification following conditions apply: input signal defined 0.4V, 2.7V, 10ns, 10ns. Delay times measured from inputs signal valid output signal valid. Setup times measured from data input valid clock input invalid. Hold times measured from clock signal valid data input invalid.
Test Condition Measured from Measured from Measured from Measured from
Min.
Typ.
Max. 2.048
Unit
Load plus LSTTL load
tHSC tSCS
Note
ELECTRICAL CHARACTERISTICS (unless otherwise specified, 10%, -5°C 70°C typical characteristic specified 25°C signals referenced GND) DIGITAL INTERFACES
Symbol Parameter Input Voltage Input High Voltage Input Voltage Input High Voltage Output Voltage Test Condition digital inputs except digital inputs except Input Input X,IL -2.0mA; other digital outputs, -1mA X,IL 2.0mA; other digital outputs, -0.5V Min. Typ. Max. Unit 25/33
Output High Voltage
Input Current Input High Current Output Current High impedance (Tri-state)
digital input, digital input,
ST5088
ANALOG INTERFACES
Symbol IMIC RMIC RLVFr CLVFr OVFr0 VOSVFr0 Parameter Input Leakage Input Resistance Load Resistance Load Capacitance Output Resistance Differential offset: Voltage VFr+, VFrLoad Resistance Load Capacitance Output Resistance Differential offset Voltage LS+, LSLoad Resistance Test Condition VMIC VMIC VFr+ VFrVFr+ VFrSteady zero code applied Alternating zero code applied maximum receive gain; LSLS+ LSSteady zero code applied Alternating zero code applied maximum receive gain; -100 +100 -100 +100 Min. -100 Typ. Max. +100 Unit
RLLS CLLS VOSLS
LTRO
POWER DISSIPATION
Symbol ICC0 Parameter Power down Current Test Condition CCLK,CI 0.4V; 2.4V (µwire only) other inputs active mode only: LS+, VFr+, VFr- loaded Min. Typ. 12.0 Max. 17.0 Unit
ICC1
Power Current
TRANSMISSION CHARACTERISTICS (unless otherwise specified, 10%, -5°C 70°C; typical characteristics specified 25°C, MIC1/2 0dBm0, 0dBm0 code, 1015.625 signal referenced GND) AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Transmit path Absolute levels MIC1 MIC2
Parameter dBM0 level Overload level Overload level dBM0 level Overload level Overload level Test Condition Transmit Amps connected gain selected selected Transmit Amps connected 15dB gain selected selected Min. Typ. 73.9 106.08 106.47 13.14 18.86 18.93 Max. Unit mVRMS mVRMS mVRMS mVRMS mVRMS mVRMS
26/33
ST5088
TRANSMISSION CHARACTERISTICS (continued) AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Receive path Absolute levels (Differentially measured)
Parameter dBM0 level dBM0 level Test Condition Receive programmed gain Receive programmed 15dB attenuation Min. Typ. 824.5 146.6 Max. Unit mVRMS mVRMS
AMPLITUDE RESPONSE (Maximum, Nominal, Minimum Levels) Receive path Absolute levels (Differentially measured)
Parameter dBM0 level dBM0 level Test Condition Receive programmed gain Receive programmed 30dB gain Min. Typ. 1.384 43.7 Max. Unit VRMS mVRMS
AMPLITUDE RESPONSE Transmit path
Symbol Parameter Transmit Gain Absolute Accuracy Test Condition Transmit Gain Programmed maximum. Measure deviation Digital Code from ideal 0dBm0 code Measure Transmit Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GXA, i.e. GAXG actual prog. Measured relative GXA. min. gain Max. gain Measured relative Maximum gain Relative 1015,625 multitone test technique used. min. gain Max. gain GXAL Transmit Gain Variation with signal level 3000 3400 4000 4600 5000 5000 -1.5 -0.3 -0.8 -0.1 Min. -0.30 Typ. Max. 0.30 Unit
GXAG
Transmit Gain Variation with programmed gain
-0.5
GXAT GXAV GXAF
Transmit Gain Variation with temperature Transmit Gain Variation with supply Transmit Gain Variation with frequency
-0.1 -0.1
Sinusoidal Test method. Reference Level dBm0 VMIC dBm0 VMIC VMIC
-0.25 -0.5 -1.5
0.25
27/33
ST5088
AMPLITUDE RESPONSE Receive path
Symbol GRAE Parameter Receive Gain Absolute Accuracy Test Condition Receive gain programmed maximum Apply dBm0 code Measure VFr+ Receive gain programmed maximum Apply dBm0 code Measure Measure Earpiece Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GRAE, i.e. GRAGE actual prog. GRAE Measure Loudspeaker Gain over range from Maximum minimum setting. Calculate deviation from programmed gain relative GRAL, i.e. GRAGL actual prog. GRAL Measured relative GRA. VFr) Maximum Gain Measured relative GRA. VFr) Maximum Gain Relative 1015,625 multitone test technique used. min. gain Max. gain GRAL Receive Gain Variation with signal level (Earpiece) 3000 3400 4000 -0.3 -0.3 -0.8 Min. -0.3 Typ. Max. Unit
GRAL
Receive Gain Absolute Accuracy
-0.6
GRAGE
Receive Gain Variation with programmed gain
-0.5
GRAGL
Receive Gain Variation with programmed gain
-1.0
GRAT
Receive Gain Variation with temperature Receive Gain Variation with Supply Receive Gain Variation with frequency (Earpiece Loudspeaker)
-0.1
GRAV
-0.1
GRAF
Sinusoidal Test Method Reference Level dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 Sinusoidal Test Method Reference Level dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0 dBm0
-0.25 -0.25 -0.5 -1.5
0.25 0.25
GRAL
Receive Gain Variation with signal level (Loudspeaker)
-0.25 -0.25 -0,5 -1.5
0.25 0.25
28/33
ST5088
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol Parameter Delay, Absolute Delay, Relative Test Condition 1000 1000 1000 1600 1600 2600 2600 2800 2800 3000 1000 1000 1600 1600 2600 2600 2800 2800 3000 Min. Typ. Max. Unit
Delay, Absolute Delay, Relative
1600
NOISE
Symbol NREC Parameter Noise, weighted Noise, weighted Noise, weighted (Earpiece) Noise, weighted (Earpiece) Noise, weighted (Loudspeaker) Noise, weighted (Loudspeaker) Noise, Single Frequency Test Condition VMIC Max. Gain VMIC Max. Gain Receive code Alternating Positive Negative code Max. Gain Receive code Positive Zero Max. Gain Receive code Alternating Positive Negative code Max. Gain Receive code Positive Zero Max. Gain VMIC Loop-around measurament from VMIC Receive code Positive Zero VMIC mVrms; 50KHz Code equals Positive Zero, mVrms, measure input dBm0 code 3400 Input Code applied 4600 5600 5600 7600 7600 8400 8400 Min. Typ. Max. Unit dBrnC0 dBm0p dBrnC0
NREP NRLC
dBm0p dBrnC0
NRLP
dBm0p dBm0
NTRO PPSRx
Recorder Noise, Pweighted Positive PSRR,
dBmp
PPSRp
Positive PSRR,
Spurious Out-Band signal output
29/33
ST5088
DISTORTION
Symbol STDx STDr Parameter Signal Total Distortion Test Condition Sinusoidal Test Methode (measured using message weighting Filter) Level dBm0 dBm0 Level dBm0 Level dBm0 dBm0 input signal dBm0 input signal Loop-around measurament Voltage VMIC dBm0 dBm0, Frequencies range 3400 Min. Typ. Max. Unit
SDFx SDFr
Single Frequency Distortion transmit Single Frequency Distortion receive Intermodulation
CROSSTALK
Symbol Tx-r Parameter Transmit Receive Test Condition Transmit Level dBm0, 3400 QuietPCM Code Receive Level dBm0, 3400 VMIC Min. Typ. Max. Unit
Tr-x
Receive Transmit
TAPE RECORDER
Symbol GTRO GTRO Parameter Receive Output Transmit Output Test Condition 0dBm0 0dBm0 Min. Typ. Max. Unit mVRMS mVRMS
APPLICATION NOTE MICROPHONE CONNECTIONS
connection modes (since MIXED MODE symmetrical with respect MIC1 MIC2) allow microphone time selected (bit Control Register CR4).
30/33
ST5088
PLCC28 PACKAGE MECHANICAL DATA
DIM. MIN. 1.24 1.143 12.32 11.43 2.29 0.51 9.91 1.27 7.62 0.46 0.71 0.101 0.049 0.045 10.92 TYP. MAX. 12.57 11.58 4.57 3.04 MIN. 0.485 0.450 0.165 0.090 0.020 0.390 0.050 0.300 0.018 0.028 0.004 0.430 inch TYP. MAX. 0.495 0.456 0.180 0.120
31/33
ST5088
SO28 PACKAGE MECHANICAL DATA
DIM. MIN. 17.7 1.27 16.51 1.27 (max.) 0.291 0.016 18.1 10.65 0.35 0.23 (typ.) 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 TYP. MAX. 2.65 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
32/33
ST5088
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics Rights Reserved SGS-THOMSON Microelectronics GROUP COMPANIES Australia Brazil France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thaliand United Kingdom U.S.A.
33/33

PIAFE PROGRAMMABLE ISDN AUDIO FRONT FEATURES: Complete CODEC FILT

Top Searches for this datasheet

Other recent searches