Lithium-Ion Battery Charger ADP3820 FUNCTIONAL BLOCK DIAGRAM

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Lithium-Ion Battery Charger ADP3820 FUNCTIONAL BLOCK DIAGRAM

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FEATURES Total Accuracy Typical Quiescent Current Shutdown Current: (Typical) Stable with Load Capacitor Input Operating Range Integrated Reverse Leakage Protection 6-Lead SOT-23-6 8-Lead SO-8 Packages Programmable Charge Current Ambient Temperature Range Internal Gate-to-Source Protective Clamp APPLICATIONS Li-Ion Battery Chargers Desktop Computers Hand-Held Instruments Cellular Telephones Battery Operated Devices
Lithium-Ion Battery Charger ADP3820
FUNCTIONAL BLOCK DIAGRAM
BIAS
50mV
VREF GATE VOUT
ADP3820
GENERAL DESCRIPTION
ADP3820 precision single cell Li-Ion battery charge controller that used with external Power PMOS device form two-chip, cost, dropout linear battery charger. available voltage options accommodate Li-Ion batteries with coke graphite anodes. ADP3820's high accuracy shutdown current easy charge current programming make this device especially attractive battery charge controller. Charge current external resistor. example, resistance used charge current Additional features this device include foldback current limit, overload recovery, gate-to-source voltage clamp protect external MOSFET. proprietary circuit also minimizes reverse leakage current from battery input voltage charger disconnected. This feature eliminates need external serial blocking diode. ADP3820 operates with wide input voltage range from specified over industrial temperature range -20°C +85°C available ultrasmall 6-lead surface mount SOT-23-6 8-lead SOIC packages.
NDP6020P
VOUT Li-Ion BATTERY
GATE VOUT
ADP3820-xx
Figure Li-Ion Charger Application Circuit
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
ADP3820-SPECIFICATIONS1(V
Parameter INPUT VOLTAGE OUTPUT VOLTAGE ACCURACY QUIESCENT CURRENT Shutdown Mode Normal Mode GATE SOURCE CLAMP VOLTAGE GATE DRIVE MINIMUM VOLTAGE
[VOUT unless otherwise noted)
Symbol Units
Conditions
VOUT
VOUT
IGND IGND
GATE DRIVE CURRENT (SINK/SOURCE) GAIN CURRENT LIMIT THRESHOLD VOLTAGE LOAD REGULATION LINE REGULATION IOUT Circuit Figure VOUT IOUT Circuit Figure Battery) Floating IDISCH
INPUT VOLTAGE INPUT CURRENT OUTPUT REVERSE LEAKAGE CURRENT
NOTES limits temperature extremes guaranteed correlation using standard Statistical Quality Control (SQC). Provided gate-to-source clamp voltage exceeded. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Input Voltage, Enable Input Voltage (VIN Operating Ambient Temperature Range -20°C +85°C Storage Temperature Range -65°C +150°C SO-8 Package 150°C/W SOT-23-6 Package 230°C/W Lead Temperature (Soldering, sec) +300°C Vapor Phase sec) .+215°C Infrared sec) .+220°C Rating
*This stress rating only; operation beyond these limits cause device permanently damaged.
Model ADP3820ART-4.1 ADP3820ART-4.2 ADP3820AR-4.1 ADP3820AR-4.2
Voltage Output
Package Option*
Marking Code
RT-6 (SOT-23-6) RT-6 (SOT-23-6) SO-8 SO-8
*SOT Surface Mount Package. Small Outline. Contact factory availability other output voltage options.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADP3820 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
ADP3820
FUNCTION DESCRIPTIONS CONFIGURATIONS SO-8 RT-6 (SOT-23-6)
SOT-23-6 SO-8
Name
Function Shutdown. Pulling this will disable output. Device Ground. This should tied system ground closest load. Output Voltage Sense. This connected MOSFET's drain directly load optimal load regulation. Bypass ground with larger capacitor. Gate drive external MOSFET. Input Voltage. This also positive terminal connection current sense resistor. Current Sense. Used sense input current monitoring voltage across current sense resistor. connected more negative terminal resistor well power MOSFET's source pin. should tied current limit feature used. Connect.
ADP3820
VIEW GATE (Not Scale)
VIEW VOUT (Not Scale) GATE
ADP3820
VOUT
CONNECT
VOUT
GATE
REV.
ADP3820 -Typical Performance Characteristics
4.110 5.1V 0.740 OUTPUT VOLTAGE 4.105 0.760 LOAD 10mA
0.720
IGND
0.700 0.680
4.100
0.660 4.095 0.640
4.090
ILOAD
1000
0.620
INPUT VOLTAGE
Figure ILOAD (VIN
Figure IGND LOAD mA)*
4.110 LOAD
0.900 ILOAD
OUTPUT VOLTAGE
4.105
0.850
4.100
IGND
0.800
4.095
0.750
4.090
0.700
INPUT VOLTAGE
INPUT VOLTAGE
Figure VOUT (ILOAD
Figure IGND LOAD
4.110 LOAD 10mA
1.200 5.1V 1.100
OUTPUT VOLTAGE
4.105
1.000 IGND 0.900 0.800 0.700 0.600
4.100
4.095
4.090
0.500 0.001
ILOAD
1000
INPUT VOLTAGE
Figure VOUT LOAD mA)*
Figure ILOAD (VIN
*Reference Figure
REV.
ADP3820
1.100 5.1V LOAD 10mA 1.000 4.190 0.900
OUTPUT VOLTAGE
4.230 4.210 VOUT 4.2V
IGND
4.170 4.150 4.130 VOUT 4.1V 4.110
0.800
0.700
0.600 4.090 0.500 4.070
TEMPERATURE
TEMPERATURE
Figure Quiescent Current Temperature*
Figure VOUT Temperature, ILOAD
LOAD 10mA OUTPUT VOLTAGE PSRR INPUT VOLTAGE
-100 100k FREQUENCY CLOAD LOAD
Figure Power-Up/Power-Down*
Figure Ripple Rejection*
INPUT VOLTAGE
5.000 OUTPUT VOLTAGE 4.000 ILOAD 10mA COUT 5.1V
3.000
OUTPUT VOLTAGE
2.000
1.000 0.000
ILOAD
Figure Line Transient Response Output Cap)*
Figure Current Limit Foldback*
REV.
ADP3820
APPLICATION INFORMATION
ADP3820 very easy use. P-channel power MOSFET small capacitor output that needed form inexpensive Li-Ion battery charger. advantage using ADP3820 controller that directly drive PMOS provide regulated output current until battery charged. When specified battery voltage reached, charge current reduced ADP3820 maintains maximum specified battery voltage accurately. When fully charged, circuit Figure works like well known linear regulator, holding output voltage within specified accuracy needed single cell Li-Ion batteries. output sensed VOUT pin. When charging discharged battery, circuit maintains charging current determined current sense resistor until battery fully charged, then reduces trickle charge keep battery specified voltage. voltage drop across current sense resistor sensed input ADP3820. minimum battery voltage shorted battery, circuit reduces this current (foldback) limit dissipation (see Figure 13). Both input VOUT sense pins need bypassed suitable bypass capacitor. gate-to-source voltage clamp provided ADP3820 protect MOSFET gates higher source voltages. ADP3820 also input, which connected input voltage enable Pulling ground will disable FET-drive.
Design Approach
ADP3820. This factor between about 0.65. T/(IO 100/(1 0.65 30.7°C/W This thermal impedance realized using transistor shown Figure when surface mounted double-sided with many vias around surfacemounted backplane PCB. Alternatively, TO-220 packaged mounted heatsink could used. thermal impedance suitable heatsink calculated below: 30.7 +28.7°C/W Where junction-to-case thermal impedance read from data sheet. cost such heatsink type PF430 made Thermalloy, with +25.3°C/W. current sense resistor this application simply calculated: 0.05/1 Where specified data sheet current limit threshold voltage mV-75 battery charging applications, adequate typical midvalue. Nonpreregulated Input Voltage input voltage source example, rectified capacitor-filtered secondary voltage small wall plug-in transformer, heatsinking requirement more demanding. VINMIN should specified lowest line voltage full load current. required thermal impedance calculated same above, here have maximum output rectified voltage, which substantially higher than depending transformer regulation line voltage variation. example, VINMAX T/(IO VINMAX) 100/(1 0.65 +15.3°C/W suitable heatsink thermal impedance: 15.3 13.3°C/W cost heatsink Type 6030B made Thermalloy, with +12.5°C/W.
Lower Current Option Preregulated Input Voltage 10%)
lower efficiency Linear Regulator Charging, most important factor thermal design cost, which direct function input voltage, output current thermal impedance between MOSFET ambient cooling air. worse-case situation when battery shorted since MOSFET dissipate maximum power. tradeoff must made between charge current, cost thermal requirements charger. Higher current requires larger with more effective heat dissipation leading more expensive design. Lowering charge current reduces cost lowering size FET, possibly allowing smaller package such SOT-23-6. following designs consider both options. Furthermore, each design evaluated under input source voltage conditions. Regarding input voltage, there options: input voltage preregulated, e.g., input voltage preregulated source, e.g., wall plug-in transformer with rectifier capacitive filter.
Higher Current Option Preregulated Input Voltage 10%)
circuit shown Figure required thermal impedance calculated follows: data sheet allows junction temperature TJMAX 150°C, then 50°C ambient convection cooling, maximum allowed junction temperature rise thus, TJMAX TAMAX 150°C 50°C 100°C. maximum current shorted discharged battery reduced from charge current multiplier factor shown Figure foldback current limiting feature
lower charging current allowed, value increased, system cost decreased. lower cost assured using inexpensive MOSFET with, example, NDT452P SOT-23-6 package mounted small area double-sided PCB. This provides convection cooled thermal impedance +55°C/W, presuming many vias used around backplane. Allowing maximum junction temperature +150°C, +50°C ambient, convection cooling maximum allowed heat rise thus 150°C-50°C 100°C. maximum foldback current allowed: 100/(55 0.33 Thus full charging current: IOUTMAX IFB/k calculated above example.
REV.
ADP3820
current sense resistor this application: VS/IO 0.05/0.5
Selection Gate-to-Source Clamp
type size pass transistor determined threshold voltage, input-output voltage differential load current. selected PMOS must satisfy physical thermal design requirements. ensure that maximum provided controller will turn worst case conditions, (i.e., temperature manufacturing tolerances) maximum available must determined. Maximum calculated follows: IOUTMAX where IOUTMAX Maximum Output Current Current Sense Resistor (Room Temperature) (Hot) (Cold) example: IOUTMAX 4.25 logic level should considered. either logic level standard MOSFET used. difference between (VDS) must exceed voltage drop sense resistor plus ON-resistance maximum charge current. selected MOSFET must satisfy these criteria; otherwise, different pass device should used. maximum RDS(ON) required available gate drive (VDR) Drain-to-Source voltage (VDS) RDS(ON) VDS/IOUTMAX From Drain-to Source current Drain-to-Source voltage gate drive graph MOSFET data sheet, determined above calculated RDS(ON) higher than graph indicates. However, value read from MOSFET data sheet graph must adjusted based junction temperature MOSFET. This adjustment factor obtained from normalized RDS(ON) junction temperature graph MOSFET data sheet.
External Capacitors
gate-to-source voltage clamp provided ADP3820 protect most MOSFET gates event allowed output suddenly shorted ground. This allows new, RDS(ON) MOSFETs.
Short Circuit Protection
power protected during short circuit conditions with foldback type current limiting that significantly reduces current. Figure foldback current limit information.
Current Sense Resistor
Current limit achieved setting appropriate current sense resistor (RS) across current limit threshold voltage. Current limit sense resistor, calculated shown above. Proper derating advised select power dissipation rating resistor. simplest cheapest sense resistor high current applications, (i.e., Figure trace. However, temperature dependence copper trace thickness tolerances trace must considered design. resistivity copper positive temperature coefficient +0.39%/°C. Copper's Tempco, conjunction with proportional-toabsolute temperature 0.3%) current limit voltage, provide accurate current limit. Table provides typical resistance values copper traces. Alternately, appropriate sense resistor, such surface mount sense resistors, available from KRL, used.
Table Printed Circuit Copper Resistance
Conductor Thickness 1/2oz/ft2
Conductor Width/Inch 0.025 0.050 0.100 0.200 0.500 0.025 0.050 0.100 0.200 0.500 0.025 0.050 0.100 0.200 0.500 0.025 0.050 0.100 0.200 0.500
Resistance 39.3 19.7 9.83 4.91 1.97 19.7 9.83 4.91 2.46 0.98 9.83 4.91 2.46 1.23 0.49 3.25 1.63 0.81 0.325
1oz/ft2
ADP3820 stable with without battery load, virtually good quality output filter capacitors used (anyCAPTM), independent capacitor's minimum (Effective Series Resistance) value. actual value capacitor associated depends capacitance external PMOS device. tantalum aluminum electrolytic capacitor output sufficient ensure stability output current.
Shutdown Mode
2oz/ft2
3oz/ft2 (106
Applying high signal tying input will enable output. Pulling this tying ground will disable output. shutdown mode, controller's quiescent current reduced less than
anyCAP trademark Analog Devices, Inc.
REV.
ADP3820
Layout Issues
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
6-Lead Plastic Surface Mount Package RT-6 (SOT-23-6)
0.122 (3.10) 0.106 (2.70)
0.071 (1.80) 0.059 (1.50)
0.118 (3.00) 0.098 (2.50)
0.037 (0.95) 0.075 (1.90) 0.051 (1.30) 0.035 (0.90) 0.006 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35)
8-Lead Narrow Body Package SO-8
0.1968 (5.00) 0.1890 (4.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
0.0500 (1.27) 0.0160 (0.41)
REV.
PRINTED U.S.A.
C2986a-2-9/99
optimum voltage regulation, place load close possible device's VOUT pins. recommended dedicated traces connect MOSFET's drain positive terminal negative terminal load avoid voltage drops along high current carrying traces.
layout used heatsink, adding many vias around power helps conduct more heat from backplane PCB, thus reducing maximum junction temperature.

Lithium-Ion Battery Charger ADP3820 FUNCTIONAL BLOCK DIAGRAM

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