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MOTOROLA M68302FADS
Application Development System Board User's Manual
CHAPTER GENERAL INFORMATION
INTRODUCTION
This manual provides general information, preparation use, installation operating instructions, functional description, support information M68302FADS Application Development System board.
GENERAL FEATURES
complete system development board processors. MC68302, MC68LC302 MC68PM302. Expansion connectors providing processor signals. Logic analyzer connectors similar expansion connectors. Single supply. MC68302 core running 25MHz. MC68LC302 core running 20MHz. MC68302 core running 20MHz. 512K byte, zero wait state static RAM, expandable byte. orientation) byte FLASH. orientation) byte EEPROM. orientation) Application Development Interface (ADI) port connector. MC68681 DUART, with RS232 serial ports. RESET ABORT controls. HALT status indicators. (LED's). Supports PCMCIA card standard 2.01. (For MC68PM302) Board power controlled from PCMCIA connector host (Important when used developing PCMCIA applications) extender board plugging into PCMCIA port supplied with M68302FADS board. expansion connector out, compatible with 302ADS.
M68302FADS User's Manual
GENERAL INFORMATION
SPECIFICATIONS
M68302FADS specifications cooling requirements given Table 1-1.
Table M68302FADS Specifications
CHARACTERISTICS Power requirements other boards attached) Microprocessor SPECIFICATIONS +5Vdc (typical), 3.15 (maximum) MC68302, MC68LC302, MC68PM302 MC68302 MC68LC302 MC68PM302 byte (4Mb external, LC302 Pchip). 512K byte, wide. (Expandable bytes) byte, bits wide. byte, wide. degrees degrees ambient temperature degrees degrees (non-condensing) 9.196 inches (233.58 8.387 inches (213.03 0.063 inches (1.6
processor addressing Total address range. SRAM FLASH memory EEPROM Operating temperature Storage temperature Relative humidity Dimensions Height Depth Thickness
COOLING REQUIREMENTS
M68302FADS specified designed, tested operate reliably with ambient temperature range from degrees Dynamic Burn-in performed while board table mounted with other boards attached Test software executed board subjected temperature variations. board attached other boards, thermal conditions worsen recommended that operating temperature should exceed degrees
M68302FADS User's Manual
GENERAL INFORMATION
GENERAL DESCRIPTION
M68302FADS development tool MC68302, MC68LC302 MC68PM302 devices. This board used hardware software development applications using member family. M68302FADS logic analyzer connectors well expansion connectors, providing physical connection processors` pins. logic analyzer connectors, enable monitor activity, providing direct connection other logic analyzers. expansion connectors user, attach hardware applications board resources, verify design.
RELATED DOCUMENTATION
following publications applicable M68302FADS provide additional helpful information. MC68302 User's Manual. MC68LC302 User's Manual. MC68PM302 User's Manual. PCMCIA specifications paper
ABBREVIATIONS USED DOCUMENT
MC68302 integrated communication processor. LC302 LCIMP cost version MC68302 integrated communication processor. PM302 Pchip MC68302 integrated with PCMCIA card interface. processor IMP, LC302 PM302. Application Development System family processor. Application Development Interface. UART Universal Asynchronous Receiver/Transmitter. spec Engineering specification document. nsec nano second. µsec micro second. Maskable Interrupt.
REQUIRED EQUIPMENT
M68302FADS operated working environments: Host controlled Stand-alone
M68302FADS User's Manual
GENERAL INFORMATION
FIGURE describes setup host controlled mode. required equipment this mode follows: +5V/3A power supply. Host Computer, following: (Sbus interface) IBM-PC/XT/AT board compatible with host computer. line flat cable with female D-type connectors each end.
FIGURE Host Controlled Configuration
cable
M68302FADS
supply
Running debugger
When board connected shown FIGURE 1-1, turn power supply host software, typing: host <ADI sbus slot No.> <ADS address> manufacturer settings address more details addresses setting, please section example, host machine with card installed Sbus slot number with address, should type, command line prompt: host
M68302FADS User's Manual
GENERAL INFORMATION
prompt get, depends processor installed, listed following table
Table Debugger prompt
Processor MC68302 Prompt Monitor/Debugger Version Copyright 1995 Motorola Inc. Cold Start IMPbug> LC302 Monitor/Debugger Version Copyright 1995 Motorola Inc. Cold Start LC302bug> PCHIP Monitor/Debugger Version Copyright 1995 Motorola Inc. Cold Start PCHIPbug>
MC68LC302
MC68PM302
M68302FADS User's Manual
GENERAL INFORMATION
Stand alone setup
FIGURE describes setup stand-alone operating mode. required equipment this mode +5V/3A power supply. VT100 compatible terminal. RS-232 cable with male D-type connector side.
FIGURE Stand-alone Configuration
RS232 cable
M68302FADS
supply
Terminal settings
terminal connected M68302FASDS board, should initialized work with following settings: Speed 9600 bps. Character size bits. Stop length bit. (1.5 fine preferred being faster) parity.
These settings written shortly 9600, After setting terminal specified turning power, debugger prompt Table 1-2, should appear terminal screen.
M68302FADS User's Manual
GENERAL INFORMATION
Parallel Serial port, priority.
There control board, select between parallel serial port communication. debugger decides automatically, with which should communicate, giving priority serial port, case, terminal detected. serial port some signals, with debugger detect presence terminal. present, then connection ignored board communication, goes serial port. When terminal detected serial port, communication, goes port.
M68302FADS User's Manual
GENERAL INFORMATION
M68302FADS User's Manual
HARDWARE PREPERATION INSTALLATION
CHAPTER HARDWARE PREPERATION INSTALLATION
INTRODUCTION
This chapter provides unpacking instructions, hardware preparation, installation instructions M68302FADS.
UNPACKING INSTRUCTIONS NOTE shipping carton damaged upon receipt, request carrier's agent present during unpacking inspection equipment.
Unpack equipment from shipping carton. Refer packing list verify that items present. Save packing material storing reshipping equipment.
CAUTION AVOID TOUCHING AREAS INTEGRATED CIRCUITRY; STATIC DISCHARGE DAMAGE CIRCUITS.
M68302FADS User's Manual
HARDWARE PREPERATION INSTALLATION
HARDWARE PREPARATION
select desired configuration ensure proper operation M68302FADS board, changes Dip-Switch/Jumpers settings required before installation. Switches, LEDs, Dip-Switches, connectors illustrated FIGURE M68302FADS Location diagram page board been factory tested shipped with Dip-Switch settings described following paragraphs. Parameters changed following conditions: board resources enable (SRAM, Flash, EEPROM, port DUART) width. ON/OFF. Processor type selection. port address selection. Pchip PCMCIA enable. Pchip PCMCIA block power source.
M68302FADS User's Manual
TERMINAL HOST HALT
PCMCIA PCOFF POWER
PORT
HOOK
PCEN PCVCCEN RAMEN FLASHEN EEPROMEN ADIEN DUARTEN ADSA0 ADSA1 ADSA2
HOOK
IOIS16 MODCLK BUSW
CHIPTYPE
FIGURE M68302FADS Location diagram
ABORT
M68302FADS User's Manual
ADDR
ADDR HIGH
LC302
RESET
Pchip PCMCIA
DATA
RLY1
CONTROL
HARDWARE PREPERATION INSTALLATION
HARDWARE PREPERATION INSTALLATION
switch configuration. FIGURE Dip-Switch
PCEN PCVCCEN RAMEN FLSHEN EEPREN ADIEN DUARTEN ADSA0 ADSA1 ADSA2
Table describes function switches
Table Dip-Switch Description
Switch Name PCEN PCVCCEN Function Direct control over Pchip signal PCEN. When internal Pchip PCMCIA interface disabled. When board powered unconditionally, with respect PCMCIA host power. When OFF, board powered, only when host connected board through PCMCIA port, turned When board SRAM enabled. (1Mbyte space) When board FLASH memory enabled. When board EEPROM enabled. When interface enabled. When DUART MC68681 along with RS232 port enabled. Default setting
RAMEN FLSHEN EEPREN ADIEN DUARTEN
M68302FADS User's Manual
HARDWARE PREPERATION INSTALLATION
Port Address Selection (Dip-Switch switches 8-10)
Each M68302FADS have eight possible port addresses, enabling eight M68302FADS boards connected same card host computer. Address selection done setting switches Dip-Switch. Switch most significant address while switch least. switch 'ON' state, stands logical '0'. default setting address Table describes switch settings each slave address:
Table Address Selection
ADDRESS Switch Switch Switch
M68302FADS User's Manual
HARDWARE PREPERATION INSTALLATION
switch configuration (for LC302/PM302). FIGURE Dip-Switch
IOIS16 MODCLK BUSW
CHIPTYPE
Table Dip-Switch description.
Switch Name IOIS16 Function IOIS16 PCMCIA signal level. IOIS16, supported Pchip. When PCMCIA transfers bits width. When off, PCMCIA transfers, bits width. Select multiplication factor when enabled. (See jumpers) selects multiplication factor selects x401 32KHz crystal. Controls BUSW input processor. Selects when width when Selects between LC302/Pchip mode. IMP, LC302 Pchip. Default
MODCLK
BUSW CHIPTYPE
LC302/PM302
FIGURE 1-5, shows default settings LC302 PM302. When plugged switch should other switches same LC302/PM302.
M68302FADS User's Manual
HARDWARE PREPERATION INSTALLATION
INSTALLATION INSTRUCTIONS
When M68302FADS been configured desired user, installed according required working environment follows:
Power Supply Connection
M68302FADS requires +5Vdc max, power supply operation. 3.15A fuses line, protected against reverse connection power supply. Connect power supply connector shown below:
FIGURE P18: Power Connector
terminal block power connector with power plug. plug designed accept wires. recommended wires. insure solid ground, terminals supplied. recommended connect both wires common power supply, while connected with single wire.
NOTE Since hardware applications connected M68302FADS using expansion connectors P12, additional power consumption should taken into consideration when power supply connected ADS.
M68302FADS User's Manual
HARDWARE PREPERATION INSTALLATION
Installation
installation various host computers, refer APPENDIX BOARD INSTALLATION page
Host computer connection
M68302FADS interface connector, pin, male, type connector. connection between M68302FADS host computer made line flat cable, supplied with board. FIGURE below shows connector arrangement connector.
FIGURE Port Connector
N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ INT_ACK N.C. HST_ACK ADS_ALL ADS_RESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK ADS_INT HOST_BRK~ ADS_BRK N.C.
NOTE: connected power supply, used ADS.
Terminal M68302FADS RS-232 Connection. (DCE port)
stand-alone operation mode, VT100 compatible terminal should connected RS-232 connector RS-232 connector pin, female, D-type connector shown FIGURE 1-8.
FIGURE RS-232 Serial Port Connector
N.C.
NOTE: line (pin connected M68302FADS.
M68302FADS User's Manual
HARDWARE PREPERATION INSTALLATION
Secondary RS-232 port. (DTE port)
second RS232 port, controlled, supported debugger. user should write drivers this port. connector shown FIGURE 1-8.
FIGURE RS-232 Serial Port Connector
N.C.
NOTE: line (pin connected M68302FADS.
M68302FADS User's Manual
OPERATING INSTRUCTIONS
CHAPTER OPERATING INSTRUCTIONS
INTRODUCTION
This chapter provides necessary information M68302FADS host-controlled standalone configuration. This includes controls, indicators, memory details, software initialization board.
CONTROLS INDICATORS
M68302FADS following switches indicators.
(Abort) Switch
switch asserts level interrupt processor. switch signal debounced, possible disable software. (Abort) switch normally used abort program execution return debugger control.
RESET Switch
RESET switch SW2, resets devices performs reset processor. switch signal debounced, possible disable software.
LC302 enable jumper
LC302, controlled applying preventing block power, VCCSYN pin. selection, done with jumper, shown FIGURE 1-10.
FIGURE 1-10 LC302 enable jumper (J1) LC302 Disabled When jumper installed pins LC302 disabled. This actually shorts LC302 VCCSYN pin, ground.
LC302
LC302 enabled When jumper installed pins LC302 enabled. This actually connects VCCSYN LC302 VCC.
LC302
M68302FADS User's Manual
OPERATING INSTRUCTIONS
Pchip enable jumper
Pchip, controlled applying preventing block power, VCCSYN pin. selection, done with jumper, shown FIGURE 1-10.
FIGURE 1-11 Pchip enable jumper (J2) Pchip Disabled When jumper installed pins Pchip disabled. This actually shorts Pchip VCCSYN pin, ground.
Pchip
Pchip enabled When jumper installed between pins Pchip enabled. This actually connects VCCSYN Pchip VCC.
Pchip
PCMCIA power source selection
PCMCIA block Pchip, powered sources. first board common supply second external power, supplied through host, plugged into PCMCIA connector. selection, done with jumper, shown FIGURE 1-12.
FIGURE 1-12 Pchip enable jumper (J3) Pchip PCMCIA block powered host When jumper installed pins Pchip PCMCIA block, power from host connected PCMCIA connector
PCMCIA
Pchip PCMCIA block powered board supply board When jumper installed pins Pchip PCMCIA block, power from board common supply.
PCMCIA
M68302FADS User's Manual
OPERATING INSTRUCTIONS
indicator
This yellow indicator connected processor address strobe (AS~) signal. when (asserted) indicate activity.
HALT indicator PCOFF indicator
This indicator, whenever processor HALT~ (asserted).
This orange indicator, when PCMCIA power control selected DIP-Switch switch (PCVCCON position) external power detected PCMCIA connector This reminder user, that board powered, despite power existence, connector. board would powered, upon detection turned PCMCIA connector
Power indicator
This green indicator, when board powered. Please aware that suppling connector does assure powered. When switch switch number position, board power, PCMCIA power dependent. board relay switches power off, unless power detected PCMCIA port. When switch switch number position, board powered when supplied trough P10, unconditionally PCMCIA port status.
M68302FADS User's Manual
OPERATING INSTRUCTIONS
MEMORY
FIGURE 1-13 memory page maps. After cold warm reset, processor's CS0, automatically enabled first block bytes. this page processor sees first bytes bytes FLASH memory installed. other space than those available this time. this point, stack pointer program counter fetched from Flash debugger starts. debugger first tasks, enable shown FIGURE 1-13. done copying code swap task, into processor's dual port jump execute code. code redefines CS0, enable shown FIGURE 1-13 goes back debugger which been moved map, offset 20000H. swap task executed from dual port RAM, would interrupted swap. swap done, order processor vector table (start $0), user would able change those vectors. (and FLASH must after reset)
FIGURE 1-13 memory
FFFFFE
FFFFFF
Reserved MC68302 internal space user applications.
700000 6FFFFE 700001 6FFFFF
610000 600000 5FFFFE 500000 4FFFFE 400000 3FFFFE 300000 2FFFFE
handshake
MC68681 DUART byte EEPROM port data
630001 620001 610001 600001 5FFFFF 510001 500001 4FFFFF 410001
400001 3FFFFF
300001 2FFFFF 200001 1FFFFF 100001 0FFFFF 080001 07FFFF 000001
byte FLASH memory*
200000 1FFFFE 100000 0FFFFE 080000 07FFFE 000000
512K byte static expansion memory 512K byte static base memory*
*Note: debugger uses 0-7FFF Static from 200000 21FFFF Dynamic RAM.
M68302FADS User's Manual
OPERATING INSTRUCTIONS
Each board comes with byte Flash memory (oriented 512K words bits each) 512K bytes static (oriented 256K words bits each). expanded, board total bytes. logic, DUART MC68681 byte EEPROM, occupies each byte which minimum division available, board chip select logic. Each empty space map, considered available user. board resources, disabled, free memory allocation user. Please Table Dip-Switch Description page
DUART MC68681 registers.
Table 2-3, shows MC68681 internal registers. This eight device, connected D0-D7 thus located addresses.
Table MC68681 internal registers Register address
$620001 $620003 $620005 $620007 $620009 $62000B $62000D $62000F $620011 $620013 $620015 $620017 $620019 $62001B $62001D $62001F
Read (R/W~
Mode register (MR1A, MR2A) Status register (SRA) access Receiver buffer (RBA) Input port change register (IPCR) Interrupt status register (ISR) Counter mode: Current counter (CUR) Counter mode: Current counter (CLR) Mode register (MR1B, MR2B) Status register (SRB) access Receiver buffer (RBB) Interrupt vector register (IVR) Input port (unlatched) Start counter command Stop counter command
Write (R/W~
Mode register (MR1A, MR2A) Clock select register (CSRA) Command register (CRA) Transmitter buffer (TBA) Auxiliary control register (ACR) Interrupt mask register (IMR) Counter/Timer upper register (CTUR) Counter/Timer lower register (CTLR) Mode register (MR1B, MR2B) Clock select register (CSRB) Command register (CRB) Transmitter buffer (TBB) Interrupt vector register (IVR) Output port configuration register (OPCR) Output port register (OPR) command Output port register (OPR) reset command
This address used factory testing should accessed user. trigger command. more details about MC68681 DUART, please refer M68000 family reference.
M68302FADS User's Manual
OPERATING INSTRUCTIONS
handshake signals
handshake signals consist out, going signals. going signals read from MC68681 DUART input port found address $62001B from input port located address $600000. second preferred user ability DUART off. outgoing signals interface found DUART output port latch. order port, functional, when DUART disabled, DUART register involved with outgoing handshake signals, were logically duplicated into space. now, outgoing signals, accessed trough base addresses. DUART well ADI. course second preferred from same reason explained above. following tables shows relevant registers well internal each register.
Table registers. Address
$600000 $60001B $60001D $60001F
Read (R/W~
input port DUART input port access access
Write (R/W~
access DUART output port configuration register (OPCR) DUART output port (OPR) command DUART output port (OPR) reset command
DUART output bit, "1", should written desired DUART reset command register. reset DUART output bit, "1", should written into DUART command register.
Table DUART output port set/reset @$60001D/@$60001F
CTS, terminal.
N.C.
EEPROM enable
used
mode
Table DUART input port @$60001B
from terminal.
Read as'0'
HST_EN~
Table input port @600000
Read as'0'
Read as'0'
Read as'0'
ADS_SEL~
ADS_SEL~ signal, member protocol, signal, generated board, report, ADS, selected host. more details protocol, please refer APPENDIX PORT HANDSHAKE DESCRIPTION page
M68302FADS User's Manual
OPERATING INSTRUCTIONS
debugger.
Each M68302FADS board, installed with debugger, resides first sectors FLASH memories, Each sector AM29F040 device, bytes, thus total 128K bytes sectors FLASH), allocated debugger. Those sectors protected software against, accidental programming.
Debugger upgrade.
debugger supports board upgrade capabilities. debugger release, programmed board, without need take FLASHes their sockets without need special programmer. Further instruction will supplied, with each upgrade.
debugger programming, internal processor registers.
initialization done debugger internal family processor registers, writing base address register (BAR) programming CS0, CS2. initialized, processor register block, resides starting from $700000. initilized bytes FLASH starting 200000H. initilized bytes (512K bytes acttualy installed) starting 000000H. initilized 30000H bytes starting 600000H. used ADI, EEPROM DUART. internal division this space, done additional logic, outside the302 processor.
M68302FADS User's Manual
OPERATING INSTRUCTIONS
Functional description FIGURE 1-14 HARDWARE BLOCK DIAGRAM
PCMCIA Connector
Expansion Connectors
Logic Analyzer Connectors
Pchip LC302 MC68302
Address Data Buffers
Clock Generator
MByte Flash Am29F040 KByte SRAM MCM6229A KByte SRAM MCM6229A KByte EEPROM AT28C16 DUART MC68681 Control logic Port Logic Port
Only three processors, used time.
RS-232 Ports
M68302FADS User's Manual
OPERATING INSTRUCTIONS
MC68LC302 LCIMP. (Sheet
LC302 cost version original MC68302 IMP, with additional chip PLL.The LC302, lacks third less pins total. Pins that were taken off, includes upper address lines (A20-A23), function code (F0-F2), arbitration logic (BR~, BG~, BGACK) more. more details please refer MC68LC302 user manual. There packages available LC302. TQFP package. first less functional pins cost package intended your application. package intended primary development tools used M68302FADS. pins added package only FC2, FRZ~, AVEC~ IAC.
MC68302 IMP. (Sheet
first chip family. integrated multi-protocol processor, using well known 68000 core.
MC68PM302 Pchip. (Sheet
Pchip integration original MC68302 IMP, with PCMCIA card logic.As LC302, lacks third less pins total. Pins that were taken off, includes upper address lines (A20-A23), function code (F0-F2), arbitration logic (BR~, BG~, BGACK) more. more details please refer MC68PM302 user manual. There packages available Pchip. TQFP package. first less functional pins cost package intended your application. package intended primary development tools. pins added package only FC2, FRZ~, AVEC~ IAC.
board processors, general
pins processors, available unbuffered user, through expansion logic analyzer connectors. user monitor processor activity connects hardware application during development stage.All processors' pins, buffered from devices minimize their load enable easy connection user hardware application.
Processors' clock (sheet
system clock generated from sources. board clock oscillator, board crystal circuit external clock source. shipped with first option. consist clock oscillator running twice processor speed, followed divide flip flop. divider assure duty cycle almost 50%. clock oscillator device mounted socket easily replaced different clock speed requested. case crystal circuit external clock option desired, please connect your Motorola dealer.
Indicators controls (sheet
reset abort, control buttons, each equipped with debounce circuit prevent oscillations. board run, halt power power indicators.
Control logic (sheet
control logic programmed into MACH220 device. consist following units: Chip select logic Provides chip select SRAM, FLASH, EEPROM, ADI, DUART. chip selects generated from CS0, CS2. first two, MACH reflect signal case CS2, MACH divide range into three sections, bytes each, ADI, EEPROM ADI. DTACK generator DTACK returned devices, accessed chip select logic, except DUART, which DTACK generator FLASH which default, supplying internal DTACK.
M68302FADS User's Manual
OPERATING INSTRUCTIONS
Interrupt controller There level (NMI) interrupt sources, board. Abort switch, abort external interrupt line. interrupt controller, assert level interrupt with auto vector line supports both interrupt modes.Those modes normal dedicated. interrupt controller, reported with DUART output port interrupt operating mode. debugger initializes with normal mode. resources enable Resources like SRAM, FLASH, etc. taken memory (disabled) this logic, user switches selection. wait state logic wait state logic, delays DTACK generation several system clock pulses, programed into MACH device each resource. Chip type selection interface LC302 Pchip, different from original IMP. first glue less design concept interface external devices, through AS~, OE~, WEL~, WEH~ signal. IMP, contrary, uses AS~, R/W~ signals. MACH used interface those signals, according processor installed board. selection between LC302/Pchip IMP, done switch switch DS2) buffers control This logic control data buffers bits width.
control logic (sheet
MACH100 device, controls interface. interface appears sheet (See APPENDIX PORT HANDSHAKE DESCRIPTION, more details interface.
Buffers (sheet
minimize signal load processors pins, address data lines buffered. buffers support width well.
SRAM (sheet
supplied with Kilobyte SRAM, which implemented four MCM6229A devices. devices organized word bits wide). SRAM access time nsec. Another bank four MCM6229A devices soldered increase SRAM memory space Mbyte.
Flash Memory (sheet
Kilobyte Flash Memory devices, 29F040, used form Mbyte program storage memory. devices organized word bits wide). Flash Memory access time nsec. Flash Memory devices mounted sockets, enable user load code, board.
EEPROM. (sheet
EEPROM used AT28C16 device (250 nano-seconds access time, bit). appears static read write cycle, with write cycle extended millisecond. During internal write cycle, 68302 must access EEPROM, access other device performs data polling EEPROM detect write cycle. data polling feature EEPROM, enables 68302 detect internal write cycle. During internal write cycle, processor, read last byte written EEPROM. internal write cycle process, then result complement written data else result true data. Only data pulling access, will return correct results from EEPROM, during internal write cycle. AT28C16
M68302FADS User's Manual
OPERATING INSTRUCTIONS
internal hardware protection, against inadvertent writes EEPROM, that might happen during power power down time.
port (sheet
interface uses drivers communicate with host. parallel port supplies parallel link from various host computers. This port connected line cable special board called (Application Development Interface) installed host computer. possible connect board IBM-PC/XT/AT SUN-4 SPARC station, provided that they have board with appropriate software drivers installed them. Each ADS, possible slave addresses, port, enabling boards connected same part. address selected switch found sheet port connector pin, male, type connector. (Same connector used communicating with board command converter). connection between host computer line flat cable, supplied with board. FIGURE 1-15 below shows configuration connector.
FIGURE 1-15 Port Connector
N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ INT_ACK N.C. HST_ACK ADS_ALL ADS_RESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK ADS_INT HOST_BRK~ ADS_BRK N.C.
Port Signal Description
list below, directions 'I', 'I/O' refer board. (I.E. means input ADS) -'I' These three inputs determine board address. address being set, would only which board respond, when referenced host computer. boards addressed port. ADS_ALL -'I' This input line used reset abort program execution development boards that connected same board. When this line active, board command converter, simultaneously referenced. -'I' This line always driven board. hardware uses this line determine host connected port. -'I'
M68302FADS User's Manual
OPERATING INSTRUCTIONS
This line used conjunction with addressing lines with ADS_ALL line generate non-maskable interrupt (interrupt level processor. -'I' When host connected, this line used conjunction with addressing lines with ADS_ALL line reset board. -'I' This signal initiates host write cycle. -'O' This signal response HOST_REQ signal, indicating that board detected assertion HOST_REQ. -'O' This signal initiates host write cycle. -'I' This signal serves host's response ADS_REQ signal. -'O' This open-collector signal, generates interrupt host. This signal common boards that connected same ADI. -'O' This line polled host computer during interrupt acknowledge cycle determine which board generated interrupt. -'I' This line asserted host interrupt acknowledge cycle. This signal used hardware negate HOST_BRK~ signal. software, must negate ADS_INT signal upon detecting assertion INT_ACK, support daisy-chain interrupt structure. -'I' (three lines) These power lines, used logic, determine host computer powered does these lines power supply. -'I/O' These eight lines parallel data bus. This used transmit receive data from host computer.
MC68681 DUART (sheet
MC68681 DUART device connected 68302 part that provides with following functions: programmable counter/timer. Port interface 68302 part. RS-232 ports interface. debugger initializes port DUART, work with 9600bps, data, stop parity.
DUART Clock Source
MC68681 uses 3.6864Mhz crystal clock source, thus communication rate, independent system clock. crystal connected, between pins, DUART.
RS-232 serial ports. (sheet
RS-232 serial ports connected channels MC68681 DUART. connected VT100 compatible terminal through primary serial port connector), which
M68302FADS User's Manual
OPERATING INSTRUCTIONS
only supported debugger. Both ports pin, D-type, female connector shown FIGURE 1-8.
FIGURE 1-16 RS-232 Serial Ports Connector
(N.C) N.C.
(N.C) N.C.
Primery port (DCE port)
Secoundary port (DTE port)
Primary RS-232 port Signal Description
list below, directions 'I', 'I/O' refer board. (I.E.'I' means input ADS) Data Carrier Detect. This line always asserted ADS. Transmit Data. Receive Data. Data Terminal Ready. This signal used software detect terminal connected board. Data Ready. This line always asserted ADS. Request Send. This line connected ADS. Clear Send. This line always asserted ADS.
secondary port above signals with opposite flow direction.
PCMCIA Connector (sheet
PCMCIA interface pins Pchip appears Sbus miniature connector, which interfaced, into PCMCIA port, trough extender. does host PCMCIA power, relay used power ADS, upon power detection, PCMCIA connector pins. user choose this relay switch selection.
M68302FADS User's Manual
SUPPORT INFORMATION
CHAPTER SUPPORT INFORMATION
INTRODUCTION
This chapter provides interconnection signals, parts list, schematic diagrams M68302FADS board.
INTERCONNECT SIGNALS
M68302FADS board interconnects with external devices through following connectors, listed Table 2-8.
Table Board interconnection
Reference Type pin, male type connector pin, female type connector pin, female type connector male, miniature Sbus connector pin, male connectors, compatible with logic analyzer connector pin, male connector pin, female connector power connector Function port RS232 terminal port (DCE) RS232 host port (DTE) PCMCIA extender interface logic analyzer connectors logic analyzer connectors expansion port connectors power supply input
M68302FADS User's Manual
SUPPORT INFORMATION
Connector Interconnect Signals
pin, male type connector. port M68302FADS. signals, listed Table 2-9. following table, input output signals, refer board)
Table Connector Interconnect Signals
Signal Name INT_ACK HST_ACK ADS_ALL ADS_RESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK ADS_INT HOST_BRK~ ADS_BRK HOST_VCC HOST_ENABLE~ Description Interrupt Acknowledge input signal. connected Host Acknowledge input signal. All, input signal. Reset input signal. Select input signal. (ADI address Select input signal. (ADI address Select input signal. (ADI address HOST Request, input signal. Request, output signal. Acknowledge, output signal. Interrupt, output signal. HOST Break open collector, output signal. Break, input signal. connected port data port data port data port data board common ground connected. host supplies +12V this pin, connected M68302FADS HOST input (+5V). M68302FADS does these inputs power supply. HOST Enable, input signal. Ground signal M68302FADS port data port data port data port data
M68302FADS User's Manual
SUPPORT INFORMATION
Connector Interconnect Signals
pin, female type connector. RS232 serial port M68302FADS. signals listed Table 2-9. following table, input output signals, refer board)
Table 2-10 Connector Interconnect Signals
Signal Name (N.C.) Description Carrier Detect output. Transmit Data output. Receive Data input. Data Terminal Ready input. Ground signal ADS. Data Ready output. Request Send. This line connected ADS. Clear Send output. connected
Connector Interconnect Signals
type female connector. host secondary RS232 port. Signals listed Table 2-13.
Table 2-11 Connector Interconnect Signals
Signal Name (N.C) Description Transmit Data input. connected Receive Data output. Data Terminal Ready output. Ground signal ADS. Data Ready input. Request Send output. Clear Send input. This line connected connected
Connector interconnect signals
pin, SBUS type connector. PCMCIA extender port. signals listed Table 2-12.
Table 2-12 Connector interconnect signals
Signal name Description Board common ground PCMCIA data PCMCIA data PCMCIA data PCMCIA data
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Table 2-12 Connector interconnect signals
Signal name CE1~ VPP1 IOIS16~ CD1~ CE2~ RFRSH IORD IOWR Description PCMCIA data Card enable PCMCIA address PCMCIA output enable PCMCIA address PCMCIA address PCMCIA address PCMCIA address (Not supported) PCMCIA address (Not supported) PCMCIA write enable PCMCIA ready output. Host power. Programming voltage (Not supported) PCMCIA address (Not supported) PCMCIA address (Not supported) PCMCIA address (Not supported) PCMCIA address PCMCIA address PCMCIA address PCMCIA address PCMCIA address PCMCIA address PCMCIA address PCMCIA address PCMCIA data PCMCIA data PCMCIA data (Set board jumper) Board common ground Board common ground PCMCIA card detect (Grounded) PCMCIA data PCMCIA data PCMCIA data PCMCIA data PCMCIA data PCMCIA card enable supported PCMCIA read PCMCIA write
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Table 2-12 Connector interconnect signals
Signal name VPP2 WAIT IPACK SPKR SCHG~ CD2~ Description PCMCIA address PCMCIA address PCMCIA address PCMCIA address PCMCIA address Host supported PCMCIA address PCMCIA address PCMCIA address PCMCIA address Reserved future PCMCIA reset PCMCIA wait Input port memory attribute supported PCMCIA status changed PCMCIA data PCMCIA data PCMCIA data PCMCIA card detect (Grounded) Board common ground
Connector Interconnect Signals
dual row, pin, male connector. upper address control signals processor, appear this connector, easy monitoring logic analyzer. connector signals listed Table 2-13.
Table 2-13 connector interconnect signals
Signal name WEH~/UDS~ Description connection connection write enable high/upper data strobe address line address line address line address line address line address line address line
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Table 2-13 connector interconnect signals
Signal name WEH~/UDS~ Description address line address line address line address line address line address line address line address line write enable high/upper data strobe Board common ground
Connector Interconnect Signals
dual row, pin, male connector. upper address control signal processor, appear this connector, easy monitoring logic analyzer.P9 connector signals listed Table 2-14.
Table 2-14 connector interconnect signals
Signal name WEL~/LDS~ BGACK~ WEH~/UDS~ WEL~/LDS~ OE~/R/W~ Description connection connection write enable low/lower data storbe grant acknowledge function code function code function code internal access write enable high/upper data strobe write enable low/lower data strobe output enable/read write address line address line address line address line address line address line address line address line Board common ground
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Connector interconnect Signals
dual row, pin, male connector. processor data appears this connector, easy monitoring logic analyzer. signals listed Table 2-16.
Table 2-15 interconnect signals
Signal name connection connection address strobe data line data line data line data line data line data line data line data line data line data line data line data line data line data line data line data line Board common ground Description
Connector interconnect Signals
dual row, pin, male connector. processor data appears this connector, easy monitoring logic analyzer. signals listed Table 2-16
Table 2-16 interconnect signals
Signal name CLKO CS3~ CS2~ AVEC~ BERR~ RST~ connection connection clock chip select line chip select line auto vector error reset Description
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Table 2-16 interconnect signals
Signal name CLKO DTACK~ HALT~ CS1~ IPL2~ IPL1~ IPL0~ CS0~ Description clock data transfer acknowledge halt control request chip select line interrupt priority level interrupt priority level interrupt priority level grant chip select line address strobe Board common ground
Connector interconnect signals
row, female connector. processors signals, routed directly P12, user hardware applications. signals listed Table 2-17.
Table 2-17 Connector interconnect signals
Signal name RMC~ CS3~ OE~/R/W~ Description Board common ground Board common ground Board common ground address line address line address line address line address line address line address line function code read modify write cycle chip select port internal access common port function code data data output enable/read write
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Table 2-17 Connector interconnect signals
Signal name DTACK~ BERR~ IPL1~ IPL2~ PA15 BGACK~ FRZ~ PA13 CS0~ PB11 PB10 WEH~/UDS~ AVEC~ IPL0~ EXTAL RST~ PA12 Description data data transfer acknowledge error interrupt priority level interrupt priority level port grant acknowledge freeze port grant board common supply Board common ground address Board common ground address address address address address address address function code chip select port port port port port write enable high/upper data strobe data data address strobe data data auto vector interrupt priority request external clock input/crystal reset port
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Table 2-17 Connector interconnect signals
Signal name busw CS1~ CS2~ WEL~/LDS CLKO BCLR~ HALT~ PA14 Description data width board common supply board common ground board common ground board address address address address address address address address chip select chip select port port port port port data data write enable low/lower data strobe data data data clock data clear data data halt control port board common supply
Connector Interconnect Signals
connector power supply. connector supplied with plug convenient
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connection power supply. connector signals, listed Table 2-9.
Table 2-18 Connector interconnect Signals
Signal Name Description Power supply, connection. Power supply, ground connection. Power supply, ground connection.
Connector Interconnect Signals
row, pin, male connector. This connector, together with processor pins easy interfacing logic analyzer. signals, listed Table 2-19.
Table 2-19 Connector interconnect signals
Signal name IPB0 IPB1 IPB2 IPB3 IPB4 IPB5 IPB6 IPB7 IPB8 IPB9 IPB10 IPB11 PDI(8) PDI(9) PDI(10) PDI(11) PDI(12) PDI(13) PDI(14) RXD1 TXD1 CD1~ CTS1~ Description Board common ground Board common ground Board common ground port port port port port port port port port port port port Board common ground port port port port port port port Board common ground Board common ground SCC1 receive data input SCC1 transmit data output SCC1 carrier detect SCC1 clear send
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Table 2-19 Connector interconnect signals
Signal name RTS1~ PCD0 PCD1 PCD2 PCD3 N.C. PCA3 PCA4 PCA5 PCRDY PCOE~ PCCE1~ PCREG~ PCWAIT~ PCSTSCH~ Description SCC1 request sent Board common ground Board common ground Board common ground Board common ground Board common ground PCMCIA data PCMCIA data PCMCIA data PCMCIA data connect Board common ground PCMCIA address PCMCIA address PCMCIA address Board common ground PCMCIA ready signal PCMCIA output enable PCMCIA card enable Board common ground PCMCIA signal PCMCIA wait signal PCMCIA status change signal Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground Board common ground port port
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Table 2-19 Connector interconnect signals
Signal name PA10 PA11 PA12 PA13 PA14 PA15 BRG1~ RCLK1 TCLK1 CTS3~ RTS3~ CD3~ Description port port port port port port port port port port port port port port Board common ground baud rate generator output Board common ground receive clock Board common ground receive clock Board common ground SCC3 clear send SCC3 request send carrier detect Board common ground Board common ground Board common ground
Connector interconnect signals
row, female connector. Processor signals, directly routed connectors, user hardware applications. connector signals, listed Table 2-20.
Table 2-20 Connector interconnect signals
Signal name Description Board common supply Board common supply Board common ground port port
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Table 2-20 Connector interconnect signals
Signal name PB10 PB11 PDI8 PDI9 PDI10 PDI11 PDI12 PDI13 PDI14 RXD1 TXD1 CD1~ CTS1~ RTS1~ EXTNMI~ PCD0 PCD1 PCD2 PCD3 N.C. PCA3 PCA4 PCA5 Description port port port port port port port port port port Board common ground port port port port port port port Board common ground Board common ground SCC1 receive data SCC1 transmit data SCC1 carrier detect SCC1 clear send SCC1 request send Board common ground Board common ground Board common supply external level interrupt source Board common ground PCMCIA data PCMCIA data PCMCIA data PCMCIA data connect Board common ground PCMCIA address Board common ground Board common ground Board common ground
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Table 2-20 Connector interconnect signals
Signal name PCRDY PCOE~ PCCE1~ PCREG~ PCWAIT~ PCSTSCHG~ BCLR~ RMC~ DISCPU PA10 PA11 PA12 PA13 PA14 PA15 BRG1 Description PCMCIA ready signal PCMCIA output enable PCMCIA card enable Board common ground PCMCIA signal PCMCIA wait signal PCMCIA status change Board common ground clear read modify write cycle Board common ground disable Board common ground Board common ground Board common ground Board common ground Board common ground Board common supply Board common supply Board common supply Board common ground Board common ground port port port port port port port port port port port port port port port port Board common ground baud rate generator
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Table 2-20 Connector interconnect signals
Signal name RCLK1 TCLK1 CTS3~ RTS3~ CD3| Description Board common ground receive clock connect transmit clock Board common ground clear send request send carrier detect Board common ground Board common ground board common supply
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Table 2-21 Part list
Reference (Alternative C1A) (Alternative (Alternative C2A) (Alternative (C7) C67C68 (C39) (C44) (Alternative D1A, D2A) (Alternative Part NO/Value 220uF/25V Alum. 220uF/10V TPSE227K010R 47uF/16V Alum. 47uF/10V TAJD476K010 0.1uF/50V 1206 Manufacturer Nippon Nippon total
10uF/20V 5A-100KAT00J 1.5nF/50V 1206 10pF/50V 1206 1nF/50V 1206 4.7pF/50V 1206-5A4R7KAT00J 15pF/50V 1206-5A150KAT00J 1N4148 LL4148 MBRD620CT 1SMC50AT3 10PST HBW10S Fuse 3.155A/250V Fast 5x20mm 2170005 Fuse holder PTF15 jumper Yellow LY-T670-HK LR-T670-HK Orange LO-T670-HK Green LG-T670-HK D-type male clip conn. D-type female clip conn. male mini SBUS conn. logic analyzer conn. DIN96p female clip
Nippon
Motorola Motorola Grayhill
Siemens Siemens Siemens Siemens Keltron Keltron Molex Elco
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Table 2-21 Part list
Reference (R2) (R5) (R6) RLY1 Part NO/Value male power conn. DIN96p straight 168477096001025 1/4W 1206 1/4W 1206 1/4W 1206 1/4W 1206 470K 1/4W 1206 1/4W 1206 1/4W 1206 100K 1/4W 1206 1/4W 1206 1/4W 1206 Relay SPDT 42319005 13x4.7K SOMC1401472 8x22 16DIP SOMC1603220J Push button SPDT E121SD1AV2GE 8018/3 (For SW2) Black 8018/2 (For SW1) 74LS244D 74ACT244D MACH110-2oJC PLCC socket 74F543 AM29F040-90 PLCC socket 205-032-10 AT28C16-15JC PLCC socket 205-032-10 SPARE MC68302RC 132p socket 13x13 MCM6229A 74ACT245 MC68LC302 132p socket 13x13 MACH220-12JC PLCC socket 205-068-10 MC68PM302RC 181p socket 15x15 MC145407 MC68681FN Manufacturer Molex Elco Finder Dale Dale total
(U9) (U39) **U10 (U11) (U14) (U17) (U20) **U23 *U24 **U27
Motorola Motorola Motorola Atmel Motorola Precidip Motorola Motorola Motorola Precidip Motorola Precidip Motorola Motorola
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Table 2-21 Part list
Reference *U34 (Y1) Part NO/Value 74ACT08D 74ACT00D 74ACT74D 40MHz Osc. HXO-125532 socket. 74LS05D 74HC4538D 74ACT14D 32KHz 4MHz crystal HC49U 3.6864MHz crystal HCU46 Rubber Manufacturer Motorola Motorola Motorola Precidip Motorola Motorola Motorola total
read table.
(U1) **U1 Component assembled. Component should mounted socket. Only socket should assembled.
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APPENDIX BOARD INSTALLATION
INTRODUCTION
This appendix describes hardware installation board into various host computers. installation instructions, cover following host computers: IBM-PC/XT/AT (SBus interface)
IBM-PC/XT/AT M68302FADS Interface
board should installed IBM-PC/XT/AT mother board system, expansion slots. single control, eight M68302FADS boards. address, host computer, configured addresses space,100-102 (hex), reconfigure, alternate address space.
CAUTION BEFORE REMOVING INSTALLING EQUIPMENT IBM-PC/XT/AT COMPUTER, TURN POWER REMOVE POWER CORD. Installation IBM-PC/XT/AT
Refer appropriate Installation Setup manual IBM-PC/XT/AT computer, instructions removing computer cover. board address block, should configured free address space. address must unique must fall within address range, another card installed computer. board address block configured start three following addresses: $100 This address unassigned IBM-PC $200 This address usually used game port $300 This address defined prototype port board factory configured address decoding 100-102 IBM-PC/XT/AT address map. These undefined peripheral addresses.
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FIGURE Physical Location jumper
NOTE: Jumper should left unconnected. following figure, shows required jumper connection, each address configuration. Address recommended usage might cause problems.
FIGURE Configuration Options
properly install board, position front bottom corner plastic card guide channel, front IBM-PC/XT/AT chassis. Keeping board ribbon cables, way, lower board until connectors aligned with computer expansion slot connectors. Using evenly distributed pressure, press board straight down until seats expansion slot. Secure board computer's chassis, using bracket retaining screw. Refer computer Installation Setup manual, instructions reinstalling, computer cover.
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SUN-4 M68302FADS Interface
board should installed SBus expansion slots Sun-4 SPARCstation. single ADI, control eight M68302FADS boards.
CAUTION BEFORE REMOVING INSTALLING EQUIPMENT SUN-4 COMPUTER, TURN POWER REMOVE POWER CORD. Installation SUN-4 machine
There jumper options, board, Sun-4 machine. board inserted into available SBus expansion slot, mother board. Refer appropriate Installation Setup manual Sun-4 computer instructions removing computer cover installing board expansion slot.
FIGURE board SBus
Connector
SBus Connector
Following Sun's manual, instructions summary: Turn power your system, keep power cord, plugged sure save open files follow steps bellow, shut down your system: hostname% /bin/su Password: mypasswd hostname# /usr/etc/halt wait following messages. Syncing file systems. done Halted Program Terminated Type b(boot), c(continue), n(new command mode) When these messages appear, safely turn off, your system power. Open system unit. sure attach grounding strap, your wrist power supply, metal casing. Follow instructions supplied with your system, gain access SBus slots.
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Remove SBus slot filler panel, from inner surface back panel your system unit. Note that board, slave only board thus will function available SBus slot. Slide board angle, into back panel your system unit. Make sure, mounting plate board, hooks into holes back panel your system unit. Push board against back panel, align connector with mate gently press board corners, plug connector firmly. Close your system unit. Connect interface flat cable board secure. Turn system power check proper operation.
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APPENDIX PORT HANDSHAKE DESCRIPTION
INTRODUCTION
M68302FADS port, connected board, mounted host computer. There boards following host computers: IBM-PC/XT/AT (SBus interface)
Port Concept Operation Description
Each board, connected with M68302FADS boards. Each address which fixed setting Dip-Switch switches 8-10, board. following operations performed using port: host computer write byte write byte host computer interrupt host computer host computer interrupt (interrupt level host computer reset more than ADS, connected same board, host computer perform following operations simultaneously M68302FADS boards: Abort boards (interrupt level Reset boards
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Handshake Description
Every action between host, asynchronous implemented asserting negating handshake signals trough software. signals have levels. control signal asserted, when driven logic'1' level, negated when driven logic'0' level. connection between host computer ADS, shown FIGURE below.
FIGURE Host Computer (ADI) M68302FADS Connection
HOST_REQ ADS_ACK ADS_REQ HST_ACK ADS_BRK HOST_BRK~
HOST COMPUTER
board
ADS_INT INT_ACK ADS_RESET ADS_ALL ADS_SEL(0:2) PD(0:7) HOST_ENABLE~ HOST_VCC
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Write Cycle from Host M68302FADS
application software Host, uses handshake signals, coordinate data transfer across parallel link. software installed ADS, responsible accepting data, responding handshake signals. signals shown FIGURE B-2. sequence events during byte write M68302FADS, follows: Host selects M68302FADS board, placing board address, ADS_SEL(0:2) lines. Host places data byte, data latch (Its output buffer, high-impedance state). Host asserts HOST_REQ signal (data buffer enabled. data appears bus). ADS, detects HOST_REQ signal reads data byte. respond asserting ADS_ACK signal. Host detects ADS_ACK signal negates HOST_REQ signal (data buffer disabled). detects HOST_REQ negation negates ADS_ACK cycle.
FIGURE Host Write M68302FADS ADS_SEL(0:2) HOST_REQ ADS_ACK PD(0:7) DATA VALID ADDRESS VALID
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Write Cycle from M68302FADS Host
Signal handshake during Host write cycle shown FIGURE B-3. sequence events, follows: M68302FADS places data byte parallel port data (buffer disabled) asserts ADS_REQ signal. (the ADS_REQ signal does appear port, until board selected Host) Host polls each address detects ADS_REQ signal from requesting board. Host asserts HST_ACK signal response, which enables data buffer. negates ADS_REQ signal. Data appears bus, long HST_ACK signal asserted. Host reads data. Host negates HST_ACK signal, cycle. ends cycle.
FIGURE M68302FADS Write Cycle Host ADS_REQ PD(0:7) DATA VALID
ADS_SEL(0:2) HST_ACK
ADDRESS VALID
M68302FADS Interrupt Host
M68302FADS generate interrupt Host. Interrupt request acknowledge sequence, shown FIGURE B-4. sequence follows: ADS, places service request code parallel port data (buffer disabled) asserts ADS_INT HOST_BRK~ signals. HOST_BRK~ signal open-collector signal, asserted low, common boards, that appears immediately port. ADS_INT signal does appear port, until board selected Host. Host detects HOST_BRK~ signal polls each address determine interrupting board. Host asserts HST_ACK signal, enabling data buffer. Host reads service request code data bus. Host negates HST_ACK signal. Host asserts INT_ACK signal, which resets HOST_BRK latch, negates HOST_BRK~ signal. HOST_BRK~ signal remain (asserted) another board driving low. selected ADS, detects INT_ACK signal negates ADS_INT signal. Host negates INT_ACK signal ends cycle.
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FIGURE M68302FADS Interrupt Host hardware ADS_INT PD(0:7) ADS_SEL(0:2) HST_ACK INT_ACK ADDRESS VALID DATA VALID software
HOST_BRK~
Host Interrupt M68302FADS
Host interrupt (interrupt level abort program execution, running board. This done selecting address required momentarily asserting ADS_BRK signal, which sets latch. latch output, interrupts processor cleared interrupt handling software ADS.
Host Reset M68302FADS
Host perform reset ADS. Reset done selecting address required board asserting ADS_RESET signal, more than microseconds.
Addressing M68302FADS
Host reset interrupt M68302FADS boards, which connected same card. host should assert ADS_ALL signal, conjunction with either ADS_RESET ADS_BRK. contents ADS_SEL(0:2) lines have affect.
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APPENDIX equations.
control logic U24.
family control logic. Logic includes logic, DTACK generator, interrupt controller, arbiter, resources enable, buffers control reg. module _302fmlyADS title '302 family control logic. Device declaration. device 'mach220a'; Pins declaration. signals. CLKO "Clock. "Address strobe. "Internal access. "Address lines. (Int level) A16, A17, A18, 57,56,40,37;"Address lines ack. CS0~, CS1~, CS2~ "Chip select lines. FC0, FC1, "Function code lines. WEL~ "WEL~/WE~ LDS~/DS~ IMP. WEH~ "WEH~/A0 UDS~/A0 IMP. "OE~ R/W~ control (in). BR_W~ "Buffered R/W~ (out.) BUSW "Bus width control. Rst~ "Reset signal. Halt~ "Halt signal. IPL0~, IPL1~, IPL2~ "Interrupt priority; AVEC~ "Auto vector. Buffer control signals. BusL~ "Data buffer D0-D7 enable. BusL2H~ "D0-D7 D8-D15 bus, enable. BusH~ "Data buffer D8-D15 enable. signals. RamLCs~ "RAM
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RamHCs~ ExpRamLCs~ ExpRamHCs~ FlashLCs~ FlashHCs~ EepromCs~ DuartCs~ AdiRd~ AdiWr~
"RAM high "Expansion "Expansion high "FLASH "FLASH high "EEPROM (Connected D0-D7) "DUART "Adi port, read enable. "Adi port, write enable.
"Low/High control split, only deviding signal load. RdL~ "Bus low, read signal. RdH~ "Bus high, read signal. WrL~ "Bus low, write signal. WrH~ "Bus high, write signal. Resources enable signals. RamEn~ board enable signal. FlashEn~ board FLASH enable signal. EepromEn~ board EEPROM enable signal. EepromWriteEnable~ "EEPROM write enable From DUART port. DuartEn~ board DUART enable signal. AdiEn~ board enable signal. Processor type selection. ChipType "Processor type selection. DTACK generator signals. Dtack~ "DTACK~ processor; DtackOe NODE; "DtackOe, controls Dtack~ output "enable. logical inverse "the Dtack~ signal, with delay "about 15nsec. This way, Dtack~ "output enable, stayes active 15nsec "after Dtack~ posage active "pullup behavior obtained. Reset control. ExtRst~ "External reset. Reset sources
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"Power ADI, PCMCIA, reset "switch. Local interrupt controller. come from sources ADI, External abort switch. ExtNmi~ "NMI input. ExtNmiState0, ExtNmiState1 NODE; "NMI F.F. ExtNmiState0, ExtNmiState1 ISTYPE 'reg, buffer'; ExtNmiFlag NODE; "Reports external condition. IntMode ExtNmiAck NODE; "Int. mode selection. (Normal/Dedicated) "External acknowledge.
Delayed CS2~ DUART. (Postponed after R/W~, DUART) CS2~_DLY1 NODE; "First delay F.F. CS2~_DLY1 ISTYPE 'reg, neg'; CS2~_DLY2 NODE; "Second delay F.F. CS2~_DLY2 ISTYPE 'reg, neg';
Wait state logic, signals. WaitState3, WaitState2, WaitState1, WaitState0 NODE; "Wait state counter. WaitState3, WaitState2, WaitState1, WaitState0
ISTYPE 'reg, buffer';
Constant declaration. .X., .Z.; .C., .D., .U.; READ WRITE !READ; BYTE WORD !BYTE;
CS0~_ACTIVE CS1~_ACTIVE CS2~_ACTIVE OE~_ACTIVE WEL~_ACTIVE WEH~_ACTIVE LDS~_ACTIVE UDS~_ACTIVE
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ADI_RD~_ACTIVE ADI_WR~_ACTIVE AS~_ACTIVE RAM_EN~_ACTIVE RAM_L_CS~_ACTIVE RAM_H_CS~_ACTIVE EEPROM_EN~_ACTIVE EEPROM_CS~_ACTIVE EEPROM_WRITE_ENABLE~_ACTIVE FLASH_EN~_ACTIVE FLASH_L_CS~_ACTIVE FLASH_H_CS~_ACTIVE DUART_EN~_ACTIVE DUART_CS~_ACTIVE ADI_EN~_ACTIVE IAC_ACTIVE EXT_NMI~_ACTIVE EXT_RST~_ACTIVE RST~_ACTIVE EXT_NMI_ACK_ACTIVE DTACK~_ACTIVE
FUNC_INT_ACK_CYCLE ADDR_INT_ACK_CYCLE EXT_NMI_INT_LEVEL NORMAL_INT_LEVEL_7 DEDICATED_INT_LEVEL_7 INT_LEVEL_0 "Normal mode level 0,0,0. "Dedicated mode level IPL2~=0. active interrupt, level.
NORMAL_INT_MODE DEDICATED_INT_MODE !NORMAL_INT_MODE; Address FunctionCode IntLevel IPL~ WaitState [A19, A18, A17, A16]; [FC2, FC1, FC0]; [A3, A1]; [IPL2~, IPL1~, IPL0~]; [WaitState3, WaitState2, WaitState1, WaitState0];
"Wait state macroes. ONE_WAIT_STATE TWO_WAIT_STATES THREE_WAIT_STATES FOUR_WAIT_STATES FIVE_WAIT_STATES SIX_WAIT_STATES SEVEN_WAIT_STATES EIGHT_WAIT_STATES NINE_WAIT_STATES TEN_WAIT_STATES ELEVEN_WAIT_STATES TWELVE_WAIT_STATES THIRTEEN_WAIT_STATES
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FOURTEEN_WAIT_STATES FIFTEEN_WAIT_STATES "Processor types. LC302 IMP+1; "Address resolution bytes. RAM_ADDRESS [0,X,X,X]; EXP_RAM_ADDRESS [1,X,X,X]; ADI_ADDRESS [0,0,0,0]; EEPROM_ADDRESS [0,0,0,1]; DUART_ADDRESS [0,0,1,0]; ADI_PORT_ACCESS (AdiRd~==ADI_RD~_ACTIVE) (AdiWr~==ADI_WR~_ACTIVE) EXT_NMI_ACK_CYCLE Vector macroes. Enternal machine states. ExtNmiState [ExtNmiState1, ExtNmiState0]; WAIT_FOR_NMI_RELEASE_STATE WAIT_FOR_NMI_INSERT_STATE WAIT_FOR_NMI_RELEASE_STATE NMI_ACTIVE_STATE WAIT_FOR_NMI_INSERT_STATE Vector macroes. Equations, state diagrams. ####### #### ##### #### #### ##### #### ###### ####### #### #### #### Buffers control. BUSL~ enables D0-D7, BUSH~ enable D8-D15, BUSL2H enables connect D8-D15 with lines D0-D7, This feature enable access when running width mode.
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equations !BusL~ ((BUSW==WORD) ((BUSW==BYTE) (WEH~==1))) (AS~==AS~_ACTIVE) ((CS0~==CS0~_ACTIVE) (FlashEn~==FLASH_EN~_ACTIVE)) ((CS1~==CS1~_ACTIVE) (RamEn~==RAM_EN~_ACTIVE)) ((CS2~==CS2~_ACTIVE) (((Address==EEPROM_ADDRESS) (EepromEn~==EEPROM_EN~_ACTIVE)) ((Address==ADI_ADDRESS) (AdiEn~==ADI_EN~_ACTIVE)) ((Address==DUART_ADDRESS) (DuartEn~==DUART_EN~_ACTIVE)))) !BusL2H~ (BUSW==BYTE) (WEH~==0) (AS~==AS~_ACTIVE) "WEH~/A0 ((CS0~==CS0~_ACTIVE) (FlashEn~==FLASH_EN~_ACTIVE)) ((CS1~==CS1~_ACTIVE) (RamEn~==RAM_EN~_ACTIVE)) ((CS2~==CS2~_ACTIVE) (((Address==EEPROM_ADDRESS) (EepromEn~==EEPROM_EN~_ACTIVE)) ((Address==ADI_ADDRESS) (AdiEn~==ADI_EN~_ACTIVE)) ((Address==DUART_ADDRESS) (DuartEn~==DUART_EN~_ACTIVE)))) !BusH~ (BUSW==WORD) (AS~==AS~_ACTIVE) ((CS0~==CS0~_ACTIVE) (FlashEn~==FLASH_EN~_ACTIVE)) ((CS1~==CS1~_ACTIVE) (RamEn~==RAM_EN~_ACTIVE)) ((CS2~==CS2~_ACTIVE) (((Address==EEPROM_ADDRESS) (EepromEn~==EEPROM_EN~_ACTIVE)) ((Address==ADI_ADDRESS) (AdiEn~==ADI_EN~_ACTIVE)) ((Address==DUART_ADDRESS) (DuartEn~==DUART_EN~_ACTIVE))))
Delayed CS2~. CS2~ delayed generate R/W~ before CS2~, DUART. equations CS2~_DLY1.clk CLKO; CS2~_DLY2.clk CLKO; CS2~_DLY1.ar CS2~_DLY2.ar !Rst~; !Rst~;
CS2~_DLY1 CS2~; CS2~_DLY2 CS2~_DLY1; signals. RAM, FLASH, EEPROM, DUART. equations !RamLCs~ (CS1~==CS1~_ACTIVE) (Address==RAM_ADDRESS) (RamEn~==RAM_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==1)) "WEH~ mode. !RamHCs~ (CS1~==CS1~_ACTIVE) (Address==RAM_ADDRESS)
M68302FADS User's Manual
SUPPORT INFORMATION
(RamEn~==RAM_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==0)) "WEH~ mode. !ExpRamLCs~ (CS1~==CS1~_ACTIVE) (Address==EXP_RAM_ADDRESS) (RamEn~==RAM_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==1)) "WEH~ mode. !ExpRamHCs~ (CS1~==CS1~_ACTIVE) (Address==EXP_RAM_ADDRESS) (RamEn~==RAM_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==0)) "WEH~ mode. !FlashLCs~ (CS0~==CS0~_ACTIVE) (FlashEn~==FLASH_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==1)) "WEH~ mode. !FlashHCs~ (CS0~==CS0~_ACTIVE) (FlashEn~==FLASH_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==0)) "WEH~ mode. !EepromCs~ (CS2~==CS2~_ACTIVE) (Address==EEPROM_ADDRESS) (EepromEn~==EEPROM_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==1)) "WEH~ mode. !DuartCs~ (CS2~_DLY2==CS2~_ACTIVE) ((Address==DUART_ADDRESS) (DuartEn~==DUART_EN~_ACTIVE)) ((Address==ADI_ADDRESS) (AdiEn~==ADI_EN~_ACTIVE) (A3==1)) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==1)) "WEH~ mode. when (ChipType==IMP) then !AdiRd~ (CS2~==CS2~_ACTIVE)
M68302FADS User's Manual
SUPPORT INFORMATION
(Address==ADI_ADDRESS) (A3==0) (AdiEn~==ADI_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (OE~==READ) (WEL~==LDS~_ACTIVE) (WEH~==UDS~_ACTIVE) else !AdiRd~ (CS2~==CS2~_ACTIVE) (Address==ADI_ADDRESS) (A3==0) (AdiEn~==ADI_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (OE~==OE~_ACTIVE);
"OE~ R/W~ IMP. "WEL~ LDS~ IMP. "WEH~ UDS~ IMP.
when (ChipType==IMP) then !AdiWr~ (CS2~==CS2~_ACTIVE) (Address==ADI_ADDRESS) (A3==0) (AdiEn~==ADI_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (OE~==WRITE) "OE~ R/W~ IMP. (WEL~==LDS~_ACTIVE) "WEL~ LDS~ IMP. (BUSW==WORD) ((BUSW==BYTE) (WEH~==1)) "WEH~ mode. else !AdiWr~ (CS2~==CS2~_ACTIVE) (Address==ADI_ADDRESS) (A3==0) (AdiEn~==ADI_EN~_ACTIVE) (AS~==AS~_ACTIVE) (IAC==!IAC_ACTIVE) (WEL~==WEL~_ACTIVE) (BUSW==WORD) ((BUSW==BYTE) (WEH~==1)) "WEH~ mode. RAM, FLASH, EEPROM, read/write control. equations "************************* Read byte signal. "************************* when (ChipType==IMP) then !RdL~ (OE~==READ) "OE~ R/W~ IMP. (WEL~==LDS~_ACTIVE) "WEL~ LDS~/DS~ (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE); else !RdL~ (OE~==OE~_ACTIVE) (Rst~==!RST~_ACTIVE)
M68302FADS User's Manual
SUPPORT INFORMATION
(IAC==!IAC_ACTIVE); "************************** Read high byte signal. "************************** when (ChipType==IMP) then !RdH~ (OE~==READ) (WEH~==UDS~_ACTIVE) (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE); else !RdH~ (OE~==OE~_ACTIVE) (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE);
"OE~ R/W~ IMP. "WEH~ UDS~/A0
"************************** Write byte signal. "************************** when (ChipType==IMP) then !WrL~ (OE~==WRITE) "OE~ R/W~ IMP. (WEL~==LDS~_ACTIVE) "WEL~ LDS~/DS~ (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE) (EepromCs~==EEPROM_CS~_ACTIVE) else !WrL~ (WEL~==WEL~_ACTIVE) (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE) (EepromCs~==EEPROM_CS~_ACTIVE) "*************************** Write high byte signal. "*************************** when (ChipType==IMP) (BUSW==WORD) then !WrH~ (OE~==WRITE) "OE~ R/W~ IMP. (WEH~==UDS~_ACTIVE) "WEH~ UDS~ IMP. (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE); else when (ChipType==IMP) (BUSW==BYTE) then !WrH~ (OE~==WRITE) "OE~ R/W~ IMP. (WEL~==LDS~_ACTIVE) "LDS~ becomes mode. (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE); else when (ChipType!=IMP) (BUSW==WORD) then !WrH~ (WEH~==WEH~_ACTIVE) (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE); else !WrH~ (WEL~==WEL~_ACTIVE) "WEL~ becomes mode. (Rst~==!RST~_ACTIVE) (IAC==!IAC_ACTIVE);
M68302FADS User's Manual
SUPPORT INFORMATION
"*************************** R/W~ signal. "*************************** when (ChipType==IMP) then BR_W~ OE~; else BR_W~ !OE~; Dtack output. equations Dtack~.oe DtackOe; when ((CS1~==CS1~_ACTIVE) (RamEn~==RAM_EN~_ACTIVE)) ((CS2~==CS2~_ACTIVE) (((Address==EEPROM_ADDRESS) (EepromEn~==EEPROM_EN~_ACTIVE)) ((Address==ADI_ADDRESS) (AdiEn~==ADI_EN~_ACTIVE)))) then Dtack~ DTACK~_ACTIVE; else Dtack~ !DTACK~_ACTIVE; DtackOe !Dtack~.fb; Wait state counter. wait state with counter. equations WaitState.clk CLKO; WaitState.ar AS~; WaitState WaitState.fb External F.F. equations ExtNmiState.clk CLKO; ExtNmiState.ar !Rst~; state_diagram ExtNmiState state WAIT_FOR_NMI_RELEASE_STATE: ExtNmi~==EXT_NMI~_ACTIVE then WAIT_FOR_NMI_RELEASE_STATE else WAIT_FOR_NMI_INSERT_STATE; state WAIT_FOR_NMI_INSERT_STATE: ExtNmi~==EXT_NMI~_ACTIVE then NMI_ACTIVE_STATE else WAIT_FOR_NMI_INSERT_STATE;
M68302FADS User's Manual
SUPPORT INFORMATION
state NMI_ACTIVE_STATE: EXT_NMI_ACK_CYCLE then WAIT_FOR_NMI_RELEASE_STATE else NMI_ACTIVE_STATE; equations ExtNmiFlag reset. equations Rst~.oe !Rst~.fb; !Rst~ (ExtRst~==EXT_RST~_ACTIVE);
halt. equations Halt~.oe !Halt~.fb; !Halt~ (ExtRst~==EXT_RST~_ACTIVE);
Interrupt priority. equations IPL0~.oe !IPL0~.fb; IPL1~.oe !IPL0~.fb; "IPL0~, IPL1~ have same function. Only "functions available MACH block. IPL2~.oe !IPL2~.fb; when ExtNmiFlag (IntMode==NORMAL_INT_MODE) (ExtRst~==!EXT_RST~_ACTIVE) then IPL~ NORMAL_INT_LEVEL_7; else when ExtNmiFlag (IntMode==DEDICATED_INT_MODE) (ExtRst~==!EXT_RST~_ACTIVE) then IPL~ DEDICATED_INT_LEVEL_7; else IPL~ INT_LEVEL_0; External acknowledge. equations ExtNmiAck (IntLevel==EXT_NMI_INT_LEVEL) (Address==ADDR_INT_ACK_CYCLE) (AS~==AS~_ACTIVE)
M68302FADS User's Manual
SUPPORT INFORMATION
Auto vector signal. equations AVEC~.oe !AVEC~.fb; !AVEC~ EXT_NMI_ACK_CYCLE (ExtRst~==!EXT_RST~_ACTIVE); Test vectors ####### ###### #### ##### ##### #### ###### #### ###### #### ##### #### ##### #### ##### #### ##### ###### #### #### #### "test_vectors _302fmlyADS
M68302FADS User's Manual
SUPPORT INFORMATION
control logic
control logic. Controls interface side command converter. module _302ADIctrl title 'ADI control logic. Shlomo Reches Motorola semiconductor March 3rd, 1994.' Device declaration. device 'mach110a'; Pins declaration. AdiA2, AdiA1, AdiA0 "ADI address. AdsA2, AdsA1, AdsA0 "ADS board local address. AdsAll "ADS all. AdsBrk "ADS break. AdsRst "ADS reset. HostEn~ "Host enable. HostVcc "Host VCC. HostAck "Host acknowledge. HostReq "Host request. IntAck "Interrupt from host. AdsGrp "ADS group. (Not supported) AdsSel~ Rst~ HstBrkAck~ RstSwitch PcmciaRst~ PwrUpRst Nmi~ AbortSwitch ExtNmi~ HostRd~ "IMP interface, selected. "Reset IMP. "Reset host break external F.F. "Reset IMP, switch. "Reset from PCMCIA. "Reset from power circuit. "Common output processor. "User abort switch. "External source. "Enable data read host.
Constant declaration. .X., .Z.; .C., .D., .U.; HOST_VCC_ACTIVE HOST_EN~_ACTIVE
M68302FADS User's Manual
SUPPORT INFORMATION
HOST_ACK_ACTIVE HOST_REQ_ACTIVE ADS_ALL_ACTIVE ADS_BRK_ACTIVE ADS_RST_ACTIVE INT_ACK_ACTIVE RST_SWITCH_ACTIVE PCMCIA_RST~_ACTIVE PWR_UP_RST_ACTIVE RST~_ACTIVE BRK~_ACTIVE HOST_RD~_ACTIVE ADS_SEL~_ACTIVE HST_BRK_ACK~_ACTIVE EXT_NMI~_ACTIVE ABORT_SWITCH_ACTIVE
ADS_TO_HOST_DIRECTION HOST_TO_ADS_DIRECTION !ADS_TO_HOST_DIRECTION; AdsAddr [AdsA2, AdsA1, AdsA0]; AdiAddr [AdiA2, AdiA1, AdiA0]; Equations, state diagrams. ####### #### ##### #### #### ##### #### ###### ####### #### #### #### selected from ADI. equations !AdsSel~ (HostVcc==HOST_VCC_ACTIVE) (HostEn~==HOST_EN~_ACTIVE) (AdsAddr==AdiAddr) (AdsAll==ADS_ALL_ACTIVE) reset. equations !Rst~ (RstSwitch==RST_SWITCH_ACTIVE) (PwrUpRst==PWR_UP_RST_ACTIVE) (AdsRst==ADS_RST_ACTIVE) (AdsSel~==ADS_SEL~_ACTIVE)
M68302FADS User's Manual
SUPPORT INFORMATION
Host break ack. (Reset host break external F.F.) equations !HstBrkAck~ Rst~==RST~_ACTIVE (IntAck==INT_ACK_ACTIVE) (AdsSel~==ADS_SEL~_ACTIVE) PD0-PD7 buffer direction control signal. equations when (AdsSel~==ADS_SEL~_ACTIVE) (AdsAll==!ADS_ALL_ACTIVE) (HostReq==!HOST_REQ_ACTIVE) (HostAck==HOST_ACK_ACTIVE) then HostRd~ HOST_RD~_ACTIVE; else HostRd~ !HOST_RD~_ACTIVE; group. (Not supported) equations AdsGrp.oe Nmi~ equations !Nmi~ (AdsBrk==ADS_BRK_ACTIVE) (AdsSel~==ADS_SEL~_ACTIVE) (ExtNmi~==EXT_NMI~_ACTIVE); _302ADIctrl
M68302FADS User's Manual
D(0:15) A(1:23) FC(0:2) CS(0:3)
D(0:15) A(1:23) FC(0:2) CS(0:3)
MC68LC302EMU HALT BUSW DISCPU IPL(0:2)
FC(0) FC(1) FC(2)
CS(0) CS(1) CS(2) CS(3) DTACK br/ipl0/irq1 IPL(0) bgack/ipl1/irq6 IPL(1) bg/ipl2/irq7 IPL(2) AVEC AVEC RXD1/L1RXD RXD1 TXD1/L1TXD TXD1 RCLK1/L1CLK RCLK1 TCLK1 TCLK1/L1SY0/SDS1 cd1/L1SY1 cts1/L1GR CTS1 RTS1 rts1/L1RQ/GCIDCL RXD2/PA0 PA(0) TXD2/PA1 PA(1) RCLK2/PA2 PA(2) TCLK2/PA3 PA(3) cts2/PA4 PA(4) rts2/PA5 PA(5) cd2/PA6 PA(6) BRG2/SDS2/PA7 PA(7) SPRXD/PA8 PA(8) SPTXD/PA9 PA(9) SPCLK/PA10 PA(10) PA(12) MODCLK/PA12 PB3/TIN1 PB(3) PB5/TIN2 PB(5) PB6/tout2 PB(6) PB7/wdog PB(7) PB(8) PB(9) PB10 PB(10) PB(11) PB11 CLKO CLKO 1.5nF VCCSYN GNDSYN EXTAL EXTAL A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) A(16) A(17) A(18) A(19) D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) XTAL XTAL
RESET HALT uds/weh/A0 lds/ds/wel/we BUSW R/w/oe DISCPU/TEST cs0/iout2 DTACK PA(0:15) PB(0:11)
0.1uF
MOTOROLA INC.
PROJECT family
Shlomo Reches
SHEET
BLOCK
LC302
DESCRIP
AVEC CS(0) CS(1) CS(2) CS(3) DTACK FC(0) FC(1) FC(2) A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) A(16) A(17) A(18) A(19) A(20) A(21) A(22) A(23)
uds/A0 lds/ds avec/iout0 rmc/iout1 cs0/iout2 bgack bclr berr ipl0/irq1 ipl1/irq6 ipl2/irq7
MC68302RC RESET HALT BUSW DISCPU CS(0:3) DTACK IPL(0:2) RXD1/L1RXD TXD1/L1TXD RCLK1/L1CLK TCLK1/L1SY0/SDS1
cd1/L1SY1 cts1/L1GR rts1/L1RQ/GCIDCL
FC(0:2) A(1:23) D(0:15)
cts2/PA4 rts2/PA5 cd2/PA6
D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) EXTAL
XTAL left unconnected
BRG1 RXD2/PA0 TXD2/PA1 RCLK2/PA2 TCLK2/PA3 BRG2/SDS2/PA7 RXD3/PA8 TXD3/PA9 RCLK3/PA10 TCLK3/PA11 BRG3/PA12 EXTAL XTAL
dreq/PA13 dack/PA14 done/PA15 cts3/SPRXD rts3/SPTXD cd3/SPCLK PB0/iack7 PB1/iack6 PB2/iack1 PB4/tout1
PB3/TIN1
PB6/tout2 PB7/wdog
PB5/TIN2
PB10 PB11 CLKO
HALT BUSW DISCPU BGACK BCLR BERR IPL(0) IPL(1) IPL(2) RXD1 TXD1 RCLK1 TCLK1 CTS1 RTS1 BRG1 PA(0) PA(1) PA(2) PA(3) PA(4) PA(5) PA(6) PA(7) PA(8) PA(9) PA(10) PA(11) PA(12) PA(13) PA(14) PA(15) CTS3 RTS3 PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) PB(8) PB(9) PB(10) PB(11) PA(0:15) CLKO PB(0:11)
CLKO
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
DESCRIP
CS(0:3) CS(0) CS(1) CS(2) CS(3) DTACK AVEC FC(0:2) A(1:23) D(0:15) FC(0) FC(1) FC(2) A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15) A(16) A(17) A(18) A(19) A(20) A(21) A(22) A(23)
MC68PM302RC weh/uds/A0 wel/we/lds/ds oe/R/w cs0/iout2 DTACK AVEC RESET HALT BUSW/PCABUF DISCPU A20/PCD4 A21/PCD5 A22/PCD6 A23/PCD7
D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15) CLKO IPL(0:2) IPL(0) IPL(1) IPL(2) PA(0:15) PA(0) PA(1) PA(2) PA(3) PA(4) PA(5) PA(6) PA(7) PA(8) PA(9) PA(10) PA(11) PA(12) PA(13) PA(14) PA(15) PDI(8) PDI(9) PDI(10) PDI(11) PDI(12) PDI(13) PDI(14) PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) PB(8) PB(9) PB(10) PB(11) HALT BUSW DISCPU
CLKO
0.1uF EXTAL 1.5nF
VCCSYN GNDSYN EXTAL
XTAL
XTAL
ipl0/irq1/br ipl1/irq6/bgack ipl2/irq7/bg PA0/RXD2/PCD8 PA1/TXD2/PCD9 PA2/RCLK2/PCD10 PA3/TCLK2/PCD11 PA4/cts2/PCD12 PA5/rts2/PCD13 PA6/cd2/PCD14 PA7/BRG2/SDS2/PCD15 PA8/RXD3 PA9/TXD3 PA10/RCLK3 PA11/TCLK3 PA12/MODCLK0/BRG3 PA13/dreq/pciord PA14/dack/pciowr PA15/done/pcwe PDI8/PCA0 PDI9/PCA1 PDI10/PCA2 PDI11/PCA6 PDI12/PCA7 PDI13/PCA8 PDI14/PCA9 PB0/iack7/PCA11 PB1/iack1/pcce2 PB2/iack6/PCA25 PB3/TIN1 PB4/tout1/PCA10 PB5/TIN2/TRIS PB6/tout2/PCEN PB7/wdog PB9/ri PB10/dte PB11 RXD1/L1RXD TXD1/L1TXD RCLK1/L1CLK TCLK1/L1SY0/SDS1 cd1/L1SY1 cts1/L1GR rts1/L1RQ/GCIDCL cd3/SPCLK rts3/SPTXD cts3/SPRXD PCD0 FC0/PCD1 FC1/PCD2 FC2/PCD3 frz/PCA5 lds/ds/pcce1 uds/A0/pcreg rw/PCRDY/pcireq berr/PCA3 avec/PCA4 bg/pcwait br/pcstschg bgack/pcoe
PDI(0:15) PB(0:11) RXD1 TXD1 RCLK1 TCLK1 CTS1 RTS1 RTS3 CTS3 PCD0 PCD1 PCD2 PCD3 PCA5 PCCE1 PCREG PCRDY PCA3 PCA4 PCWAIT PCSTSCHG PCOE
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
Pchip
DESCRIP
74ACT74
10pF
0.1uF External clock termination
50MHz Mounted socket
EXTAL
EXTAL
CLKO 0.1uF
Clock termination
25MHz
470K XTAL
10pF
Parts dashed box, option should mounted board.
MOTOROLA INC.
PROJECT family
Shlomo Reches
SHEET
BLOCK
Clock circuit
DESCRIP
PCMCIA reset duration extender.
PWR5V
4.7K 4.7K
Reset debouncer.
Power indicator
RSTSW PCRST
74ACT00 74ACT14_PWR
4.7K
RX/CX 74HC4538_PWR
0.1uF
(GREEN)
PCRST
(YELLOW)
74ACT00
100K
74ACT08
4.7K
100K
(RED)
74ACT08
HALT
4.7K 4.7K
Abort debouncer
74ACT00
ABORTSW
PWR5V
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
(ORANGE)
power control indicator.
74ACT14_PWR
PB(6) PCVCCEN RAMEN FLSHEN EEPRMEN ADIEN DUARTEN ADSA0 ADSA1 ADSA2
74ACT00
Power reset
1N4148
PWR5V
(PCEN)
PCVCCEN
PWRUPRST
47uF
74ACT14_PWR
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
IOIS16 PA(12) BUSW BUSWDIP
(MODCLK)
CHIPTYP
MOTOROLA INC.
PROJECT family
Shlomo Reches
SHEET
BLOCK
User other controls.
DESCRIP
MACH220
CLKO BUSWDIP EXTRST I0/CLK0 I1/CLK1 I4/CLK2 I5/CLK3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 BRDH FLHCS CS(0) FLLCS BWRL BRDL UARTCS ORMLCS ORMHCS RMHCS RMLCS EPRCS ADSRD ADSWR CS(1) FC(2) FC(1) FC(0) BR_W I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47
BUSH BUSL2H BUSL BWRH DTACK IPL(1) A(19) IPL(0) IPL(2) A(18) A(1) ADIEN NR_DE A(2) AVEC CS(2) A(17) A(16) CHIPTYP A(3) FLSHEN RAMEN EEPRMEN EEPWREN DUARTEN HALT
U18-59
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
control logic.
DESCRIP
PWRUPRST EXTNMI ADSBRK HSTVCC ABORTSW HSTEN I2/CLK0 I5/CLK1 ADSALL ADSA0 ADSA1 EXTRST
U3-7 U3-8
MACH110 I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 ADIA2 HSTRD PCRST ADSGRP ADSSEL ADSRST
U3-18
ADSA2 ADIA0
U3-15 U3-16
ADIA1
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11
HSTACK HSTREQ INTACK BRKCLR RSTSW
U3-42 U3-43 U3-39 U3-37 U3-30 U3-31
U3-27 U3-26
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
control logic.
DESCRIP
D(0:15) BD(0) BD(1) BD(2) BD(3) BD(4) BD(5) BD(6) BD(7)
74ACT245 74ACT245
D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7) BD(8) BD(9) BD(10) BD(11) BD(12) BD(13) BD(14) BD(15)
D(0) D(1) D(2) D(3) D(4) D(5) D(6) D(7)
BD(8) BD(9) BD(10) BD(11) BD(12) BD(13) BD(14) BD(15)
D(8) D(9) D(10) D(11) D(12) D(13) D(14) D(15)
74ACT245
BD(0:15)
BR_W BUSL BUSL2H BUSH
A(1:23)
A(1) A(2) A(3) A(4) A(5) A(6) A(7)
BA(1:23)
BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7)
A(8) A(9) A(10) A(11) A(12) A(13) A(14) A(15)
74ACT244
BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15)
A(16) A(17) A(18) A(19)
74ACT244
BA(16) BA(17) BA(18) BA(19)
74ACT244
MOTOROLA INC.
PROJECT family
Shlomo Reches
SHEET
BLOCK
Buffers
DESCRIP
BA(1:23) BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15) BA(16) BA(17) BA(18) BD(0:15)
MCM6229A
BD(0) BD(1) BD(2) BD(3) BD(4) BD(5) BD(6) BD(7) BD(8) BD(9) BD(10) BD(11) BD(12) BD(13) BD(14) BD(15) BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15) BA(16) BA(17) BA(18)
MCM6229A
BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15) BA(16) BA(17) BA(18)
MCM6229A
BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15) BA(16) BA(17) BA(18)
MCM6229A
BA(19) BA(18) BA(17) BA(16) BA(15) BA(14) BA(13) BA(12) BA(11) BA(10) BA(9) BA(8) BA(7) BA(6) BA(5) BA(4) BA(3) BA(2) BA(1)
29F040
BRDL BRDH BWRL BWRH RMLCS RMHCS FLLCS FLHCS EPRCS BD(0:15)
BD(7) BD(6) BD(5) BD(4) BD(3) BD(2) BD(1) BD(0)
BA(19) BA(18) BA(17) BA(16) BA(15) BA(14) BA(13) BA(12) BA(11) BA(10) BA(9) BA(8) BA(7) BA(6) BA(5) BA(4) BA(3) BA(2) BA(1)
29F040
AT28C16PGA
BD(15) BD(14) BD(13) BD(12) BD(11) BD(10) BD(9) BD(8)
BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11)
BD(0) BD(1) BD(2) BD(3) BD(4) BD(5) BD(6) BD(7)
EPRCS BRDL BWRL
BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15) BA(16) BA(17) BA(18)
BA(1:23)
BRDL BRDH BWRL BWRH ORMLCS ORMHCS
BD(0) BD(1) BD(2) BD(3) BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15) BA(16) BA(17) BA(18)
MCM6229A
MCM6229A
BD(4) BD(5) BD(6) BD(7)
BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15) BA(16) BA(17) BA(18)
MCM6229A
BD(8) BD(9) BD(10) BD(11)
BA(1) BA(2) BA(3) BA(4) BA(5) BA(6) BA(7) BA(8) BA(9) BA(10) BA(11) BA(12) BA(13) BA(14) BA(15) BA(16) BA(17) BA(18)
MCM6229A
BD(12) BD(13) BD(14) BD(15)
MOTOROLA INC.
256K word option
PROJECT
family Shlomo Reches
SHEET
BLOCK
Memory block
DESCRIP
INTACK HSTACK HSTACK HSTACK HSTACK ADSALL BADSALL BADSRST BADIA2 BADIA1 BADIA0
ADSGRP INTACK ADSGRP HSTACK HSTACK ADSALL ADSRST ADIA2 ADIA1 ADIA0
74LS244
BADSGRP BHSTACK
BINTACK
BADSGRP
BINTACK
ADSRST ADIA2 ADIA1 ADIA0
BHSTACK
BADSALL
BADSRST
ADSREQ
ADSSEL
ADSACK ADSINT
ADSACK ADSINT
ADSREQ
LS244_4
BADIA2 BADIA1
BHSTVCC
HSTREQ
LS244_4
HSTVCC HSTEN ADSBRK ADSBRK
4.7K
BHSTREQ
BHSTEN BHSTEN BADSBRK
BD(0) BD(1) BD(2) BD(3) BD(4) BD(5) BD(6) BD(7)
BHSTVCC
HSTBRK
BADIA0 BHSTVCC BHSTREQ BHSTVCC BHSTVCC BHSTVCC BADSREQ BHSTVCC BADSACK BHSTEN BHSTEN BHSTEN BHSTEN BADSINT
BD(8) BD(9) BD(10) BD(11) BD(12) BD(13) BD(14) BD(15)
ADSSEL ADSBRK HSTREQ HSTACK INTACK
OEBA LEBA 74F543
OEAB LEAB
BADSBRK
BPD0 BPD1 BPD2 BPD3 BPD4 BPD5 BPD6 BPD7
74ACT244
ADSRD ADSWR HSTRD
PWR5V
BD(0:15)
BD(9) (HSTBRK)
ADSWR BRKCLR
74LS05_PWR 74ACT74
HSTBRK
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
port interface
DESCRIP
PB(11) DTACK (PB11 parallel with interrupt capability)
BA(1:23) BD(0) BD(1) BD(2) BD(3) BD(4) BD(5) BD(6) BD(7)
BA(1) BA(2) BA(3) BA(4) 10uF
MC68681FN DTACK
10uF
MC145407
10uF
Terminal port (DTE)
10uF
BD(0:7) BR_W UARTCS
TxDA RxDA TxDB RxDB X1/CLK RESET IACK
15pF
3.6864MHz
HSTACK HSTREQ HSTEN INTACK
10uF 10uF
MC145407
ADSACK EEPWREN ADSINT ADSREQ NR_DE
10uF
Host port (DCE)
10uF
4.7pF
ADSACK EEPWREN ADSINT ADSREQ NR_DE
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
Serial ports
DESCRIP
PDI(0:15)
PCVCC A(20) A(22) PCCE1 PCOE PDI(14) PA(15) (PCD4) (PCD6) (PCCE1) (PCOE) (PCA9) (PCA13) (PCWE) `VCC (PCA16) (PCA12) (PCA6) (PCA4) (PCA2) (PCA0) (PCD1) (IOIS16) (PCD11) (PCD13) (PCD15) (PCRFRSH) (PCIOWR) (PCA18) (PCA20) (PCA22) (PCA24) (PCWAIT) (PCREG) (PCSTSCHG) (PCD9) (PCCD2) PDI(11) PCA4 PDI(10) PDI(8) PCD1 IOIS16 PA(3) PA(5) PA(7) PA(14) PCWAIT PCREG PCSTSCHG PA(1) PCVCC
A(1:23) PB(0:11)
10uF
(PCD3) (PCD5) (PCD7) (PCA10) (PCA11) (PCA8) (PCA14) (PCRDY) (PCVPP1) (PCA15) (PCA7) (PCA5) (PCA3) (PCA1) (PCD0) (PCD2) (PCCD1) (PCD12) (PCD14) (PCCE2) (PCIORD) (PCA17) (PCA19) (PCA21) (PCVPP2) (PCA23) (PCA25) (PCRST) (PCIPACK) (PCSPKR) (PCD8) (PCD10)
PCD3 A(21) A(23) PB(4) PB(0) PDI(13) PCRDY
PDI(12) PCA5 PCA3 PDI(9) PCD0 PCD2
PA(4) PA(6) PB(1) PA(13)
4.7K
4.7K
4.7K
PCIPCK
74ACT08
PB(2) PCRST
PA(0) PA(2)
PA(0:15)
MOTOROLA INC.
PROJECT family
Shlomo Reches
SHEET
BLOCK
PCMCIA connector
DESCRIP
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1N4148 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 220uF/25V 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
PCVCCEN
PWR5V
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
74LS05_PWR
74ACT00_PWR 74LS05_PWR 74LS05_PWR
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
RX/CX 74HC4538_PWR
RLY1
PCVCC
74ACT14_PWR
0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
0.1uF
470K
1SMC50AT3
MBRD620CT
supply Pchip PCMCIA block
VCCPC
0.1uF
Ground hooks
from PCMCIA connector
PCVCC
MOTOROLA INC.
PROJECT family
Shlomo Reches
SHEET
BLOCK
Power input
DESCRIP
D(14) D(12) D(10) D(8) D(6) D(4) D(2) D(0) D(0:15) A(1:23) D(15) D(13) D(11) D(9) D(7) D(5) D(3) D(1)
A(14) A(12) A(10) A(8) A(6) A(4) A(2) A(0)
A(15) A(13) A(11) A(9) A(7) A(5) A(3) A(1)
FC(0:2) BGACK
(R/W) FC(2) FC(0) A(22) A(20) A(18) A(16)
A(1:23)
BGACK FC(1) A(23) A(21) A(19) A(17)
CLKO BERR HALT
CLKO CS(2) BERR HALT CS(1) IPL(1)
CS(3) AVEC DTACK IPL(2) IPL(0) CS(0)
AVEC DTACK
CS(0:3) IPL(0:2)
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
Logic analyzer connectors.
DESCRIP
PB(0:11)
PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) PB(8) PB(9) PB(10) PB(11) PCA3 PCA4 PCA5 PCRDY PCOE PCCE1 PCREG PCWAIT PCSTSCHG PDI(8) PDI(9) PDI(10) PDI(11) PDI(12) PDI(13) PDI(14) PCD0 PCD1 PCD2 PCD3 RXD1 TXD1 CTS1 RTS1
PDI(0:15) PA(0:15)
PA(0) PA(1) PA(2) PA(3) PA(4) PA(5) PA(6) PA(7) PA(8) PA(9) PA(10) PA(11) PA(12) PA(13) PA(14) PA(15) BRG1 RCLK1 TCLK1 CTS3 RTS3
MOTOROLA INC.
PROJECT family
Shlomo Reches
SHEET
BLOCK
Logic analyzer expansion connector
DESCRIP
EXTNMI PCD0 PCD1 PCD2 PCD3 PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) PB(8) PB(9) PB(10) PB(11) PCA3 PCA4 PCA5 PCRDY PCOE PCCE1 PCREG PCWAIT PCSTSCHG BCLR DISCPU PDI(8) PDI(9) PDI(10) PDI(11) PDI(12) PDI(13) PDI(14) RXD1 TXD1 CTS1 RTS1
PB(0:11) PDI(0:15) PA(0:15)
PA(0) PA(1) PA(2) PA(3) PA(4) PA(5) PA(6) PA(7) PA(8) PA(9) PA(10) PA(11) PA(12) PA(13) PA(14) PA(15) BRG1 RCLK1 TCLK1 CTS3 RTS3
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
Expansion connector
DESCRIP
A(1) A(2) A(5) A(10) A(15) A(12) A(17) A(22) FC(0) CS(0) PB(11) PB(10) PB(2) PB(8) PB(4) D(10) D(13) D(9) D(2) AVEC IPL(0) EXTAL PA(12) D(3) BUSW PB(1) FC(1) D(14) D(11) (R/W) D(6) DTACK BERR IPL(1) IPL(2) PA(15) BGACK PA(13) A(7) A(4) A(9) A(14) A(19) A(16) A(21) FC(2) CS(3) PB(3)
A(1:23) FC(0:2) CS(0:3) PB(0:11)
A(3) A(6) A(11) A(8) A(13) A(18) A(23) A(20) CS(1) CS(2) PB(6) PB(5) PB(7) PB(9) PB(0) D(15) D(12) D(8) D(7) D(1) CLKO D(5) BCLR D(4) D(0) HALT PA(14)
D(0:15) IPL(0:2) PA(0:15)
MOTOROLA INC.
PROJECT family
Shlomo Reches
SHEET
BLOCK
Expansion connector
DESCRIP
DISCPU
PWR5V
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
74ACT14_PWR
SPARE
74ACT14_PWR
AVEC BERR HALT BGACK DTACK CTS3 PB(11) PB(5) state control signal (TRIS), Pchip.
74ACT00_PWR 74ACT00_PWR
22V10A CK/I1 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
PB(0:11)
TCLK1 RCLK1 RXD1 EXTNMI BCLR CTS1 IPL(0) IPL(1) IPL(2) IPL(0:2)
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
74ACT00_PWR
SPARE
PCA3 BERR
74LS05_PWR
PA(7) (BOOT)
74LS05_PWR
22V10A CK/I1 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
74ACT08
MOTOROLA INC.
PROJECT
family Shlomo Reches
SHEET
BLOCK
PullUps spare gates.
DESCRIP
MOTOROLA
1995
M68302 FADS Addendum CPU32BUG Debug Monitor User's Manual:
Overview
following addendum CPU32BUG Debug Monitor User's Manual. CPU32Bug debugger (V0.4) M68302 Family Application Development System almost compatible with M68CPU32BUG Debug Monitor. CPU32BUG Debug Monitor User's Manual primary documentation. version CPU32Bug that runs M68302 FADS board referred FADSbug. CPU32Bug FADSbug sometimes used abbreviations refer debugger that runs M68302 FADS board. NOTE: debugger prompt M68302FADS board will indicate which part plugged into board: LCIMPbug> used MC68LC302 PCHIPbug> used MC68PM302 ENIMPbug> used MC68EN302 IMPbug> used MC68302. NOTE: FADSbug debugger uses locations through 0x8000. should always start programs DRAM from address 0x8000.
Changes FADSbug
There some enhancements some changes FADSbug software brief summary included below. 1.2.1 Features that M68CPU32Bug currently FADSbug version running M68302 FADS board
1.2.1.1
Switch Directories feature included with FADSbug version running M68302 FADS board. 1.2.1.2 PA/NOPA:
Printer Attach/Detach feature included with FADSbug version running M68302 FADS board.
1.2.1.3
Port Format feature included with FADSbug version running M68302 FADS board.
1.2.1.4
Transparent Mode feature included with FADSbug version running M68302 FADS board.
page
Addendum CPU32Bug Debug Monitor User's Manual
MOTOROLA
1995
1.3.1
Enhancements CPU32Bug (FADSbug) running MC68360FADS board HELP Command:
enhancement consists adding syntax each individual help. example: Temporary Breakpoint <ADDR> [:<COUNT>] syntax taken from Manual. This enhancement displayed when full list help commands requested i.e., when type: 1.3.2 Macro Expansion Listing Status (MALS):
This allows user interrogate whether debugger Macro Expansion currently (the output OFF). Remember that NOMAL set/reset macro expansion. 1.3.3 Command
This menu driven direct interface registers MC68XX302 Family Peripherals. 1.3.3.1 Exit
board exits user-interface module enters FADSbug monitor/debugger. 1.3.3.2 Flip
When highlighted sign appears), chosen structures read then written; set, structures just read. 1.3.3.3
transmit tables displayed concise format.
1.3.3.4
transmit tables displayed concise format. 1.3.3.5 General Purpose
registers general purpose displayed. These mode register, status register, source destination addresses, count registers.
page
Addendum CPU32Bug Debug Monitor User's Manual
MOTOROLA
1995
1.3.3.6
Chip Select
registers chip select block displayed. These base option registers each four chip select areas.The debugger gives felixibility write registers chip selects(CS) careful write area want change. example, modify CS0, CS!, CS2, however suggested that modify these chip selects FADS board because these chip selects used decode memory FADS board. 1.3.3.7 Parallel
registers parallel block displayed. These control, direction data registers both parallel port Pchipbug only). 1.3.3.8 Interrupt Controller
registers interrupt controller block displayed. These interrupt mode, pending, in-service mask registers. 1.3.3.9 Timers
registers timer block displayed. They mode, status, reference, capture count registers timers reference count registers watchdog timer. 1.3.3.10 SCC1 registers
This option displays registers associated with channel These channel's configuration, mode, sync, event, mask, status registers 1.3.3.11 SCC2 registers
This option displays registers associated with channel These channel's configuration, mode, sync, event, mask, status registers 1.3.3.12 SCC3 registers (Pchipbug ONLY)
This option displays registers associated with channel These channel's configuration, mode, sync, event, mask, status registers 1.3.3.13 PCMCIA registers (Pchipbug ONLY)
This option displays registers associated with PCMCIA interface. 1.3.3.14 PCMCIA CARD registers (Pchipbug ONLY)
This option displays registers associated with PCMCIA Card Configuration interface. 1.3.3.15 16550 registers (Pchipbug ONLY)
This option displays registers associated with 16550 emulation. 1.3.3.16 MC68XX302 Commands
This option used writing commands directly command register MC68XX302. entering '?', help screen containing defined commands displayed; this screen scrolled desired command selected from this menu.
page
Addendum CPU32Bug Debug Monitor User's Manual
MOTOROLA
1995
1.3.3.17
block
This option displays data structures associated with (Serial Communications Port). 1.3.3.18 block
This option displays data structures associated with (Serial Management Controller). 1.3.3.19 Serial interface
This option displays data structures associated with serial interface block. 1.3.3.20 DRAM Refresh
This option displays parameters associated with this block. Note that they overlaid last buffer descriptors SCC2 Transmit Table. wish DRAM Refresh Controller, must only BD's this table 1.3.4 Symbols:
user define (currently symbols which equated values expressions, following manner: [<symbol>] [<expression>] NOSYM [<symbol>] Options: displays defined symbols their value both hexadecimal decimal). <symbol> displays symbol value. <symbol> <expression> evaluates expression gives value symbol. Usage: symbols used debugger's command level with in-line assembler. symbol name limited characters length. Example: FADSbug> DPRBASE 20000 FADSbug> REGBASE DPRBASE+1000 FADSbug> PEPAR REGBASE+16 FADSbug> PEPAR FADSbug> 410;di 00000410 1000 move.b d0,d0 move.l #pepar, FADSbug>md 410:1 00000410 203c0002 1016 MOVE.L #$21016,D0
page
Addendum CPU32Bug Debug Monitor User's Manual
MOTOROLA
1995
1.3.5
Reprogramming Flash EPROMS:
There command added that enables users reprogram flash EPROMs FADS board. command called LOF. Syntax: "LOF <range> <addr>[;B|W|L]" command loads from memory addresses defined <range> another place flash memory, beginning <addr>. option field only allowed when <range> specified using count. this case, defines size data which count referring. example, count four with option would mean load four long words bytes) from DRAM <addr> location flash. range beginning address greater than address error results. error also results option field specified without count range. order erase program flash needed. applied board error results. Example: Suppose want load your program flash starting address (0x200000). program length about 0x20000 bytes. program must linked address 0x200000. next step load that program DRAM. There ways parallel port (pdl) serial port. (lo) Since program linked 0x200000 must command (serial load) command parallel load) with their offset option load address DRAM. example with parallel load command executed psrec -sub 1F0000 program.srx last step type command. example program loaded 0x10000(DRAM address) then starting address location program 0x200000, ending address would approximately 0x220000. starting address flash memory 200000, command 10000 30000 200000 1.4.1
Changes CPU32Bug running M68360FADS board
Macros:
user define macros chars each, instead unlimited number macros when total number characters only chars.
page
Addendum CPU32Bug Debug Monitor User's Manual
MOTOROLA
1995
1.4.2
Addressing Modes:
There have been some minor changes assembler addressing modes format. following addressing modes An+Xn+bd represented CPU32Bug following syntaxes: (bd,An,Xi) (addr,PC,Xi) bd(An,Xi) addr(PC,Xi) CPU32Bug running M68360FADS board (FADSbug), only second syntax acceptable. CPU32Bug running M68360FADS board also allows skip omit entries with following addressing modes: Address register indirect with index, base displacement. Program counter indirect with index, base displacement. M68CPU32BUG does not.
Differences between 302bug CPU32bug compliant debuggers:
TRAP routines different fromthe 302bug debuggers (LCIMPbug, PCHIPbug, IMPbug, ENIMPbug). TRAP handler which allows system calls from user programs different format than 302bug. Refer chapter System Calls CPU32 Debug Monitor User's Manual details format TRAP command user program.
Chip Selects Registers
debugger gives felixibility write registers chip selects(CS) careful write area want change. example, modify CS0, CS!, CS2, however suggested that modify these chip selects FADS board because these chip selects used decode memory FADS board.
page
Addendum CPU32Bug Debug Monitor User's Manual
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