2814.4 Binary Correlator Intersil HSP45256 high-speed, binar
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HSP45256
2814.4
Binary Correlator
Intersil HSP45256 high-speed, binary correlator. configured perform one-dimensional two-dimensional correlations selectable data precision length. Multiple HSP45256's cascaded increased correlation length. Unused taps masked reduced correlation length. correlation array consists eight 32-tap stages. These cascaded internally compare 8-bit input data with 1-bit reference. Depending number bits input data, length correlation 256, 128, taps. HSP45256 also configured separate correlators with window sizes from each. mask register used prevent subset bits from contributing correlation score. output correlation array (correlation score) feeds weight logic, which gives added flexibility data format. addition, offset register provided that preprogrammed value added correlation score. This result then passed through user programmable delay stage cascade summer. delay stage simplifies cascading multiple correlators compensating latency previous correlators. Binary Correlator configured writing control registers standard microprocessor interface. simplify operation, both control reference registers double buffered. This allows user load mask reference data while current correlation progress.
Features
Reconfigurable Stage Binary Correlator 1-Bit Reference 8-Bit Data Separate Control Reference Interfaces 25.6, 33MHz Versions Configurable Operation Double Buffered Mask Reference Programmable Output Delay Cascadable Standard Microprocessor Interface
Applications
Radar/Sonar Spread Spectrum Communications Pattern/Character Recognition Error Correction Coding
Ordering Information
PART NUMBER HSP45256JC-25 HSP45256JC-33 HSP45256GC-25 HSP45256GC-33 HSP45256JI-25 HSP45256JI-33 TEMP. RANGE (oC) PACKAGE PLCC PLCC PLCC PLCC PKG. N84.1.15 N84.1.15 G85.A G85.A N84.1.15 N84.1.15
Block Diagram
DOUT DOUT0-7 DIN0-7 DREF0-7 CORRELATION ARRAY DREFOUT CSCORE WEIGHT AUXOUT0-8
DCONT0-7 CONTROL A0-2 DELAY CASCADE SUMMER CASOUT0-12
CASIN0-12
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
HSP45256 Pinouts
BOTTOM VIEW
DREF0 DREF2 DREF3 DREF5 DIN0 DREF6 DIN4 DIN7 CASIN CASIN CASIN CASIN CASIN CASIN CASOUT CASOUT CASOUT CASOUT CASIN1 CASIN3 CASIN6 CASIN CASOUT CASOUT CASOUT CASOUT CASOUT CASOUT CASIN0 INDEX CASIN CASIN CASOUT CASOUT CASOUT DIN5 DIN6 DOUT0 DOUT1 DOUT2 DIN3 DIN2 DOUT4 DOUT7 DOUT3 DREF7 DIN1 DOUT6 DOUT5 DREF4 AUXOUT AUXOUT DREF1 DCONT DCONT OUT2 RLOAD CLOAD DCONT DCONT OUT6 OUT4 OUT3 TXFR DCONT7 DCONT1 DCONT3 DCONT0 OUT8 OUT7 OUT5
VIEW
CASIN CASIN CASIN CASIN DIN5 DIN6 DOUT0 DOUT CASIN CASIN INDEX CASIN CASIN CASIN CASIN CASIN CASIN OUT2 CASIN OUT1 OUT3 OUT4 OUT5 OUT6 OUT7 OUT9 OUT8 OUT10 OUT11 OUT12 DOUT2 DOUT DOUT OUT0 OUT2 OUT3 OUT5
DIN7
DIN4 DREF DIN0 DREF DREF DREF DREF
DOUT DOUT DOUT OUT1
DIN3 DREF DREF DREF
DIN2
DIN1
LOAD TXFR LOAD
DCONT DCONT
DCONT DCONT OUT6 OUT8
OUT4 OUT7
DCONT DCONT
DCONT DCONT
HSP45256 Pinouts
(Continued) PLCC VIEW
CASIN2 CASIN3 CASIN4 CASIN5 CASIN6 CASIN7 CASIN8 CASIN9 CASIN10 CASIN11 CASIN12 OEC# CASOUT0 CASOUT1 CASOUT2 CASOUT3 CASOUT4 CASOUT5 CASOUT6 CASOUT7 CASIN1 CASIN0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 DREF7 DREF6 DREF5 DREF4 DREF3 DREF2 DREF1 DREF0 RLOAD TXFR CLOAD DCONT7 DCONT6 DCONT5 DCONT4 DCONT3 DCONT2 DCONT1 DCONT0 AUXOUT8 AUXOUT7 AUXOUT6 AUXOUT5 CASOUT8 CASOUT9 CASOUT10 CASOUT11 CASOUT12 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 AUXOUT0 AUXOUT1 AUXOUT2 AUXOUT3 AUXOUT4
HSP45256 Descriptions
SYMBOL DIN0-7 PLCC NUMBER 17-24 TYPE power supply pin. Ground. DIN0-7 consists eight single data input pins. assignment active pins determined configuration. Data loaded synchronous rising edge CLK. DIN0 LSB. DOUT0-7 data output correlation array. format output dependent window configuration weighting. DOUT0 LSB. System Clock. Positive edge triggered. CASIN0-12 allows multiple correlators cascaded connecting CASOUT0-12 correlator CASIN0-12 another. CASIN added internally correlation score form CASOUT. CASIN0 LSB. CASOUT0-12 output correlation score. This value delayed taps chip CASIN0-12. When part configured independent correlators, CASOUT0-8 represents correlation score first correlator while second correlation score available AUXOUT0-8 bus. this configuration, cascading feature longer option. CASOUT0 LSB. output enable CASOUT0-12. When high, output three-stated. Processing interrupted this (active low). TXFR synchronous clock enable signal that allows loading reference mask inputs from preload register correlation array. Data transferred rising edge while TXFR (active low). DREF0-7 8-bit wide data reference input. This input data used load reference data. RLOAD going active initiates loading reference registers. This input used load reference registers correlation array. manner which reference data loaded determined window configuration. window configuration 256, reference bits loaded time over DREF7. When HSP45256 configured array, data loaded into stages parallel. this case, DREF7 reference data first stage DREF0 reference data eighth stage. contents reference data registers affected changing window configuration. DREF0 LSB. RLOAD enables loading reference registers. Data DREF0-7 loaded into preload registers rising edge RLOAD. This data transferred into correlation array TXFR (active low). DCONT0-7 control data input which used load mask each tap, well configuration registers. mask data sequentially loaded into eight stages same manner reference data. DCONT0 LSB. CLOAD enables loading data DCONT0-7. destination this data controlled A0-2 (active low). A0-2 3-bit address that determines what function will performed when CLOAD active. This address with respect rising edge load signal, CLOAD. LSB. AUXOUT0-8 9-bit that provides either data reference output single correlation configuration 9-bit correlation score second correlator, dual correlator configuration. When user programs chip separate correlators, score second correlator output this bus. When user programmed chip correlator, AUXOUT0-7 represents reference data out, with state AUXOUT8 undefined. AUXOUT0 LSB. signal output enable AUXOUT0-8 output. When high, output disabled. Processing interrupted this (active low). DESCRIPTION
DOUT0-7 CASIN0-12
60-62, 64-68 1-13
CASOUT0-12
71-76, 78-83
TXFR
DREF0-7
25-32
RLOAD
DCONT0-7
41-48
CLOAD A0-2
38-40
AUXOUT0-8
50-54, 56-59
HSP45256 Block Diagram
CONFIG OFFAL A(2:0) DECODE CLOAD OFFAM DELAY OFFBL OFFBM MASK DCONT(7:0) RLOAD TXFR DIN7 CORRELATOR STAGE DATA (000) (001) CONFIG(4:0)
DREF7
CORRELATION SCORE
DIN6 CORRELATOR STAGE CONFIG(4:0) DATA
DREF6
DIN0
CORRELATOR STAGE CONFIG(4:0)
DREF0
ARRAY
REFERENCE
CASIN(12:0)
CASIN(12:0) DOUT(7:0)
NOTE: registers clocked with unless otherwise specified. CORRELATOR BLOCK DIAGRAM
HSP45256 Block Diagram
(Continued)
OFFSET REGISTER OFFAM OFFAL OFFBM OFFBL DELAY
(010)
(011)
(101)
(110)
CONFIG(4:0)
OFFSET REGISTER
CORRELATION SCORE
DELAY WEIGHT PROGRAMMABLE DELAY (100) CASOUT(12:0)
RO(0-7) REFERENCE RLOAD
CONFIG(4:0)
AUXOUT(8:0)
CASCADE REGISTER
CASIN(12:0) DOUT(7:0)
DOUT(7:0)
NOTE: registers clocked with unless otherwise specified.
HSP45256 Functional Description
correlation array consists eight 32-bit stages. first stage receives data directly from input DIN7. other seven stages receive input data from either external data pin, DIN0-6, from Shift Register output previous stage, determined Configuration Register. When part configured single correlator correlation score, Offset Register cascade input appears CASOUT0-12. Delayed versions data reference inputs appear DOUT0-7 AUXOUT0-7, respectively. input output multiplexers correlation array controlled together; example, correlation, input data loaded into DIN7 output appears DOUT7. configuration data bits, length correlation (and two-dimensional data, number rows), commonly called correlation window. level Block Diagram single correlator configuration shown Figure Compare single correlator configuration data output correlation output level Block Diagram dual correlator configuration shown Figure
DIN(7:0) DREF(7:0) 32-BIT CORRELATORS CORR SCORE AUXOUT(7:0) DELAY 0000 OFFA DOUT(7:0) CORR
Correlator Array
core HSP45256 correlation array, which consists eight 32-tap stages. single correlator cell consists XNOR gate individual comparison; i.e., data reference bits either both high both low, output correlator cell high. Figure details circuitry single correlation cell Figure shows timing that single correlation cell. addition, latches, reference control data path contained this cell. These latches loaded from Preload Registers rising edge when TXFR that reference mask values updated without interrupting data processing. mask function implemented with gate. When mask logic low, corresponding correlator cell output low.
DIN(7:4) DREF(7:4) DOUT(7:4)
32-BIT CORRELATORS SCORE
WEIGHT
OFFA
WEIGHT
DELAY
CASIN(12:0)
CORRELATOR
CASOUT(8:0)
CASIN(12:0)
CASOUT(12:0)
DIN(3:0) DREF(3:0)
32-BIT CORRELATOR CORR SCORE
DOUT (3:0)
FIGURE SINGLE CORRELATOR CONFIGURATION
OFFB
WEIGHT
AUXOUT(8:0) CORRELATOR
FIGURE DUAL CORRELATOR CONFIGURATION
HSP45256
function performed correlation cell (Di,n XNOR Ri,n) Mi,n where: Di,n data register Ri,n reference register Mi,n mask register reference mask bits loaded sequentially, bits time, where depends current configuration (see Tables reference data loaded rising edge RLOAD mask data loaded rising edge CLOAD. mask reference bits stored internally Shift Registers, that mask reference information that loaded most recently will used process newest data. When information loaded previous contents mask reference bits shifted over sample, oldest information lost. There registers multiplexer array (see Block Diagram), data DOUT0-7 corresponds data last element correlation array. When monitoring DOUT0-7, AUXOUT0-8, REFOUT0-7, only those bits listed Table valid.
DREF RLOAD DCONT (MASK) CLOAD
DREFOUT
DCONTOUT
TXFR DATA
DATAOUT
COROUT
FIGURE CORRELATION CELL BLOCK DIAGRAM
DCONT CLOAD
DATA CONTROL
DREF RLOAD
TXFR DR-1
DATA
FIGURE CORRELATION CELL TIMING DIAGRAM
HSP45256 Weight Logic
Weight Logic provides weighting final correlator score from eight stages correlation array. configuration, outputs each stages given weight then added together. (8-bit data) configuration, output each stage will shifted that output data represents 8-bit word, with stage seven being MSB. 13-bit Offset Register loaded from control data bus. output added correlation score obtained from correlator array. This then goes programmable delay register data input. When chip configured dual correlators, user capability loading different offset values, each correlators. Programmable Delay Register sets number pipeline stages between output weight logic input Cascade Summer. This delay register used align correlation scores multiple correlators HSP45256 cascaded configurations (see Applications Section). number delays programmable from allowing correlators cascaded. When HSP45256 configured dual correlators, delay must 0000, which specifies delay
Control Registers
3-bit address value, A0-2, used determine which internal register will loaded with data DCONT0-7. function initiated when CLOAD brought low, register loaded rising edge CLOAD. Table indicates function associated with each address. Tables define function bits each control registers.
TABLE ADDRESS MAPPING Mask Register Configuration Register Offset Register A-Most Significant Bits Offset Register A-Least Significant Bits Programmable Delay Register Offset Register B-Most Significant Bits Offset Register B-Least Significant Bits Reserved DESTINATION
Cascade Summer
Cascade Summer used cascading several correlator chips together. value present this represents correlation score from previous HSP45256 that will summed with current score provide final correlation score. When several correlator chips cascaded, CASOUT0-12 each correlator connected CASIN0-12 next correlator chain. CASIN0-12 first chip tied low. following function represents correlation score present CASOUT0-12 each correlator: CASOUT(n) CO7)(n-Delay) CO6)(n-Delay) CO5)(n-Delay) CO4)(n-Delay) CO3)(n-Delay) CO2)(n-Delay) CO1)(n-Delay) CO0)(n-Delay) Offset (n-Delay) CASIN. where: CO0-CO7 correlation score outputs correlation stages; W0-W7 weight given each stage; n-Delay represents delay weighted summed correlation score through Programmable Delay Register; Offset value programmed into Offset register; CASIN cascade input.
HSP45256
TABLE MASK REGISTER DESTINATION ADDRESS (000) POSITIONS
FUNCTION Mask Register Enable
DESCRIPTION MR(7:0): Mask Register. When mask register corresponding reference register enabled. Mask register data loaded from DCONT(7:0) into holding register rising edge CLOAD written mask register rising edge TXFR. TABLE CONFIGURATION REGISTER DESTINATION ADDRESS (001)
POSITION
FUNCTION Reserved Reserved; Program zero.
DESCRIPTION
Configures correlator twos complement input format, where position depends current configuration. twos complement; offset binary. CONFIG4: state CONFIG4 configures HSP45256 either correlators. When CONFIG4 HSP45256 configured correlator with correlation score available CASOUT0-12. When CONFIG4 HSP45256 configured dual correlators with first correlators score available CASOUT0-8 second score available AUXOUT0-8. When chip configured dual correlators, Programmable Delay must 0000 delay
CONFIG(4)
CONFIG(3:2): CONFIG(1:0)
CONFIG(3:2): Control number data bits correlated. Table CONFIG(1:0): CONFIG1 CONFIG0 represent length correlation window indicated Table TABLE OFFSET REGISTER DESTINATION ADDRESS (010)
POSITION
FUNCTION Reserved Offset Register Reserved. Program zero.
DESCRIPTION
OFFA(12:8): Most significant bits Offset Register This register used single correlator mode. TABLE OFFSET REGISTER DESTINATION ADDRESS (011)
POSITION
FUNCTION Offset Register
DESCRIPTION OFFA(7:0): Least significant bits Offset Register TABLE PROGRAMMABLE DELAY REGISTER DESTINATION ADDRESS (100)
POSITION
FUNCTION Reserved Programmable Delay Reserved. Program zero.
DESCRIPTION
PDELAY(3:0): Controls amount delay from weight logic cascade summer. number delays 1-16, with PDELAY 0000 corresponding delay PDELAY 1111 corresponding delay
HSP45256
TABLE OFFSET REGISTER DESTINATION ADDRESS (101) POSITION
FUNCTION Reserved Offset Register Reserved. Program zero.
DESCRIPTION
OFFB8: Most significant Offset Register dual correlator mode, this register used correlator whose output appears AUXOUT pins. TABLE OFFSET REGISTER DESTINATION ADDRESS (110)
POSITION
FUNCTION Offset Register
DESCRIPTION OFFB0-7: Least significant bits Offset Register
TABLE CONFIGURATION SETUP
CONFIGURATION CORRELATORS ACTIVE INPUTS DATA BITS CORRELATOR ACTIVE OUTPUTS OUTPUT WEIGHTING
ROWS
LENGTH
DREF
DOUT
AUXOUT
CASOUT 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0 12-0
HSP45256
HSP45256
During reference register loading, 8-bits, DREF0-7 used reference data inputs. falling edge RLOAD initiates reference data loading; when RLOAD returns high, data DREF0-7 latched into selected correlation stages. active bits DREF0-7 determined current configuration. window configuration determined state control signals upon programming Control Register. Table represents programming information required each window configuration. Table note that data listed Output Weighting refers weights given each Correlation Outputs (CO0-7 Block Diagram). During initialization, loading configuration reference data user. Table shows loading options. These load controls specify whether reference data given stage comes from shift register output previous stage from external data pin.
Applications
There single correlator configurations possible with HSP45256. There dual correlator configurations possible with HSP45256. Table details configuration (bits rows length) maximum correlation sums combinations.
TABLE CORRELATION SCORE FORMULAS SINGLE CORRELATOR CONFIGURATIONS CONFIGURATION BITS ROWS LENGTH HIGHEST POSSIBLE TOTAL CORRELATION SCORE 8160
FIGURE NUMBER Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
CORRELATION SCORE CS=2(CO7+CO6+CO5+CO4)+CO3+ CO2+CO1+CO0 CS=8CO7+4CO6+2CO5+CO4CS= 8CO3+4CO2+2CO1+CO0
Single Correlator Configurations
1-Bit Data, Single Row, Samples Configuration
(1-D configuration) correlation requires only HSP45256. initialize correlator, reference bits, control bits, delay value variable delay, window configuration must specified. Table details these settings 1-bit data, Samples Configuration. Figure illustrates data flow through correlator.
TABLE REGISTER CONTENTS CORRELATOR WITH EQUAL WEIGHTING A0-2 DCONT0-7 00000000 NOTES 256-tap correlator: window configuration, reference loaded from DREF7, eight stages weighted equally, DOUT7 data input output, respectively. Offset Register
000000f00 00000000 00000000 00000000 00000000
Programmable Delay Offset Register (Loading this register optional this mode).
HSP45256
loading Reference Mask Registers done simultaneously setting A0-2 000, setting DREF DCONT inputs their proper values pulsing RLOAD CLOAD low. this configuration, DREF7 loads reference data DCONT7 loads mask information; both sets data loaded serially. will take load pulses (RLOAD) load reference array, CLOAD pulses load mask array. Upon completion mask register loading, TXFR pulsed low, which transfers reference control data from preload registers Reference Mask Registers, updating data that will used correlation. Reference mask data loaded more quickly configuring correlator sample array, loading bits eight time, then changing configuration back perform correlation.
DATA REFOUT DATAOUT
1-Bit, Quad Row, Sample Configuration
DATA DATA DATA DATA REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT
FIGURE 1-BIT, ROWS TAPS
1-Bit, Octal Row, Sample Configuration
DATA DATA DATA DATA DATA DATA DATA DATA REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT
FIGURE 1-BIT, TAPS
Other 1-Bit Configurations
1-Bit, Dual Row, Sample Configuration
DATA DATA REFOUT DATAOUT REFOUT DATAOUT
FIGURE 1-BIT, ROWS TAPS
2-Bit Configurations
2-Bit, Single Row, Sample Configuration
DATA DATA REFOUT DATAOUT REFOUT DATAOUT
FIGURE 1-BIT, ROWS TAPS
FIGURE BITS, TAPS
HSP45256
2-Bit Data, Dual Row, Samples
DATA DATA DATA DATA REFOUT DATAOUT DATA DATA REFOUT DATAOUT DATA DATA REFOUT DATAOUT REFOUT DATAOUT
2-Bit, Quad Row, Sample Configuration
DATA DATA DATA DATA REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT
FIGURE 2-BITS, ROWS TAPS
FIGURE 2-BITS, ROWS TAPS
4-Bit Configurations
4-Bit, Single Row, Sample Configuration
DATA DATA DATA DATA REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT
4-Bit Dual Row, Sample Configurations
DATA DATA DATA DATA DATA DATA DATA DATA REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT
FIGURE 4-BITS, TAPS
FIGURE BITS, ROWS TAPS
HSP45256 8-Bit Configurations
8-Bit Data, Single Row, Sample Configurations
correlation also requires only HSP45256. initialize correlator, reference bits, control bits, value programmable delay, window configuration must specified. Table details these settings. Again, loading reference mask registers done simultaneously. programming initialization, DREF0-7 used load reference data 8bits time. will take load pulses each RLOAD CLOAD load both arrays. Upon completion mask register loading, TXFR pulsed low, which transfers reference control data from preload registers registers that store active data. This configuration performs correlation 8-bit number with 1-bit reference. Each byte correlation array gives 8-bit level confidence that data corresponds reference. correlation score these confidence levels.
DATA DATA DATA DATA DATA DATA DATA DATA
TABLE REGISTER LOADING CORRELATOR WITH BINARY WEIGHTING A0-2 DCONT0-7 00001111 NOTES 256-tap correlator; window configuration, 8-bit data stream; reference register loaded from DREF7 stages. Correlator score (128 CO7) CO3) CO5) CO1) CO6) CO4) CO2) CO0. Offset Register 0000000010000.
00000000 00010000 00000000 00000000 00000000
Programmable Delay Offset Register (Loading optional this mode).
REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT REFOUT DATAOUT
FIGURE BITS, TAPS
HSP45256 Dual Correlator Configurations
1-Bit, Single Row, Sample Configuration
DATA
DATAOUT
DATA
DATAOUT
(CO7+CO6+CO5+CO4); (CASOUT)
(CO3+CO2+CO1+CO0); (AUXOUT)
FIGURE DUAL 1-BIT, TAPS
1-Bit, Dual Row, Sample Configuration
DATA DATA DATAOUT DATA DATAOUT
DATAOUT DATAOUT
DATA
(CO7+CO6+CO5+CO4); (CASOUT)
(CO3+CO2+CO1+CO0); (AUXOUT)
FIGURE 1-BIT, ROWS TAPS
1-Bit, Quad Row, Sample Configuration
DATA DATA DATA DATA DATA DATA DATA DATA
DATAOUT DATAOUT DATAOUT DATAOUT
DATAOUT DATAOUT DATAOUT DATAOUT
(CO7+CO6+CO5+CO4); (CASOUT)
(CO3+CO2+CO1+CO0); (AUXOUT)
FIGURE 1-BIT, ROWS TAPS
HSP45256
2-Bit, Dual Row, Sample Configuration
Dual correlators require only HSP45256. initialize correlator, reference bits, control bits, delay value variable delay, window configuration must specified. Table details settings 2-bit Dual Row, Sample Configuration.
DATA
this example, each dual correlators compares 2-bit data 1-bit reference. will take load pulses (RLOAD/CLOAD) completely load reference mask registers array. programmable delay must output correlators aligned.
DATAOUT
DATA
DATAOUT
DATA
DATAOUT
DATA
DATAOUT
2(CO7+CO6)+CO5+CO4); (CASOUT)
2(CO3+CO2)+CO1+CO0); (AUXOUT)
FIGURE 2-BITS, TAPS TABLE REGISTER LOADING DUAL CORRELATORS WITH EQUAL WEIGHTING AO-2 DCONT0-7 00010110 NOTES Dual correlators: Each data, taps; reference register correlation loaded from DREF7 DREF5, reference register correlator loaded from DREF3 DREF1. Correlator CO4, correlator CO0. Offset Register 0000000010000.
00000000 00010000 00000000 00000000 00000000
Programmable Delay Offset Register
2-Bit, Dual Row, Sample Configuration
DATA DATA DATA DATA DATAOUT DATAOUT DATAOUT DATAOUT DATA DATA DATA DATA DATAOUT DATAOUT DATAOUT DATAOUT
2(CO7+CO6)+CO5+CO4); (CASOUT)
2(CO3+CO2)+CO1+CO0); (AUXOUT)
FIGURE 2-BITS, ROWS TAPS
4-Bit, Single Row, Sample Configuration
DATA DATA DATA DATA DATAOUT DATAOUT DATAOUT DATAOUT DATA DATA DATA DATA DATAOUT DATAOUT DATAOUT DATAOUT
8(CO7)+4(CO6)+2(CO5)+(CO4); (CASOUT)
8(CO3)+4(CO2)+2(CO1)+(CO0); (AUXOUT)
FIGURE 4-BITS, TAPS
HSP45256
Cascading Multiple Correlator Devices
Correlators cascaded either serial parallel fashion. Longer correlations achieved connecting several correlators together shown Figures Figure each correlator data bit, row, configuration. number bits significance CASOUT output each correlator builds from correlation next, that maximum score first correlator 256, maximum output second correlator 512, etc. this configuration, maximum length correlation 4096. This would implemented with HSP45256's. Programmable Delay Register first correlator would delay, second would two, with final HSP45256 being delay Correlations more bits calculated connecting CASOUT each chip CASIN following chip (Figure 21). data CASOUT lines accumulates similar manner mode, except that maximum output first correlator decimal 960, (hexadecimal 3C0); general case, maximum number correlators that cascaded this manner eight, since maximum output last would 1E00, which nearly uses 13-bit range cascade summer. More parts could cascaded together some bits masked user prior knowledge maximum value correlation score. before, delay first correlator would one, second correlator would delay two, Multiple HSP45256's cascaded dimensional data (Figure 22). maximum output each chip same case; only difference manner which correlators connected. programmable delay registers would before.
DATA INPUT DIN7 CASIN0-12 DOUT7 CASOUT0-12 DIN7 CASIN0-12 DOUT7 CASOUT0-12 DIN7 CASIN0-12 DOUT7 CASOUT0-12 DIN7 CASIN0-12 DOUT7 CASOUT0-12 CORRELATOR SCORE OUTPUT
FIGURE 1-BIT, 1024 SAMPLE CONFIGURATION
DATA INPUT DIN7, DOUT7, CASIN0-12 CASOUT0-12 DIN7, DOUT7, CASIN0-12 CASOUT0-12 DIN7, DOUT7, CASIN0-12 CASOUT0-12 DIN7, DOUT7, CASIN0-12 CASOUT0-12 CORRELATOR SCORE OUTPUT
FIGURE 4-BIT, SAMPLE CONFIGURATION
DATA INPUT ROWS DIN0-7 CASIN0-12 CASOUT0-12
DATA INPUT ROWS DIN0-7 CASIN0-12 CASOUT0-12
DATA INPUT ROWS DIN0-7 CASIN0-12 CASOUT0-12
DATA INPUT ROWS DIN0-7 CASIN0-12 CASOUT0-12 CORRELATOR SCORE OUTPUT
FIGURE 1-BIT, WINDOW CONFIGURATION
HSP45256 Reloading Data During Operation
RLOAD CLOAD asynchronous signals that designed driven memory interface signals microprocessor. TXFR synchronized that mask reference data updated specific clock cycle. normal mode operation, user loads reference mask memories, then pulses TXFR that data. correlator uses mask reference information immediately. Loading reference mask data remains asynchronous long there least cycle between rising edge RLOAD CLOAD TXFR pulse. system timing makes necessary TXFR RLOAD and/or CLOAD active during same clock cycle, then they must treated synchronous signals; timing this case shown Figure given Timing Specifications (tTHCL tCLLH). this example, data loaded during clock cycle transferred rising edge that occurs clock cycle two. Another data loaded during clock cycle which will transferred later TXFR pulse. sequence events follows: clock cycle TXFR becomes active least nanoseconds after rising edge CLK. RLOAD and/or CLOAD pulses low; timing critical long rising edge occurs before clock cycle this condition met, undetermined whether data loaded this pulse will transferred current TXFR pulse. rising edge TXFR occurs while high during clock cycle margin between rising edge TXFR falling edge defined tTHCL. RLOAD and/or CLOAD pulses low. rising edge RLOAD CLOAD must occur after falling edge CLK. margin between defined tCLLH. time from rising edge TXFR falling edge must greater than tTHCL, time from falling edge rising edge RLOAD CLOAD must greater than this timing violated, data being transferred TXFR pulse shown include data loaded clock cycle
CLOCK CYCLE
CLOCK CYCLE
TXFR tTHCL RLOAD, CLOAD tCLLH
FIGURE LOADING TRANSFERRING DATA DURING SAME CLOCK CYCLE
HSP45256
Absolute Maximum Ratings
Supply Voltage +8.0V Input, Output Voltage -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) PLCC Package. Package. Maximum Package Power Dissipation Commercial .2.9W Commercial PLCC .2.3W Industrial PLCC .1.9W Maximum Storage Temperature Range -65oC 150oC Maximum Junction Temperature PLCC .150oC .175oC Maximum Lead Temperature (Soldering 10s) .300oC Gate Count 13,000 Gates
Operating Conditions
Voltage Range +4.75V +5.25V Temperature Range Commercial 70oC Industrial. -40oC 85oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Logical Input Voltage Logical Zero Input Voltage High Level Clock Input Level Clock Input Output High Voltage Output Voltage Input Leakage Current Output Leakage Current Standby Power Supply Current Operating Power Supply Current SYMBOL VIHC VILC ICCSB ICCOP 5.25V 4.75V 5.25V 4.75V 400µA, 4.75V +2.0mA, 4.75V GND, 5.25V VOUT GND, 5.25V GND, 5.25V 25.6MHz, GND, 5.25V, Note TEST CONDITIONS UNITS
Capacitance
25oC, Note SYMBOL UNITS TEST CONDITIONS Frequency 1MHz, Open measurements referenced device ground.
PARAMETER Input Capacitance Output Capacitance NOTES:
Power supply current proportional operating frequency. Typical rating ICCOP 7mA/MHz. tested, characterized initial design major process/design changes. Output load test load circuit 40pF.
Electrical Specifications
PARAMETER Period High
5.0V ±5%, 70oC, -40oC 85oC, Note 33MHz SYMBOL NOTES 25.6MHz UNITS
HSP45256
Electrical Specifications
PARAMETER Set-Up Time High Hold Time High TXFR Set-Up Time TXFR Hold Time Output Delay DOUT, AUXOUT, CASOUT CLOAD Cycle Time CLOAD High CLOAD Set-Up Time, RLOAD, CLOAD Hold Time, RLOAD, CLOAD RLOAD Cycle Time RLOAD High RLOAD Set-Up Time, DCONT CLOAD Hold Time, CLOAD DCONT Set-Up Time, DREF RLOAD Hold Time, RLOAD DREF Output Enable Time Output Disable Time Output Rise, Fall Time TXFR High RLOAD, CLOAD High NOTES: testing performed follows: Input levels (CLK Input) 4.0V Input levels (all other inputs) 3.0V; Timing reference levels (CLK) 2.0V; others 1.5V. Output load test load circuit with 40pF. Output transition measured 1.5V 1.5V. Controlled design process parameters directly tested. Characterized upon initial design after major process and/or design changes. 5.0V ±5%, 70oC, -40oC 85oC, Note (Continued) 33MHz SYMBOL THCL CLLH Note Note Note Note NOTES 25.6MHz UNITS
Test Load Circuit
INCLUDES STRAY
CAPACITANCE
1.5V
EQUIVALENT CIRCUIT SWITCH OPEN ICCSB ICCOP TEST
HSP45256 Timing Waveforms
DIN0-7 CLOAD A0-2 DOUT0-7 CASOUT0-12, AUXOUT0-8 DCONT0-7
TXFR
FIGURE INPUT, OUTPUT TIMING
FIGURE CONTROL INPUT TIMING
DLOAD A0-2 DREF0-7 DOUT0-7, CASOUT0-12, AUXOUT0-8 0.8V 2.0V AUXOUT0-8 CASOUT0-12 OEA, 1.7V 1.3V
FIGURE REFERENCE INPUT TIMING
FIGURE OUTPUT TIMING
THCL CLLH
TXFR
RLOAD, CLOAD
FIGURE TRANSFER, LOAD TIMING WHEN BOTH OCCUR SINGLE CYCLE
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