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MC74HC161A HC163A identical pinout LS161 LS163. device inputs compatib
Top Searches for this datasheetMC74HC161A, MC74HC163A Presettable Counters MC74HC161A HC163A identical pinout LS161 LS163. device inputs compatible with standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs. HC161A HC163A programmable 4-bit binary counters with asynchronous synchronous reset, respectively. Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance with Requirements Defined JEDEC Standard Chip Complexity: FETs Equivalent Gates Device Count Mode Binary Binary Reset Mode PDIP-16 SUFFIX CASE MC74HC16xAN AWLYYWW SO-16 SUFFIX CASE 751B HC16xA AWLYWW Assembly Location Wafer Year Work Week HC161A HC163A Asynchronous Synchronous ORDERING INFORMATION Device MC74HC16xAN MC74HC16xAD MC74HC16xADR2 RIPPLE CARRY BINARY OUTPUT Package PDIP-16 SOIC-16 SOIC-16 Shipping 2000 Rail 2500 Reel LOGIC DIAGRAM PRESET DATA INPUTS ASSIGNMENT RESET CLOCK ENABLE RIPPLE CARRY ENABLE LOAD CLOCK RESET LOAD COUNT ENABLES ENABLE ENABLE Clock FUNCTION TABLE Inputs Reset* Load Enable Enable Output Reset Load Preset Data Count Count Count *HC163A only. HC161A Asynchronous Reset Device high level, level, don't care Semiconductor Components Industries, LLC, 2000 March, 2000 Rev. Publication Order Number: MC74HC161A/D MC74HC161A, MC74HC163A MAXIMUM RATINGS* Symbol Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Vout Output Voltage (Referenced GND) Input Current, Iout Output Current, Supply Current, Pins Power Dissipation Still Air, Storage Temperature Plastic SOIC Package Tstg This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open. Lead Temperature, from Case Seconds (Plastic SOIC Package) *Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: mW/_C from 125_C SOIC Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Unit Supply Voltage (Referenced GND) Vin, Vout Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure 1000 http://onsemi.com NOTE: Information typical parametric values found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). ELECTRICAL CHARACTERISTICS (Voltages Referenced GND) Symbol Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Low-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Parameter |Iout| |Iout| Iout |Iout| |Iout| |Iout| |Iout| |Iout| |Iout| Vout |Iout| Vout |Iout| MC74HC161A, MC74HC163A Test Conditions http://onsemi.com 25_C 1.35 3.15 0.26 0.26 0.26 2.48 3.98 5.48 Guaranteed Limit 85_C 125_C 0.33 0.33 0.33 2.34 3.84 5.34 1.35 3.15 1.35 3.15 Unit ELECTRICAL CHARACTERISTICS Input Symbol tTLH, tTHL tPHL tPHL tPLH tPHL tPLH tPHL tPHL tPLH fmax Maximum Input Capacitance Maximum Output Transition Time, Output Maximum Propagation Delay, Reset Ripple Carry (HC161A Only) Maximum Propagation Delay, Clock Ripple Carry Maximum Propagation Delay, Enable Ripple Carry Maximum Propagation Delay, Reset (HC161A Only) Maximum Propagation Delay, Clock Maximum Clock Frequency (50% Duty Cycle)* Parameter *Applies noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. Clock Ripple Carry propagation delays. Enable Enable Clock setup times Clock Enable Enable hold times determine fmax. However, Ripple Carry each stage tied Clock next stage (nonsynchronously clocked) fmax table above applicable. Applications information this data sheet. NOTE: propagation delays with loads other than information typical parametric values, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Used determine no-load dynamic power consumption: load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Power Dissipation Capacitance (Per Gate)* MC74HC161A, MC74HC163A http://onsemi.com Fig. 25_C Typical 25°C, Guaranteed Limit 85_C 125_C Unit TIMING REQUIREMENTS Input Symbol trec trec Maximum Input Rise Fall Times Minimum Pulse Width, Reset (HC161A Only) Minimum Pulse Width, Clock Minimum Recovery Time, Load Inactive Clock Minimum Recovery Time, Reset Inactive Clock (HC161A Only) Minimum Hold Time, Clock Enable Enable Minimum Hold Time, Clock Reset (HC163A Only) Minimum Hold Time, Clock Load Preset Data Inputs Minimum Setup Time, Enable Enable Clock Minimum Setup Time, Reset Clock (HC163A Only) Minimum Setup Time, Load Clock Minimum Setup Time, Preset Data Inputs Clock Parameter MC74HC161A, MC74HC163A http://onsemi.com Fig. 25_C 1000 Guaranteed Limit 85_C 125_C 1000 1000 Unit MC74HC161A, MC74HC163A FUNCTION DESCRIPTION HC161A/163A programmable 4-bit synchronous counters that feature parallel Load, synchronous asynchronous Reset, Carry Output cascading count-enable controls. HC161A HC163A binary counters with asynchronous Reset synchronous Reset, respectively. INPUTS Clock (Pin level. HC161A resets asynchronously, HC163A resets with rising edge Clock input (synchronous reset). Loading internal flip-flops toggle output count advances with rising edge Clock input. addition, control functions, such resetting loading occur with rising edge Clock input. Preset Data Inputs (Pins With rising edge Clock, level Load (Pin loads data from Preset Data input pins (P0, into internal flip-flops onto output pins, through count function disabled long Load low. Count Enable/Disable These data inputs programmable counting. Data these pins synchronously loaded into internal flip-flops appear counter outputs. (Pin least-significant (Pin most-significant bit. OUTPUTS (Pins These devices have count-enable control pins: Enable (Pin Enable (Pin 10). devices count when these pins Load high. logic equation Count Enable Enable Enable Load count either enabled disabled control inputs according Table general, Enable count-enable control: Enable both count-enable Ripple-Carry Output control. Table Count Enable/Disable Control Inputs Load Enable Enable Result Outputs Count Count Count Count High when Q0-Q3 maximum* High when Q0-Q3 maximum* Ripple Carry These counter outputs. (Pin least-significant (Pin most-significant bit. Ripple Carry (Pin When counter maximum state 1111, this output goes high, providing external look-ahead carry pulse that used enable successive cascaded counters. Ripple Carry remains high only during maximum count state. logic equation this output Ripple Carry Enable CONTROL FUNCTIONS Resetting through maximum when 1111. level Reset (Pin resets internal flip-flops sets outputs through OUTPUT STATE DIAGRAMS Binary Counters http://onsemi.com MC74HC161A, MC74HC163A SWITCHING WAVEFORMS 1/fmax tPLH tPHL OUTPUT tTLH tTHL OUTPUT RESET tPHL trec CLOCK CLOCK Figure Figure ENABLE tPLH RIPPLE CARRY tTLH tPHL CLOCK tTHL RESET Figure VALID INPUTS LOAD CLOCK trec CLOCK Figure HC163A Only VALID ENABLE ENABLE Figure TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST Figure *Includes probe capacitance Figure http://onsemi.com LOAD LOAD LOAD LOAD LOAD LOAD Figure 4-Bit Binary Counter with Asynchronous Reset (MC74HC161A) MC74HC161A, MC74HC163A http://onsemi.com LOAD LOAD ENABLE LOAD LOAD RIPPLE CARRY ENABLE RESET LOAD CLOCK flip-flops shown circuit diagrams Toggle-Enable flip-flops. Toggle- Enable flip-flop combination flip-flop flip-flop. When loading data from Preset inputs Load signal used disable Toggle input (Tn) flip-flop. logic level input then clocked output flip-flop next rising edge clock. logic zero Reset device input forces internal clock high resets output flip-flop low. MC74HC161A, MC74HC163A Sequence illustrated waveforms: Reset outputs zero. Preset binary twelve. Count thirteen, fourteen, fifteen, zero, two. Inhibit. RESET (HC161A) RESET (HC163A) LOAD (ASYNCHRONOUS) (SYNCHRONOUS) PRESET DATA INPUTS CLOCK (HC161A) CLOCK (HC163A) COUNT ENABLES ENABLE ENABLE OUTPUTS RIPPLE CARRY RESET LOAD COUNT INHIBIT Figure Timing Diagram http://onsemi.com LOAD LOAD LOAD LOAD LOAD LOAD Figure 4-Bit Binary Counter with Synchronous Reset (MC74HC163A) MC74HC161A, MC74HC163A http://onsemi.com LOAD LOAD ENABLE LOAD LOAD RIPPLE CARRY ENABLE RESET LOAD CLOCK flip-flops shown circuit diagrams Toggle-Enable flip-flops. Toggle- Enable flip-flop combination flip-flop flip-flop. When loading data from Preset inputs Load signal used disable Toggle input (Tn) flip-flop. logic level input then clocked output flip-flop next rising edge clock. logic zero Reset device input forces internal clock high resets output flip-flop low. MC74HC161A, MC74HC163A TYPICAL APPLICATIONS CASCADING LOAD INPUTS INPUTS INPUTS LOAD COUNT DISABLE COUNT DISABLE LOAD LOAD ENABLE ENABLE CLOCK RIPPLE CARRY ENABLE ENABLE CLOCK RIPPLE CARRY ENABLE ENABLE CLOCK RIPPLE CARRY MORE SIGNIFICANT STAGES RESET OUTPUTS CLOCK NOTE: When used these cascaded configurations clock fmax guaranteed limits apply. Actual performance will depend number stages. This limitation times between Enable (Port) Clock. OUTPUTS OUTPUTS Figure N-Bit Synchronous Counters INPUTS LOAD ENABLE ENABLE LOAD LOAD INPUTS INPUTS LOAD ENABLE ENABLE CLOCK CLOCK RESET RIPPLE CARRY ENABLE ENABLE CLOCK RIPPLE CARRY ENABLE ENABLE CLOCK RIPPLE CARRY MORE SIGNIFICANT STAGES OUTPUTS OUTPUTS OUTPUTS Figure Nibble Ripple Counter http://onsemi.com MC74HC161A, MC74HC163A TYPICAL APPLICATIONS VARYING MODULUS HC163A OTHER INPUTS RESET OPTIONAL BUFFER NOISE REJECTION OUTPUT HC163A OTHER INPUTS RESET OPTIONAL BUFFER NOISE REJECTION OUTPUT Figure Modulo-5 Counter Figure Modulo-11 Counter HC163A facilitates designing counters modulus with minimal external logic. output glitch-free synchronous Reset. http://onsemi.com MC74HC161A, MC74HC163A PACKAGE DIMENSIONS PDIP-16 SUFFIX CASE 648-08 ISSUE NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS 0.740 0.770 18.80 19.55 0.250 0.270 6.85 6.35 0.145 0.175 4.44 3.69 0.015 0.021 0.53 0.39 0.040 0.070 1.77 1.02 0.100 2.54 0.050 1.27 0.008 0.015 0.38 0.21 0.110 0.130 3.30 2.80 0.295 0.305 7.74 7.50 0.020 0.040 1.01 0.51 0.25 (0.010) SEATING PLANE SOIC-16 SUFFIX CASE 751B-05 ISSUE NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 0.25 0.19 0.25 0.10 6.20 5.80 0.50 0.25 INCHES 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.229 0.244 0.010 0.019 0.25 (0.010) SEATING PLANE 0.25 (0.010) http://onsemi.com MC74HC161A, MC74HC163A Notes http://onsemi.com MC74HC161A, MC74HC163A Notes http://onsemi.com MC74HC161A, MC74HC163A Semiconductor trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. 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