PM3386 DUAL GIGABIT ETHERNET CONTROLLER PM3386 S/UNI-2x
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RELEASED DATASHEET PMC-1991129 ISSUE
PM3386
DUAL GIGABIT ETHERNET CONTROLLER
PM3386
S/UNI-2xGE
DUAL GIGABIT ETHERNET CONTROLLER
DATASHEET
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REVISION HISTORY Issue Issue Date Originator July 2001 Karen Leandro Details Change Release Production Datasheet Updated Characteristics with qualified values Added SERDES Mode Added GMII/TBI Mode Modified timing contained within SERDES Transmit Data Timing Modified timing contained within SERDES Received Data Timing 2001 2000 June 2000 2000 1999 Sept 1999 Karen Leandro Karen Leandro Stuart Robinson Stuart Robinson Stuart Robinson Stuart Robinson Added register descriptions. Updated register defaults Added pinout register section. Included Timing Diagrams Preliminary release Created Document.
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CONTENTS DEFINITIONS FEATURES GENERAL LINE SIDE INTERFACE. GIGABIT ETHERNET MAC. FLOW CONTROL STATISTICS
APPLICATIONS REFERENCES. APPLICATION EXAMPLES BLOCK DIAGRAM DESCRIPTION DIAGRAM DESCRIPTION. FUNCTIONAL DESCRIPTION. 10.1 10.2 SERIALIZER-DESERIALIZER (SERDES) ENHANCED GIGABIT MEDIA ACCESS CONTROL (EGMAC) 10.2.1 EGMAC GENERAL 10.2.2 EGMAC EGRESS DIRECTION. 10.2.3 EGMAC INGRESS DIRECTION. 10.2.4 EGMAC FLOW CONTROL CONTROL SUBLAYER. 10.2.5 EGMAC AUTO-NEGOTIATION
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10.2.6 EGMAC ADDRESS FILTER LOGIC 10.3 10.4 MANAGEMENT STATISTICS (MSTAT) POS-PHY LEVEL PHYSICAL LAYER INTERFACE 10.4.1 POS-PHY LEVEL GENERAL 10.4.2 POS-PHY LEVEL INGRESS PHYSICAL LAYER INTERFACE (PL3IP) 10.4.3 POS-PHY LEVEL EGRESS PHYSICAL LAYER INTERFACE (PL3EP) 10.5 10.6 MICROPROCESSOR INTERFACE JTAG TEST ACCESS PORT INTERFACE.
NORMAL MODE REGISTER DESCRIPTION TEST FEATURES DESCRIPTION 12.1 JTAG TEST PORT
OPERATION 13.1 13.2 13.3 13.4 POWER SEQUENCE SYSTEM RESET. GMII SERDES CONFIGURATION SYSTEM CLOCKING. 13.4.1 PHY-LINK FREQUENCY SELECTION. 13.4.2 GMII MODE CLOCKING 13.4.3 SERDES MODE CLOCKING 13.5 13.6 13.7 13.8 INTERFACING GMII INTERFACING INTERFACING. ENABLING DISABLING DATA FLOWS
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13.8.1 ENABLING DISABLING INGRESS DATA FLOW. 13.8.2 ENABLING DISABLING EGRESS DATA FLOW. 13.9 REGISTER ACCESS PROCEDURES 13.9.1 PL3IP REGISTER ACCESS PROCEDURE 13.9.2 PL3EP REGISTER ACCESS PROCEDURE. 13.9.3 EGMAC REGISTER ACCESS PROCEDURE. 13.10 FRAME DATA BYTE FORMAT 13.11 SERDES LOOPBACK. 13.12 GMII LOOPBACK. 13.13 MANIPULATION. 13.14 FRAME LENGTH SUPPORT 13.15 TRANSMIT PADDING GENERATION 13.16 OPERATIONS 13.16.1 13.16.2 READ ACCESS WRITE ACCESS
13.17 AUTO-NEGOTIATION. 13.17.1 13.17.2 13.17.3 MONITORING AUTO-NEGOTIATION MODIFYING AUTO-NEGOTIATION CONTROL AUTO-NEGOTIATION
13.18 TX_ER ASSERTION CRITERIA. 13.19 FRAME FILTERING 13.19.1 13.19.2 13.19.3 GROUP MULTICAST ADDRESS FILTERING EXACT MATCH FILTER PROGRAM OPTIONS. EXACT MATCH FILTER OPERATION
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13.19.4 ADDRESS FILTER ACCEPT DISCARD EVALUATION 13.19.5 ADDRESS FILTER PROGRAMMING
13.20 PAUSE FLOW CONTROL 13.20.1 13.20.2 13.20.3 13.20.4 INTERNAL FIFO FLOW CONTROL EXTERNAL SIDE-BAND PAUSE REQUEST EXTERNAL HOST BASED PAUSE REQUEST. RECEPTION 802.3 PAUSE FRAMES.
13.21 INGRESS POS-PHY BUFFER THRESHOLDS 13.22 EGRESS POS-PHY BUFFER THRESHOLDS. 13.23 POS-PHY PARITY SELECTION 13.24 POS-PHY FRAME BURST SIZES 13.25 INTERRUPT HANDLING 13.26 JTAG SUPPORT 13.26.1 CONTROLLER.
13.27 FIELD GUIDE FIRST PACKET. FUNCTIONAL TIMING. 14.1 14.2 14.3 POS-PHY LEVEL INTERFACE GMII INTERFACE MICROPROCESSOR INTERFACE
ABSOLUTE MAXIMUM RATINGS D.C. CHARACTERISTICS INTERFACE TIMING CHARACTERISTICS. ORDERING THERMAL INFORMATION.
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MECHANICAL INFORMATION.
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DEFINITIONS CSMA/CD 1000BASE-T 1000BASE-SX 1000BASE-LX Auto-Negotiation Base Page Comma CommaComma+ Data Frame Even Parity Carrier Sense Multiple Access with Collision Detection. IEEE 802.3-1998 Physical Layer specification 1000 Mb/s CSMA/CD using four pairs Category balanced copper cabling. IEEE 802.3-1998 using short wavelength laser devices over multimode fiber IEEE 802.3-1998 using long wavelength laser devices over multimode single-mode fiber. algorithm that allows devices either link segment negotiate common data service functions. first 16-bit message exchanged during IEEE 802.3-1998 Auto-Negotiation. seven-bit sequence that part 8B/10B code-group that used purpose code-group alignment. seven-bit sequence (1100000) encoded data stream. seven-bit sequence (0011111) encoded data stream. Consists Destination Address, Source Address, Length Field, logical link control (LLC) Data, PAD, Frame Check Sequence. source destination data connected local area network. frame. packet count number data word bits. there number then parity will that including parity bit, number even number. Same Data Frame mode operation that supports simultaneous communication between pair stations, provided that Physical Layer capable supporting simultaneous transmission reception without interference. Gigabit Media Independent Interface. Inter-Packet (IPG): delay time between CSMA/CD physical packets intended provided interframe recovery time other CSMA/CD sublayers Physical Medium. Management Information Base (MIB): repository information describe operation specific network device.
Frame Full Duplex
GMII
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Next Page Nibble Packet
Physical Packet POS-PHY
Parity
Media Access Control (MAC): data link sublayer that responsible transferring data from Physical Layer. Media independent Interface (MII): transparent signal interface bottom Reconciliation sublayer. General class pages optionally transmitted AutoNegotiation able devices following base page word negotiation. group four data bits. unit exchange MII. logical unit data transferred across POS-PHY Level interface. This generally corresponds Data Frame defined previously, although present POS-PHY Level egress direction. Consists Data Frame defined previously, preceded Preamble Start Frame Delimiter, encoded, appropriate, Physical Layer (PHY) type. SATURN compatible Packet over SONET interface specification physical layer devices. POS-PHY level defines interface rates including 2.488 Gbit/s. Short hand notation POS-PHY Level term. count number data word bits. there number then parity will that including parity bit, number number Start Frame. Start Packet.
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FEATURES General port full-duplex Gigabit Ethernet Controller with industry standard POS-PHY Level system interface. Provides direct connect optics internal Serializer/Deserializer (SERDES) Provides connection copper Gigabit Ethernet physical layer devices GMII interfaces. Incorporates dual SERDES, compatible IEEE 802.3 1998 physical layer specification. Provides on-chip data recovery clock synthesis. Supports dual IEEE 802.3 -1998 GMII interfaces connection copper Gigabit Ethernet physical layer devices. Provides dual standard IEEE 802.3 Gigabit Ethernet MACs frame verification. Enables frame filtering unicast multicast entries. Internal byte egress byte ingress FIFOs channel accommodate system latencies. Incorporates SATURN POS-PHY Level 32-bit System Interface clocked mode only). Line side loopback capability system level diagnostic capability. Includes generic microprocessor interface device initialization, control, register port statistics access. Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. power 1.8V CMOS device with 3.3V compatible digital inputs compatible microprocessor inputs) 3.3V CMOS/TTL compatible digital outputs within 27mm 27mm UBGA package. Industrial temperature range (-40°C +85°C). Line Side Interface SERDES interface provides differential pairs 1250 connection electrical optical modules. GMII interface provides wide data interfaces with control signals connection copper Gigabit Ethernet physical layer devices. Allows selection between SERDES GMII interface channel basis.
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Gigabit Ethernet Verifies frame integrity (i.e. length checks). Erred frames filtered passed higher layer device. Automatic Base page Auto-Negotiation, extended Auto-Negotiation (Next Page) supported host. Egress Ethernet physical frame encapsulation (pad size, preamble, generation). Supports Ethernet 2.0, IEEE 802.3 IEEE 802.3 SNAP/LLC encoding formats VLAN tagged frames. Provides unicast exact-match address filters filter frames based with optional VID. Each address filter programmed indicate whether accept discard based match. Provides group multicast address filter. Supports byte minimum size frames jumbo frames 9.6K bytes. Programmable Inter-packet (IPG). System side loopback through GMAC diagnostic capability. Flow Control Supports IEEE 802.3-1998 flow control each Ethernet port enabled. Programmable watermarks full/empty FIFO thresholds. Automatic generation PAUSE frames based FIFO fill levels. Upper layer device flow control Ethernet ports using side-band host signaling cause generation PAUSE frame. Provides side-band Paused state indication upstream devices. Loss-less flow control valid frames 9.6k bytes. Statistics counters used ensure rollover compliance with IEEE 802.3-1998. Minimum minutes before rollover. Provides port statistic counters needed support standard 802.3-1998, SNMP, RMON Management Information Base (MIB) implementations.
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APPLICATIONS Core Routers Edge Routers Enterprise Edge Routers Multi-Service Switches/Routers SONET/SDH Transport Muxes
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REFERENCES IEEE 802.3-1998 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method Physical Layer Specifications PMC-980495 SATURN Compatible Interface Packet Over SONET Physical Layer Link Layer Devices (Level 1757 Remote Network Monitoring Management Information Base 1213 Management Information Base Network Management TCP/IPbased internets: MIB-II 2233 Interfaces Group using SMIv2 2665 Definitions Managed Objects Ethernet-like Interface Types
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APPLICATION EXAMPLES PM3386 S/UNI-2xGE applicable equipment implementing high density Gigabit Ethernet interfaces. PM3386 dual channel SERDES GMAC with embedded FIFOs that provides high density power Gigabit Ethernet solution direct connection electrical optical modules. Alternatively, GMII interface provided connection copper Gigabit Ethernet physical layer devices. system side, POS-PHY Level synchronous FIFO style interface clocked MHz) allows common connection higher layer devices. common system interface simplifies multi-service equipment utilizing some following physical layer options: OC-48 POS/A4xOC-12 POS/A16xOC-3 POS/AChannelized POS/AHigh density Gigabit Ethernet
PM3386 particularly suited following applications: Core Routers Edge Routers Enterprise Edge Routers Multi-Service Switches/Routers SONET/SDH Transport Muxes
These applications require various interfaces (Gigabit Ethernet, ATM, POS, DS3) which POS-PHY Level interface. Service cards various physical layer options re-use upper layer devices board design improve timeto market. Gigabit Ethernet within Internet points presence (POPs), Super POPs Transport POPs increasing requirement inexpensive high-speed Layer interconnect. Thus, connections between
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Edge Routers Core Routers within provided Gigabit Ethernet. Co-located server clusters also connected Gigabit Ethernet routers. Similarly, Gigabit Ethernet becoming choice connection between Enterprise Routers Multi-Service switches. Transport equipment looking provide Ethernet directly over SONET/SDH wide area transparent bridging. typical application S/UNI-2xGE performs data recovery Gigabit Ethernet stream, level frame checks sends frame upper layer device (such processor) forwarding POS-PHY level interface. S/UNI-2xGE maintains extensive statistics SNMP RMON applications. egress, frames formatted into physical frames with proper inter-frame gap, preamble start frame delimiter. physical packet then serialized transmission over external electrical optical module. initial configuration ongoing control monitoring S/UNI-2xGE provided generic microprocessor interface. following diagram shows typical multi-service card application PM3386 S/UNI2xGE with similar cards OC48 Quad OC-12 ports.
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Figure
PM3386 Typical Application Example
POS-PHY Level
Gigabit Ethernet Line Card
+/RX +/Copper PM3386 S/UNI 2xGE
Upper Layer Device(s)
Scheduler
Gigabit Ethernet
Twisted Pair
Optical Transceiver
Switch Fabric
Classification/ Forwarding
Gigabit Ethernet
GMII
Switch Fabric Device
OC-48 Line Card
Upper Layer Device(s)
Scheduler
OC-48
Optical Transceiver
+/RX
PM5381 S/UNI 2488 Classification Forwarding
Switch Fabric Device
OC-12
Optical Transceiver Optical Transceiver Optical Transceiver
Quad OC-12 Line Card
Upper Layer Device(s)
Scheduler
OC-12
PM5380 S/UNI 4x622 Classification Forwarding
OC-12 OC-12
Optical Transceiver
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BLOCK DIAGRAM Figure PM3386 Dual Gigabit Ethernet POS-PHY Level
POS-PHY Level Ingress Interface
MDIO RX_CLK RX_DV RX_ER [7:0] GTX_CLK TX_EN TX_ER [7:0]
Managment Statistics Enhanced Gigabit Flow Ctrl Auto-Negotiation Address Filtering
PAUSE [1:0] PAUSED [1:0] RFCLK RENB RDAT[31:0] RMOD[1:0] RPRTY RVAL RSOP REOP RERR
GMII Interface
Ingress FIFO Gigabit Media Access Controller
Data Recovery/ Serial Parallel 8B/10B Encoder/ Decoder
Egress Interface
DTPA[1:0] STPA PTPA TADR TFCLK TENB TDAT[31:0] TMOD[1:0] TPRTY TSOP TEOP TERR
CLK125
Clock Multiply
+/ATP[3:0]
Parallel Serial SERDES Microprocessor Interface
Egress FIFO
JTAG
PMD_SEL [1:0]
RSTB
INTB [10:0]
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[15:0]
TRSTB
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Figure
PM3386 Device Loop Back Paths
POS-PHY Level Ingress Interface
MDIO RX_CLK RX_DV RX_ER [7:0] GTX_CLK TX_EN TX_ER [7:0]
Managment Statistics Enhanced Gigabit Flow Ctrl Auto-Negotiation Address Filtering
PAUSE [1:0] PAUSED [1:0] RFCLK RENB RDAT[31:0] RMOD[1:0] RPRTY RVAL RSOP REOP RERR
GMII Interface
Ingress FIFO Gigabit Media Access Controller
Data Recovery/ Serial Parallel 8B/10B Encoder/ Decoder
Egress Interface
DTPA[1:0] STPA PTPA TADR TFCLK TENB TDAT[31:0] TMOD[1:0] TPRTY TSOP TEOP TERR
CLK125
Clock Multiply
+/ATP[3:0]
Parallel Serial SERDES Microprocessor Interface
Egress FIFO
JTAG
PMD_SEL [1:0]
RSTB
TRSTB
INTB [10:0]
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[15:0]
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DESCRIPTION PM3386 monolithic integrated circuit that implements port full duplex 1000 Mbit/s Gigabit Ethernet data transport device. PM3386 provides line interface connectivity provided on-chip SERDES GMII functions data transport stream device industry standard POS-PHY Level interface. Serializer-Deserializer (SERDES) PM3386 internal serializer-deserializer transceivers. SERDES IEEE 802.3-1998 Gigabit Ethernet compatible supporting gigabit data transfer flows. SERDES based X3T11 specification. PM3386 receives transmits Gigabit Ethernet streams using serial interface direct connection optical transceiver devices. SERDES performs data recovery serial parallel conversion connection Enhanced Gigabit Media Access Control block. Gigabit Media Independent Interface (GMII) Gigabit Ethernet over copper support, PM3386 provides dual standard GMII interfaces. copper Gigabit Ethernet physical layer device connected PM3386 this interface. Enhanced Gigabit Media Access Control (EGMAC) Enhanced Gigabit Media Access Control (EGMAC) block provides integrated IEEE 802.3-1998 Gigabit Ethernet Media Access Control (MAC) supporting high performance 1000Base capability. EGMAC line side interfaces connection internal (SERDES) external Gigabit GMII each Gigabit Ethernet port. Enhanced Gigabit (EGMAC) incorporates Gigabit Ethernet functions including AutoNegotiation, statistics, Control Sub-layer that adheres IEEE 802.3-1998 providing support PAUSE control frames. EGMAC provides basic frame integrity checks validate incoming frames. EGMAC also provides simple line rate ingress address filtering support exact-match address unicast filters, 64-bin hash-based multicast filter, ability filter accept matched frames instance programmable fashion. inquires filtering done line rate with system latency introduced look cycles.
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Management Statistics (MSTAT) PM3386 also incorporates rich port RMON, SNMP, Etherlike Management Information Base counters. Deep statistical counters used management counts providing minimum rollover time greater than minutes. counts easily managed Management Statistics (MSTAT) block. POS-PHY Level Interface (PL3) PM3386 connect single upper layer device through POS-PHY Level Interface. POS-PHY Level interface 32-bit wide interface with clock rate from MHz. POS-PHY Level developed with cooperation SATURN Development Group cover application rates including Gbit/s. This interface provides standards support interoperation between PM3386, multiple layer device, connecting Link Layer device. interface stresses simplicity operation allow forward migration more elaborate Link Layer devices. POSPHY interface contains 64KB receive 16KB transmit FIFOs channel. These FIFOs contain programmable thresholds specifying full empty conditions. Receive Direction receive direction, PM3386 configured internal SERDES GMII interface channel basis. SERDES operation, Gigabit Ethernet stream received from external optical transceiver. data recovered converted from serial parallel data connection EGMAC block. EGMAC terminates 8B/10B line codes performs frame integrity checks (frame length, etc). GMII operation, physical packet sourced from external copper physical layer device PM3386 GMII interface bits clocked MHz). EGMAC accepts data performs frame integrity checks once complete frame received. EGMAC optionally filter erred frames. Statistics updated frame sent POS-PHY Level interface. FIFO's POS-PHY interface accommodate system latencies allows loss-less flow control 9.6k bytes. received frames then read through POS-PHY Level bits clocked from 60-104 MHz) system side interface. Transmit Direction transmit direction, packets transmitted written into POS-PHY FIFO through POS-PHY Level interface bits clocked from 60-104
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MHz) from upper layer device. channel selected upper layer device indicated in-band POS-PHY interface. EGMAC builds properly formatted Ethernet physical packet (padding minimum size inserting preamble, start frame delimiter (SFD) inter-packet (IPG)). Statistics updated physical packet sent SERDES GMII interface. SERDES operation, EGMAC encodes physical packet using 8B/10B encoding passes physical packet SERDES block. SERDES performs parallel serial conversion using internally synthesized 1250 clock. stream sent external optical transceiver transmission over fiber cable. GMII operation, EGMAC sends physical packet byte byte across GMII interface bits clocked MHz) external copper Gigabit Ethernet physical layer device. copper Gigabit Ethernet physical layer device then transmits physical packet over copper cable. Flow Control Flow control handled EGMAC block. When PAUSE control frame received, PM3386 will optionally terminate transmission (after current frame sent) assert appropriate channel side band flow control output indicate paused condition. received PAUSE control frame optionally filtered passed link layer device POS-PHY Level interface. PAUSE control frames transmitted either under link layer control using channel side band flow control inputs, under link layer control transparent PM3386, host based PAUSE frame control under internal control based receive FIFO levels. four methods provide loss-less flow control. General PM3386 configured, controlled monitored generic 16-bit microprocessor interface. PM3386 also provides standard signal IEEE 1149.1 JTAG test port boundary scan board test purposes. PM3386 implemented power, +1.8 Volt, CMOS technology with compatible digital inputs 3.3V TTL/CMOS compatible digital outputs. PM3386 packaged 352-pin UBGA package.
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DIAGRAM PM3386 packaged 352-pin Ultra Ball Grid Array (UBGA) having body size 27mm 27mm. Table PM3386 Diagram
VSSQ
RXD1 RXD1 RX_E TX_E TXD1 TXD1 D[13 D[10 VSSQ A[6] A[3] A[1] D[7] D[4] D[1] RXD1 RXD1 RX_C TX_E TXD1 TXD1 D[15 D[11 VDDO INTB A[9] A[8] A[5] A[2] D[8] D[5] D[2] VDDO RXD1 RXD1 RX_D GTX_ TXD1 TXD1 TXD1 A[10 D[12 TRST VDDO A[7] A[4] A[0] D[9] D[6] D[3] VDDO CLK1 RXD1 RXD1 TXD1 D[14 VDDO VDDO VDDI VDDO VDDI VDDQ VDDO VDDI VDDI VDDO D[0] VDDO VDDO
PMD_ VDDI VDDI SEL1 CLK1 VDDQ AVDL
RDAT
AVDH AVDQ AVDL AVDL RXSD AVDH VDDO RXD1 RXD1 AVDL AVDL AVDH AVDH TXD1 TXD1 ATP0 ATP1 AVDL AVDL AVDH AVDL AVDL AVDL AVDQ AVDL RXD0 RXD0 RXSD AVDH AVDL AVDL VDDO TXD0 TXD0 AVDH PMD_ VDDI SEL0 TXD0 TXD0 TXD0 TXD0 TXD0 TXD0 VDDO TXD0 TXD0 VDDI VDDO
RDAT VDDI RDAT RDAT RDAT VDDO RDAT RDAT VSSQ RDAT RDAT RDAT RDAT [11] RDAT RDAT RDAT VDDQ [10] [12] [13] RDAT RDAT RDAT VDDI [14] [15] [16] RDAT RDAT VDDO [17] [18] RDAT RDAT RDAT [21] [20] [19] RDAT RDAT RDAT VDDI [24] [23] [22] RDAT RDAT RDAT RDAT [30] [28] [26] [25] RPRT RDAT RDAT [29] [27] RDAT VDDO RERR REOP [31] RMOD RFCL VDDI RVAL PAUS PAUS RMOD RSOP PAUS VDDQ RENB PAUS VSSQ RSTB
RX_C TDAT TDAT TDAT TMOD VDDI VDDO VDDI VDDQ VDDO VDDI VDDO VDDI VDDI VDDO [31] [11] GTX_ RXD0 RXD0 RXD0 TDAT TDAT TDAT TDAT TDAT TDAT TDAT TDAT TDAT TMOD VDDO TENB TEOP STPA VDDO CLK0 [28] [25] [21] [19] [16] [13] TX_E RX_D RXD0 RXD0 TDAT TDAT TDAT TDAT TDAT TDAT TDAT TDAT TDAT TDAT TDAT TPRT DTPA VDDO MDIO TADR VDDO [29] [26] [23] [20] [18] [17] [14] [10] TX_E RX_E RXD0 RXD0 RXD0 TDAT TDAT TDAT TDAT TDAT TDAT TDAT TDAT TDAT TFCL DTPA VSSQ TSOP TERR PTPA [30] [27] [24] [22] [15] [12] VDDO VDDO VDDI
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DESCRIPTION Serial Line Side Interface Signals Type Schmitt Input Function Reference Clock (Port reference clock used generate GTX_CLK0 GTX_CLK1 during GMII mode. Clock Synthesis Unit uses this clock it's input reference during SERDES mode. Please refer Operations section discussion clock mode selection interfacing issues.
Table
Name CLK125
RXD0+ RXD0-
Differential PECL Input
Receive Differential Data (Port These PECL inputs (RXD0+/-) contain 8B/10B serial receive stream. receive data recovered from RXD0+/bit stream. Receive Signal Detect (Port RXSD0 indicates presence valid receive signal power from Optical Physical Medium Dependent Device. logic level high indicates presence valid data. logic indicates loss signal.
RXSD0
Input
RXD1+ RXD1-
Differential PECL Input
Receive Differential Data (Port PECL inputs RXD1+/- contain 8B/10B serial receive stream. receive data recovered from RXD1+/bit stream.
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Name RXSD1
Type Input
Function Receive Signal Detect (Port RXSD1 indicates presence valid receive signal power from Optical Physical Medium Dependent Device. logic level high indicates presence valid data. logic indicates loss signal.
TXD0+ TXD0-
Differential PECL Output Differential PECL Output BiM24 Directional CMOS
Transmit Differential Data (Port PECL outputs TXD0+/- contain 1.25 Gbit/s transmit stream. TXD0+/outputs driven using clock. Transmit Differential Data (Port PECL outputs TXD1+/- contain 1.25 Gbit/s transmit stream. TXD1+/outputs driven using clock. Receive Transmit Analog Test Ports ATP[1:0] pins used manufacturing testing only should tied analog ground.
TXD1+ TXD1-
ATP0 ATP1
Table
-Gigabit Media Independent Interface (GMII) Direction Output AD22 Function GMII Transmit Clock (Port reference clock supplied PM3386.
Signal Name GTX_CLK0
TXD0[0] TXD0[1] TXD0[2] TXD0[3] TXD0[4] TXD0[5] TXD0[6] TXD0[7]
Output
AA24 AA25
GMII Transmit Data (Port Byte-wide transmit data output these pins synchronously device. least significant bit, TXD0[0] first transferred line. This signal updated rising edge GTX_CLK0.
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Signal Name TX_EN0
Direction Output
AE23
Function Transmit Enable (Port When GMII mode this signal active high signal asserted when valid data present TXD0[7:0] TX_ER0 pins. This signal updated rising edge GTX_CLK0. When SERDES mode this signal enables operation external transmitter. When asserted (default active low) indicates potential presence valid transmit data. When de-asserted indicates absence valid transmit data. Note that while SERDES mode polarity this signal programmable support interoperability with differing optical transmitters.
TX_ER0
Output
AF24
GMII Transmit Coding Error (Port Active high signal asserted when error detected during transmission. Please refer Operations section full listing error conditions reported PM3386 using TX_ER0 output. This signal updated rising edge GTX_CLK0.
RX_CLK0
Schmitt Input Input
AC21
GMII Receive Clock (Port GMII reference clock received from device.
RXD0[0] RXD0[1] RXD0[2] RXD0[3] RXD0[4] RXD0[5] RXD0[6] RXD0[7]
AF20 AD19 AE20 AF21 AD20 AE21 AF22 AD21
GMII Receive Data (Port Byte-wide receive data input these pins synchronously from device. least significant bit, RXD0[0] expected contain first received line. This signal synchronized RX_CLK0.
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Signal Name RX_DV0
Direction Input
AE22
Function GMII Receive Data Valid (Port Active high signal asserted when valid data present RXD0[7:0] RX_ER0 pins. This signal synchronized RX_CLK0.
RX_ER0
Input
AF23
GMII Receive Error (Port Active high signal asserted when there been error during received physical packet. This signal synchronized RX_CLK0.
GTX_CLK1
Output
GMII Transmit Clock (Port reference clock supplied PM3386.
TXD1[0] TXD1[1] TXD1[2] TXD1[3] TXD1[4] TXD1[5] TXD1[6] TXD1[7]
Output
GMII Transmit Data (Port Byte-wide transmit data output these pins synchronously device. least significant bit, TXD1[0] first transferred line. This signal updated rising edge GTX_CLK1.
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Signal Name TX_EN1
Direction Output
Function Transmit Enable (Port When GMII mode this signal active high signal asserted when valid data present TXD1[7:0] TX_ER1 pins. This signal updated rising edge GTX_CLK1. When SERDES mode this signal enables operation external transmitter. When asserted (default active low) indicates potential presence valid transmit data. When de-asserted indicates absence valid transmit data. Note that while SERDES mode polarity this signal programmable support interoperability with differing optical transmitters.
TX_ER1
Output
GMII Transmit Coding Error (Port Active high signal asserted when error detected during transmission. Please refer Operations section full listing error conditions reported PM3386 using TX_ER1 output. This signal updated rising edge GTX_CLK1.
RX_CLK1
Schmitt Input Input
GMII Receive Clock (Port GMII reference clock received from device.
RXD1[0] RXD1[1] RXD1[2] RXD1[3] RXD1[4] RXD1[5] RXD1[6] RXD1[7]
GMII Receive Data (Port Byte-wide receive data input these pins synchronously from device. least significant bit, RXD1[0] expected contain first received line. This signal synchronized RX_CLK1.
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Signal Name RX_DV1
Direction Input
Function GMII Receive Data Valid (Port Active high signal asserted when valid data present RXD1[7:0] RX_ER1 pins. This signal synchronized RX_CLK1
RX_ER1
Input
GMII Receive Error (Port Active high signal asserted when there been error during received physical packet. This signal synchronized RX_CLK1.
Output
AD18
Management Data Clock provides reference clock communication between PM3386 other transceivers.
MDIO
Internal pull-down
AE19
Management Data When configured input, external supplies status during Management read cycles. When configured output, PM3386 supplies control during Management write/read cycles data during Management write cycles. Data values MDIO updated sampled rising edge MDC.
Table
-POS-PHY Level Transmit Interface Direction Schmitt Input Function POS-PHY Transmit FIFO Write Clock TFCLK used synchronize data transfer transactions between higher layer device PM3386. TFCLK cycles rate.
Signal Name TFCLK
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Signal Name TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] TDAT[16] TDAT[17] TDAT[18] TDAT[19] TDAT[20] TDAT[21] TDAT[22] TDAT[23] TDAT[24] TDAT[25] TDAT[26] TDAT[27] TDAT[28] TDAT[29] TDAT[30] TDAT[31]
Direction Input
AC10 AD10 AE10 AD11 AF10 AE11 AC12 AF11 AD12 AE12 AF12 AD13 AE13 AE14 AD14 AE15 AD15 AF16 AE16 AF17 AD16 AE17 AF18 AD17 AE18 AF19 AC17
Function POS-PHY Transmit Packet Data This carries packet octets that written selected transmit FIFO in-band port address select desired transmit FIFO. TDAT considered valid only when TENB simultaneously asserted. When 32-bit interface used, data must transmitted endian order TDAT[31:0]. TDAT[31:0] sampled rising edge TFCLK.
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Signal Name TERR
Direction Input
Function POS-PHY Transmit Error Indicator Active high signal used indicate that current packet must aborted. TERR should only considered valid when TENB TEOP simultaneously asserted. TERR sampled rising edge TFCLK.
TENB
Input
POS-PHY Transmit Write Enable Active signal used control flow data transmit FIFOs. When TENB high, TDAT[31:0], TMOD, TSOP, TEOP, TPRTY TERR signals invalid ignored PM3386. However, signal asserted valid processed PM3386 only when TENB high. When TENB low, TDAT[31:0], TMOD, TSOP, TEOP, TPRTY TERR signals valid processed PM3386. signal ignored PM3386 when TENB low. TENB sampled rising edge TFCLK.
TPRTY
Input
POS-PHY Transmit parity transmit parity (TPRTY) signal indicates parity calculated over TDAT bus. TPRTY considered valid only when TENB asserted. default PM3386 uses parity. PM3386 supports both even parity. PM3386 reports parity error host processor maskable interrupt, does interfere with transferred data. TPRTY sampled rising edge TFCLK.
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Signal Name TMOD[0] TMOD[1]
Direction Input
Function POS-PHY Transmit Word Modulo TMOD[1:0] indicates number valid bytes data TDAT[31:0]. TMOD should always zero, except during last double-word transfer packet TDAT[31:0]. When TEOP TENB asserted, number valid packet data bytes TDAT[31:0] specified TMOD[1:0]. TMOD[1:0] "00" TMOD[1:0] "01" TMOD[1:0] "10" TMOD[1:0] "11" TDAT[31:0] valid TDAT[31:8] valid TDAT[31:16] valid TDAT[31:24] valid
TMOD [1:0] sampled rising edge TFCLK. Input POS-PHY Transmit Start Transfer Active high signal indicating when inband port address present TDAT[31:0] bus. When high TENB high (not asserted), value contained within TDAT[7:0] address transmit FIFO selected. TDAT[7:0] selects channel zero. TDAT[7:0] selects channel one. Subsequent data transfers TDAT will fill FIFO specified this inband address. TDAT[7:0] channel within PM3386 device will selected. Subsequent data transfers TDAT address outside will dropped interface. considered valid only when TENB asserted. sampled rising edge TFCLK.
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Signal Name TSOP
Direction Input
Function POS-PHY Transmit Start Packet Active high signal used delineate packet boundaries TDAT bus. When TSOP high, start packet present TDAT bus. TSOP required present beginning every packet considered valid only when TENB asserted. TSOP sampled rising edge TFCLK.
TEOP
Input
POS-PHY Transmit Packet Active high signal used delineate packet boundaries TDAT bus. When TEOP high, packet present TDAT bus. Note that TMOD[1:0] indicates number valid bytes last double word composed when TEOP TENB asserted. TEOP required present every packet considered valid only when TENB asserted. TEOP sampled rising edge TFCLK.
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Signal Name TADR
Direction Input
Function POS-PHY Transmit Address TADR signal used with PTPA signal poll transmit FIFOs packet available status. When TADR sampled rising edge TFCLK PM3386, polled packet available indication PTPA signal updated with status port specified TADR address following rising edge TFCLK. TADR channel TADR channel TADR sampled rising edge TFCLK.
PTPA
Output
POS-PHY Polled-PHY Transmit Packet Available PTPA transitions high when predefined (user programmable) minimum number bytes available polled transmit FIFO. Once high, PTPA indicates that transmit FIFO full. When PTPA transitions low, indicates that transmit FIFO full near full (user programmable). PTPA allows polling PM3386 channel selected TADR address pin. port which PTPA reports updated following rising edge TFCLK after PM3386 channel address TADR sampled PM3386 device. PTPA updated rising edge TFCLK.
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Signal Name STPA
Direction Output
Function POS-PHY Selected-PHY Transmit Packet Available STPA transitions high when predefined (user programmable) minimum number bytes available transmit FIFO specified in-band address TDAT bus. Once high, STPA indicates transmit FIFO full. When STPA transitions low, indicates that transmit FIFO full near full (user programmable). STPA always provides status indication selected port PM3386 device order avoid FIFO overflows while polling performed. port which STPA reports updated following rising edge TFCLK after PM3386 channel address TDAT sampled PM3386 device. STPA updated rising edge TFCLK.
DTPA0 DTPA1
Output
POS-PHY Direct Transmit Packet Available Active high signals that provide direct status indication corresponding ports PM3386. DTPA[1:0] transitions high when predefined (user programmable) minimum number byes available transmit FIFO. Once high, DTPA[1:0] signals indicate that corresponding transmit FIFO full. When DTPA[1:0] transitions low, indicates that transmit FIFO full near full. (user programmable). DTPA0 corresponds channel zero. DTPA1 corresponds channel one. DTPA0 DTPA1 updated rising edge TFCLK.
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Table Signal Name RFCLK
POS-PHY Level Receive Interface Direction Schmitt Input Function POS-PHY Receive FIFO Write Clock RFCLK used synchronize data transfer transactions between higher layer device PM3386. RFCLK cycles rate MHz. POS-PHY Receive Data Valid Active high signal indicating validity receive data signals. RVAL will transition when receive FIFO empty, data burst from given channel. When RVAL high, RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP RERR signals valid. When RVAL low, RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP RERR signals invalid must disregarded. signal only valid when RVAL low. RVAL updated rising edge RFCLK.
RVAL
Output
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Signal Name RENB
Direction Input
Function POS-PHY Receive Read Enable Active signal used control flow data from PM3386. higher layer device de-assert RENB anytime unable accept data from PM3386. When RENB sampled PM3386, upper level device signaling that receive data. then asserted indicate address RDAT[0] RVAL asserted indicating validity read data control RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, RERR signals. Note that these signals will updated following rising edge RFCLK. When RENB sampled high PM3386, upper level device signaling that longer accept data. following rising edge RFCLK, active, RVAL signal will remain asserted signifying valid data control RDAT[31:0], RPRTY, RMOD[1:0], RSOP, REOP, RERR. RENB sampled rising edge RFCLK.
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Signal Name RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RDAT[16] RDAT[17] RDAT[18] RDAT[19] RDAT[20] RDAT[21] RDAT[22] RDAT[23] RDAT[24] RDAT[25] RDAT[26] RDAT[27] RDAT[28] RDAT[29] RDAT[30] RDAT[31]
Direction Output
Function POS-PHY Receive Packet Data RDAT[31:0] carries packet octets that read from receive FIFO in-band port address selected receive FIFO. in-band address RDAT[0] considered valid only when RVAL deasserted (LOW) asserted (HIGH). data RDAT[31:0] considered valid only when RVAL asserted(HIGH). Data presented data endian order RDAT[31:0]. RDAT[31:0] updated rising edge RFCLK.
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Signal Name RPRTY
Direction Output
Function POS-PHY Receive Parity receive parity (RPRTY) signal indicates parity calculated over RDAT bus. RPRTY only valid when RVAL asserted. PM3386 supports both even parity over RDAT bus. RPRTY updated rising edge RFCLK.
RMOD[0] RMOD[1]
Output
POS-PHY Receive Word Modulo RMOD[1:0] indicates number valid bytes data RDAT[31:0]. RMOD must always zero, except during last double-word transfer packet RDAT[31:0]. When REOP RVAL asserted, number valid packet data bytes RDAT[31:0] specified RMOD[1:0]. RMOD[1:0] "00" RMOD[1:0] "01" RMOD[1:0] "10" RMOD[1:0] "11" RDAT[31:0] valid RDAT[31:8] valid RDAT[31:16] valid RDAT[31:24] valid
RMOD[1:0] considered valid only when RVAL REOP asserted. RMOD[1:0] updated rising edge RFCLK. RSOP Output POS-PHY Receive Start Packet Active high signal used delineate packet boundaries RDAT bus. When RSOP high, start packet present RDAT bus. RSOP required present start every packet only considered valid when RVAL asserted. RSOP updated rising edge RFCLK.
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Signal Name REOP
Direction Output
Function POS-PHY Receive Packet Active high signal used delineate packet boundaries RDAT bus. When REOP high, packet present RDAT bus. Note that RMOD[1:0] indicates number valid bytes last double word composed when REOP RVAL asserted. REOP required present every packet considered valid only when RVAL asserted. REOP updated rising edge RFCLK.
RERR
Output
POS-PHY Receive error indicator Active high signal used indicate that current packet aborted should discarded. RERR shall only asserted when REOP RVAL asserted. Conditions that cause RERR limited FIFO overflow, abort sequence detection error. RERR updated rising edge RFCLK.
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Signal Name
Direction Output
Function POS-PHY Receive Start Transfer indicates when in-band port address present RDAT bus. When high RVAL low, value RDAT[0] address receive FIFO selected PM3386. Subsequent data transfers RDAT will from FIFO specified this in-band address. considered valid only when RVAL asserted. considered valid only when RENB asserted previous cycle. updated rising edge RFCLK.
Table Name PAUSE0 PAUSE1
Side-band Flow Control Type Input Internal pull-down Description PAUSE Control Assertion PAUSE0 PAUSE1 signals cause (programmed option) PM3386 channel basis transmit 802.3-1998 PAUSE frames either drop layer pass POS-PHY client further incoming frames (programmed option). De-assertion PAUSE0 PAUSE1 signal cause removal PAUSE condition channel basis. programmability options these pins please PAUSE flow control section Operations section. PAUSE0 PAUSE1 active high signals. PAUSE0 PAUSE1 sampled rising edge RFCLK.
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PAUSED0 PAUSED1
Output
PAUSED Status PAUSED0 PAUSED1 signals indicate reception execution 802.3-1998 PAUSE control frames given port PM3386. asserted (high) PAUSED0 PAUSED1 indicates that corresponding channels ingress PAUSE timer non-zero. This also typically indicates enabled FCRX EGMAC GMACC1Config Register) that given channel paused state. De-assertion PAUSED0 PAUSED1 indicates that corresponding channels PAUSE counter zero. This also typically indicates that given channel longer pausing that channel. Please refer FCRX definition more information. PAUSED0 PAUSED1 updated rising edge RFCLK.
Table Microprocessor Interface Name Type Input Function Active-low chip select signal during PM3386 register accesses. required (i.e., registers accesses controlled using signals only), must connected tied low. Input Active-low read enable signal during PM3386 register read accesses. PM3386 drives D[15:0] with contents addressed register while low.
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Name
Type Input
Function Active-low write strobe signal during PM3386 register write accesses. D[15:0] contents clocked into addressed register rising edge while low.
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10]
Input
bi-directional data D[15:0] used during PM3386 register read write accesses.
Address A[10:0] selects specific registers during PM3386 register accesses.
Input Internal pull-up
Address latch enable active-high latches address A[10:0] when low. When high, internal address latches transparent. allows PM3386 interface multiplexed address/data bus. integral pull-up resistor.
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Name INTB
Type Output Open Drain
Function Active-low interrupt INTB when PM3386 interrupt source active that source unmasked. PM3386 enabled report many alarms events interrupts. INTB tri-stated when interrupt acknowledged appropriate register access. INTB open drain output.
Table Name RSTB
Device Miscellaneous Type Schmitt input Internal pull-up Description Master Reset This active reset signal input provides asynchronous reset device. RSTB Schmitt triggered input with internal pull-up resistor. When RSTB forced low, device registers forced their default states. Physical Medium Select These active high signals select between using on-board SERDES external transceiver GMII pins. (tied VSS) will select internal SERDES. high (tied VDDO) will select external transceiver GMII pins. These pins required tied VDDO prior device power
PMD_SEL0 PMD_SEL1
Input Internal pull-down
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Table Name
JTAG Test Access Port (TAP) Signals Type Input Description JTAG Test Clock JTAG test clock (TCK) signal provides clock timing test operations that carried using IEEE P1149.1 test access port. must tied VDDO when JTAG test.
Input Internal pull-up
JTAG Test Mode Select controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. internal pull resistor.
Input Internal pull-up
JTAG test Input carries test data into PM3386 IEEE P1149.1 test access port. sampled rising edge TCK. internal pull-up resistor JTAG Test Output carries test data PM3386 IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when progress shifting boundary scan data out. JTAG Test Reset TRSTB provides asynchronous reset testing IEEE P1149.1 test access port. TRSTB Schmitt triggered input with internal put-up resistor. Note that when being used JTAG testing TRSTB must connected RSTB input proper normal mode operation.
Output
TRSTB
Schmitt Input Internal pull-up
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Table Name VDDI
Power Grounds Type Power Function AA23 AC22 AC20 AC16 AC11 1.8V Digital power core logic
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Name VDDO
Type Power
Function AC14 AC19 AC23 AD24 AE25 AB24 AC24 3.3V Digital power
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Name VDDQ
Type Power
Function AC15 3.3V Digital Quite power
AVDH
Analog Power
3.3V Analog power analog cells. Insure these inputs connected welldecoupled +3.3V supply.
AVDL
Analog Power
1.8V Analog power analog cells. Insure these inputs connected welldecoupled +1.8V supply.
AVDQ
Analog Power
3.3V Analog Quite power analog cells. Insure these inputs connected well-decoupled +3.3V supply.
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Name
Type Ground
Function Device ground AF13 AF14 AE24 AF25 AF26 AE26 AD25 AD26 AC25 AC26 AB26 AF15
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Notes Description: PM3386 inputs bi-directional signals present minimum capacitive loading operate logic levels except inputs marked Analog PECL. GTX_CLK0, GTX_CLK1, TXD0[7:0], TXD1[7:0], TX_ER0, TX_ER1, TX_EN0, TX_EN1, MDC, MDIO, STPA, PTPA, DTPA[1:0], RVAL, RDATA[31:0], RPRTY, RMOD[1:0], RSOP, REOP, RERR, RSX, PAUSED0, PAUSED1, D[15:0], INTB, outputs have drive capability. digital inputs tolerant. PECL inputs outputs should terminated passive network interface PECL levels described Operations section. mandatory that every ground (VSS) connected printed circuit board ground plane ensure reliable device operation. mandatory that every digital power (VDDI, VDDO, VDDQ) connected printed circuit board power planes ensure reliable device operation. analog power pins sensitive noise. They must isolated from digital power. Care must taken correctly decouple these pins. mandatory that every analog power (AVDL, AVDH, AVDQ) de-coupled from connected printed circuit board power planes ensure reliable device operation. protection structures pads necessary exercise caution when powering device down. protection devices behave diodes between power supply pins from pins power supply pins. Under extreme conditions possible damage these protection devices trigger latch Please adhere recommended power supply sequencing described Operation section this document.
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FUNCTIONAL DESCRIPTION PM3386 provides high density power solution implementing Gigabit Ethernet connectivity. PM3386 dual Gigabit Ethernet controller with integrated SERDES GMAC functions connecting standard POSPHY Level system interface. PM3386 accepts serial streams from optical transceiver devices Gigabit Ethernet devices performs Media Access Control frame verification. Statistics maintained frame forwarded internal FIFOs POS-PHY Level interface. PM3386 connected upper layer device POS-PHY Level interface classification forwarding. PM3386 partitioned into following major functional blocks. operation each block described more detail subsequent sections. SERDES Enhanced Gigabit Media Access Control Ethernet Statistics Address Filtering POS-PHY Level System Interface Microprocessor Interface
10.1
Serializer-Deserializer (SERDES) PM3386 internal serializer-deserializer transceivers. SERDES IEEE 802.3-1998 Gigabit Ethernet compatible supporting gigabit data transfer flows. SERDES based X3T11 specification. PECL cells used implement SERDES capable both 3.3V voltage PECL operation they coupled within system design. transmitter section SERDES accepts 10-bit wide parallel data serializes this data into high-speed serial data stream. parallel data 8B/10B encoded data. internally generated reference clock then multiplied generate 1250 serial clock used clock encoded data high-speed output rate 1250 Mbit/s. high-speed outputs capable interfacing directly separate fiber optic module optical transmission.
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receiver section accepts serial electrical data stream 1250 Mbit/s recovers original 10-bit wide parallel data. receiver Clock Recovery Unit (CRU) locks onto incoming serial signal facilitates recovery high-speed serial data. serial data converted back into 10-bit parallel data, recognizing 8B/10B comma character establish byte alignment. recovered parallel data presented EGMAC. 10.2 Enhanced Gigabit Media Access Control (EGMAC)
10.2.1 EGMAC General PM3386 integrates standard IEEE 802.3-1998 Gigabit Ethernet Media Access Control interfaces connection internal serializer-deserializers (SERDES) external transceivers using Gigabit Media Independent Interface (GMII) pins each gigabit Ethernet port. dual ports PM3386 capable operation either SERDES GMII mode. ports configured operate independently from each other using PMD_SEL0 PMD_SEL1 pins. EGMAC capable supporting normal Ethernet frame sizes 1518 bytes, VLAN tagged frame sizes 1522 bytes, Jumbo frames sizes 9.6k bytes. Transmit Frame Length Receive Frame Length registers contain values associate with maximum accepted Ethernet frame sizes. default these registers contain value 1518 bytes. This allows normal frame sizes well 1522 VLAN tagged frames accepted. EGMAC will base frame length calculations statistics these registers. EGMAC takes into account VLAN tagging frames ensure their proper representation statistics gathering process. Note that possible program ingress egress maximum frame sizes separately. 10.2.2 EGMAC Egress Direction egress direction packet data from PL3EP presented EGMAC synchronizing transmit FIFO. EGMAC/PL3EP interface push style interface. packet data available transmit PL3EP will push (transfer) data EGMAC. PL3EP will notify EGMAC start packets using simple packet start packet indications. PL3EP will also present EGMAC error signal that asserted when error condition observed POS-PHY internal error encountered egress data path. EGMAC upper bound 9.6k bytes size egress frames. egress direction EGMAC accept packets minimum size bytes. Egress packets sent EGMAC that minimum bytes
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less than minimum byte frame length required 802.3-1998 have programmed option padded appropriately bytes bytes VLAN tagged frames) optionally have associated appended frame prior transmit. user also elect program EGMAC insert Frame Check Sequence (FCS) field. case that link device disregards flow control information provided DTPA0, DTPA1, STPA, PTPA continues write PM3386 attempt overflow egress FIFO PM3386 will truncate current packet when FIFO becomes full. this time PM3386 will wait until minimum packet accepted then resume data transfer. event that link device deliver data fast enough PM3386, placing PM3386 case FIFO underrun, current packet will truncated sending bytes currently available then PM3386 will resync TSOP. error cases CRC-32 that kept over packet will invalidated appended frame transmitted thereby signaling error. Following each frame transmission EGMAC provides statistical vector MSTAT block that updates statistic collection counters maintained system visible registers. Please refer MSTAT functional description Register section this document full list port statistics. 10.2.3 EGMAC Ingress Direction ingress direction SERDES GMII presents receive physical packet EGMAC. EGMAC scans preamble looking Start Frame Delimiter (SFD). default preamble stripped converting physical packet frame. EGMAC will then compare destination address frame address filtering logic given port. enabled address filtering logic programmed accept reject incoming frames. EGMAC also programmable accept frames regardless validity. EGMAC supports ingress frame sizes 9.6k bytes. EGMAC interfaces PL3IP using simple push style interface. EGMAC signals start frame frame while transferring data information PL3IP. There decision points which frame forwarding filtering decisions made. first decision point beginning ingress frame. this point once possible fields recognized frame filtered based address filter logic described later. frame forwarded incoming data will written
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EGMAC ingress FIFO preparation frame transfer. frame filtered frame will written EGMAC FIFO EGMAC will resync next incoming ingress frame. second decision point frame. EGMAC will perform frame integrity checks such length CRC. frame violates these integrity checks frame will need discarded. Discarding frame done possible ways. cases described below. number bytes that have been written EGMAC ingress FIFO less than programmed value within EGMAC Receive FIFO Forwarding Threshold register, frame entirety stored within FIFO, will therefore dropped within EGMAC. EGMAC will flush this frame from FIFO resume reception ingress traffic next start frame indication. number bytes that have been written EGMAC ingress FIFO greater than programmed value within EGMAC Receive FIFO Forwarding Threshold register frame will have started draining from FIFO therefore dropped within PM3386. this case frame will marked assertion RX_ERR EGMAC PL3IP interface. This indication carried POSPHY Level interface will cause assertion RERR last byte transfer packet. mentioned above ingress frames held receive FIFO within EGMAC until byte count exceeds forwarding threshold programmed EGMAC Receive FIFO Forwarding Threshold register until Frame (EOF). Frames that contain errors greater than programmed value within EGMAC Receive FIFO Forwarding Threshold register will marked erred PM3386 will discarded within PM3386. EGMAC will distinguish between unicast, broadcast, multicast frames. EGMAC programmed forwarded filter frames based unicast, broadcast, multicast type frames. 10.2.4 EGMAC Flow Control Control Sublayer PM3386 provides loss-less frame flow control frame sizes 9.6k bytes over 1000BASE 1000BASE 1000BASE implementations. EGMAC interface contains Control Sublayer which adheres IEEE 802.3-1998 provides support Control frames. EGMAC performs functions lined IEEE 802.3-1998 Clause "MAC Control" Annexes 31B. Clause introduces optional Control
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sublayer popular layer stack. This sublayer provides real-time control manipulation operation. clause defines control frames distinguishable their unique Length/Type field identifier. EGMAC supports Annex opcode PAUSE implementing Annex31B's frame based flow control scheme which utilizes PAUSE Control frames. purpose flow control slow down aggregate rate frames that other link sending. Finite FIFO depths have tendency overflow when line-rate frames being received upper layer device cannot keep Thus prevent overflow FIFOs, flow control used. Control client wishing inhibit transmission data frames from PM3386 generates PAUSE Control frame which contains reserved multicast address (01-80-C2-00-00-01), Control frame type field 88-08, PAUSE opcode, 00-01, pauseTimer, 16-bit value expressed pause quanta times. When EGMAC receives PAUSE Control frame, loads Pause Timer with value sent pauseTime filed. pauseTime nonzero FCRX within EGMAC GMACC1-Config Register asserted, EGMAC will pause from transmitting frames will wait pauseTime number slot times before resuming operation. however, pauseTime value equal zero, EGMAC allowed resume transmitting data frames. time EGMAC receiving PAUSE control frames EGMAC will assert PAUSED0 PAUSED1 status pins. These pins will held asserted until EGMAC pauseTime counts down zero EGMAC resumes transmitting data frames. possible depending system requirements allow ingress PAUSE Control frames processed processed EGMAC layer (see FCRX bit) PAUSE Control frames dropped EGMAC layer passed upper layer device(see PASS_CTRL bit). reason upstream device needs stop incoming frames, accomplish this four different ways. First, upper layer device send 802.3-1998 PAUSE Control frames own. Second, upper layer device assert PAUSE0 PAUSE1 pins device have EGMAC automatically send PAUSE Control frames. Third, system processor initiate PAUSE operation configuration registers EGMAC. Fourth, link device de-assert RENB cause FIFO fill levels PL3IP block fill start automatic flow control. Note that even though EGMAC sending egress PAUSE Control frames ingress channel will still operational with exception normal blocking POS-PHY data-path from link level. Please refer Operations section under PAUSE Flow Control programming options. PAUSE operation PM3386 will send PAUSE frame with null Pause Timer value allowing quick PAUSE signaling downstream devices.
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10.2.5 EGMAC Auto-Negotiation EGMAC implements Clause IEEE 802.3-1998 Standard, AutoNegotiation function, type 1000BASE-X. Auto-Negotiation 1000BASE-X function provides means exchange information between devices that share link segment allowing management ability configure both devices such that takes maximum advantage their capabilities. After reset occurs EGMAC senses whether Auto-Negotiation enabled. EGMAC will start Auto-Negotiation exactly following state diagram outlined 802.3-1998 Clause Base page Auto-Negotiation therefore completely taken care EGMAC. Above base page Auto-Negotiation, EGMAC communicates between host processor external physical device means wire interface. EGMAC block produces clock (MDC) general MDIO. host controls EGMAC management registers.
10.2.6 EGMAC Address Filter Logic EGMAC provides rich address filtering options. host microprocessor complete programmable access filtering features. EGMAC perform separate exact-match MAC/VID unicast filter operations. Each unicast filter will perform exact match either optional exact match VID. enabled, each unicast filter channel programmed indicate ACCEPT DISCARD upon match. Each unicast filter channel enabled separately. EGMAC also includes 64-bin hash-based multicast filter. This hash-based filter utilizes 6-bits CRC-32 output taken over provide standard imperfect multicast filtering capability. multicast filter output will asserted only IEEE Group/Functional frame (Most significant least significant byte DA). enabled, filter output will indicate ACCEPT only. enabled, will indicate nothing.
10.3
Management Statistics (MSTAT) MSTAT block used accumulate Ethernet specific counts used supporting management agents such RMON, SNMP, Etherlike interfaces. MSTAT provides counter width support compliance with 802.3-1998
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rollover requirements minutes. MSTAT supports full system probing with counter snapshotting shadow registers. Incorporated into MSTAT block fully programmable interrupt array enabling counter rollover monitoring with interrupt reporting.
10.4
POS-PHY Level Physical Layer Interface
10.4.1 POS-PHY Level General PM3386 connect single upper level device through POS-PHY Level Interface. POS-PHY Level interface 32-bits wide interface with clock rate MHz. POS-PHY Level developed with cooperation SATURN Development Group cover application rates including Gbit/s. POS-PHY Level specification defines requirements interoperation between devices such multi-PHY PM3386 single Link Layer device. Each channel within PM3386 contains byte ingress byte egress POS-PHY latency FIFO. 10.4.2 POS-PHY Level Ingress Physical Layer Interface (PL3IP) POS-PHY slave device, hence ingress receive direction, PM3386 outputs received packets upper layer device whenever data available. interface accepts read clock (RFCLK) read enable signal (RENB) when data read from ingress FIFO (using rising edge RFCLK). start packet (RSOP) marks first byte received packet data RDAT[31:0] bus. RPRTY signal reports parity RDAT[31:0] bus. Parity defaults programmed even parity. packet indicated REOP signal. RERR signal provided indicate that error received packet occurred. RVAL signal used indicate when RSOP, REOP, RERR, RDAT[31:0] valid. indicates start transfer marks clock cycle where in-band channel address given RDAT[31:0] bus. event that upper level device cannot accept data de-assert RENB. this point specific port's POS-PHY interface ingress byte FIFO will start fill When FIFO exceeds programmed high water mark flow control threshold ingress FIFO will assert indication EGMAC start PAUSE flow control. ingress POS-PHY FIFO will continue keep flow control signal high until number entries FIFO have decreased programmed water mark flow control threshold level.
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event that link layer device does re-assert RENB continue data flow PM3386 will buffer incoming frames from line side interface until buffer facilities within PM3386 exhausted. this time PM3386 will longer accept data from line side. data bits will dropped line interface until resources within PM3386 become available. this time PM3386 will re-sync physical packet continue reception. event that PM3386 truncates frame because resource exhaustion frame will marked erred asserting RERR last interface transaction packet transfer specified protocol. POS-PHY ingress FIFO will absorb in-flight frames when PM3386 placed into PAUSE flow control state from upper level device. FIFO will accept number maximum size 9.6k byte frames without loss. scheduling packets through ingress POS-PHY interface controlled simple round robin approach that fairly switches between both Gigabit Ethernet channels. POS-PHY bursts packets across interface using programmable burst sizes. 10.4.3 POS-PHY Level Egress Physical Layer Interface (PL3EP) POS-PHY Level compliant interface consists write clock (TFCLK), write enable signal (TENB), start packet (TSOP) indication, packet (TEOP) indication, erred packet (TERR) indication, parity (TPRTY). PM3386 supports three POS-PHY Level egress status modes. STPA signal reports selected egress FIFO's fill status. PTPA signal shows FIFO fill status polled channel. DTPA[1:0] signal pins show direct FIFO fill status per-channel basis. signal indicates when in-band channel selection given TDAT[7:0] pins. This done beginning each transfer sequence. in-band address does equal subsequent data transfers TENB will dropped. TMOD[1:0] signal provided indicate whether bytes valid final word transfer packet(TEOP asserted). packet aborted asserting TERR signal packet. egress direction PM3386 collects packets into PM3386 egress FIFO delays data transfer PM3386 EGMAC transmission until number bytes gathered equal greater than PL3EP Channel Minimum Frame Size register until packet (via TEOP) signaled. Each packet must satisfy forwarding conditions prior
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transmission. This allows programmable underrun protection depending upon application. 10.5 Microprocessor Interface PM3386 uses simple multiplexed non-multiplexed microprocessor interface that commonly found PMC-Sierra devices. PM3386 supports complete accessibility internal resources from host microprocessor. This allows host read write host accessible registers chip data structures. 10.6 JTAG Test Access Port Interface JTAG Test Access Port block provides JTAG support boundary scan. standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE STCTEST instructions supported. PM3386 identification code 033860CD hexadecimal.
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NORMAL MODE REGISTER DESCRIPTION This section describes normal mode registers device. Table PM3386 General Memory Group PL3IP PL3EP EGMAC EGMAC MSTAT MSTAT SERDES Address Range (Hex) 0x100 0x14F 0x200 0x24B 0x300 0x376 0x400 0x476 0x500 0x5E9 0x600 0x6E9 0x700 0x71F
Table
PM3386 Specific Memory Register Level Registers Identification Register Product Revision Register Reset Control Register Interrupt Status Register Device Status Register Reference Lock Status Register Data Lock Status Register Software Resource Register
Address (Hex)
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Address (Hex) 0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107 0x108 0x11f Channel 0x120 0x121 0x122 0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x21f Channel 0x220 0x221 Channel 0x240 0x241 Channel 0x140 0x141 0x142 Reserved PL3IP Interrupt Status PL3IP Interrupt Mask
Register PL3IP Common Configuration Registers
PL3IP Configuration Register PL3IP Equalization Threshold Limit PL3IP Equalization Difference Limit Reserved Reserved Reserved PL3IP Channel Specific Registers PL3IP Channel High Watermark PL3IP Channel Watermark PL3IP Channel Packet Burst Mask Reserved PL3EP Interrupt Status PL3EP Interrupt Mask PL3EP Configuration Register Reserved Reserved Reserved Reserved PL3EP Channel Specific Registers PL3EP Channel FIFO Reserve PL3EP Channel Minimum Frame Size
PL3EP Common Configuration Registers
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Address (Hex)
Register EGMAC Registers
Channel 0x300 0x301 0x302 0x303 0x304 0x305 0x306 0x307 0x308 0x309 0x30A 0x30C 0x310 0x316 0x318 0x31A 0x31C 0x31D 0x31E 0x31F 0x320 0x322 0x324 0x326 0x328 0x332
Channel 0x400 0x401 0x402 0x403 0x404 0x405 0x406 0x407 0x408 0x409 0x40A 0x40C 0x410 0x416 0x418 0x41A 0x41C 0x41D 0x41E 0x41F EGMAC GMACC0: Config Register Word EGMAC GMACC0: Config Register High Word EGMAC GMACC1: Config Register Word EGMAC GMACC1: Config Register High Word EGMAC GMACC2: Config Register Word EGMAC GMACC2: Config Register High Word EGMAC GPCSC: Config Word EGMAC GPCSC: Config High Word EGMAC Station Address [15:0] EGMAC Station Address [31:16] EGMAC Station Address [47:32] EGMAC TPID: VLAN Register EGMAC RX_MAXFR: Receive Frame Length Reserved EGMAC ANCTL: Auto-Negotiation Control EGMAC ANSTT: Auto-Negotiation Status EGMAC ANADV: Auto-Negotiation Advert word EGMAC ANADV: Auto-Negotiation Advert high word EGMAC ANLPA: Auto-Neg Link Part Able word EGMAC ANLPA: Auto-Neg Link Part Able high word EGMAC MCMD: Managment Command EGMAC MADR: Management Address EGMAC MWTD: Management Write Data EGMAC MRDD: Management Read Data EGMAC MIND: Management Indicators 0x432 EGMAC Transmit Control
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Address (Hex) 0x333 0x334 0x335 0x336 0x337 0x338 0x339 0x33A 0x33B 0x33C 0x33D 0x33E 0x33F 0x340 0x341 0x342 0x343 0x344 0x345 0x346 0x347 0x348 0x349 0x34A 0x34B 0x34C 0x34D 0x34E 0x433 0x434 0x435 0x436 0x437 0x438 0x439 0x43A 0x43B 0x43C 0x43D 0x43E 0x43F 0x440 0x441 0x442 0x443 0x444 0x445 0x446 0x447 0x448 0x449 0x44A 0x44B 0x44C 0x44D 0x44E EGMAC: Control register
Register EGMAC: PAUSE Timer register EGMAC: PAUSE Interval register EGMAC: Transmit Frame Length EGMAC: Receive FIFO Forwarding Threshold Reserved EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register
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Address (Hex) 0x34F 0x350 0x351 0x352 0x353 0x354 0x355 0x356 0x357 0x358 0x359 0x35A 0x35B 0x35C 0x35D 0x35E 0x35F 0x360 Channel 0x500 0x501 0x502 0x503 0x504 0x505 0x506 0x507 0x44F 0x450 0x451 0x452 0x453 0x454 0x455 0x456 0x457 0x458 0x459 0x45A 0x45B 0x45C 0x45D 0x45E 0x45F 0x460 Channel 0x600 0x601 0x602 0x603 0x604 0x605 0x606 0x607 MSTAT: Control
Register EGMAC: Exact Match Address Register EGMAC: Exact Match Address Register EGMAC: Exact Match Register EGMAC: Exact Match Register EGMAC: Exact Match Register EGMAC: Exact Match Register EGMAC: Exact Match Register EGMAC: Exact Match Register EGMAC: Exact Match Register EGMAC: Exact Match Register EGMAC: Multicast Hash Word Register EGMAC: Multicast Hash MidLow Word Register EGMAC: Multicast Hash MidHigh Word Register EGMAC: Multicast Hash High Word Register EGMAC: Address Filter Control Register EGMAC: Address Filter Control Register EGMAC: Address Filter Control Register EGMAC: Address Filter Control Register MSTAT Registers
MSTAT: Counter Rollover MSTAT: Counter Rollover MSTAT: Counter Rollover MSTAT: Counter Rollover MSTAT: Interrupt Mask MSTAT: Interrupt Mask MSTAT: Interrupt Mask
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Address (Hex) 0x508 0x509 0x50A 0x50B 0x50C 0x50D0x50F 0x510 0x511 0x512 0x514 0x515 0x516 0x518 0x519 0x51A 0x51C 0x51D 0x51E 0x520 0x521 0x522 0x524 0x525 0x526 0x608 0x609 0x60A 0x60B 0x60C 0x60D0x60F 0x610 0x611 0x612 0x614 0x615 0x616 0x618 0x619 0x61A 0x61C 0x61D 0x61E 0x620 0x621 0x622 0x624 0x625 0x626 MSTAT: Interrupt Mask
Register MSTAT Counter Write Address MSTAT Counter Write Data MSTAT Counter Write Data Middle MSTAT Counter Write Data High Reserved MSTAT Counter Registers High High High High High High MulticastFramesReceivedOK UnicastFramesReceivedOK OctetsReceived FramesReceived OctetsReceivedOK FramesReceivedOK
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Address (Hex) 0x528 0x529 0x52A 0x52C 0x52D 0x52E 0x530 0x531 0x532 0x534 0x535 0x536 0x538 0x539 0x53A 0x53C 0x53D 0x53E 0x540 0x541 0x542 0x544 0x545 0x546 0x548 0x549 0x54A 0x628 0x629 0x62A 0x62C 0x62D 0x62E 0x630 0x631 0x632 0x634 0x635 0x636 0x638 0x639 0x63A 0x63C 0x63D 0x63E 0x640 0x641 0x642 0x644 0x645 0x646 0x648 0x649 0x64A High High High High High High High High High Reserved SymbolError
Register BroadcastFramesReceivedOK
TaggedFramesReceivedOK
PAUSEMACControlFrameReceived
MACControlFrameReceived
FrameCheckSequenceErrors
FramesLostDueToInternalMACError
InRangeLengthErrors
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Address (Hex) 0x54C 0x54D 0x54E 0x550 0x551 0x552 0x554 0x555 0x556 0x558 0x559 0x55A 0x55C 0x55D 0x55E 0x560 0x561 0x562 0x564 0x565 0x566 0x568 0x569 0x56A 0x56C 0x56D 0x56E 0x64C 0x64D 0x64E 0x650 0x651 0x652 0x654 0x655 0x656 0x658 0x659 0x65A 0x65C 0x65D 0x65E 0x660 0x661 0x662 0x664 0x665 0x666 0x668 0x669 0x66A 0x66C 0x66D 0x66E High High High High High High High High High Fragments Jabbers
Register FramesTooLongErrors
UndersizedFrames
ReceiveFrames64Octets
ReceiveFrames65to127Octets
ReceiveFrames128to255Octets
ReceiveFrames256to511Octets
ReceiveFrames512to1023Octets
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Address (Hex) 0x570 0x571 0x572 0x574 0x575 0x576 0x578 0x579 0x57A 0x57C 0x57D 0x57E 0x580 0x581 0x582 0x584 0x585 0x586 0x588 0x589 0x58A 0x590 0x591 0x592 0x594 0x595 0x596 0x670 0x671 0x672 0x674 0x675 0x676 0x678 0x679 0x67A 0x67C 0x67D 0x67E 0x680 0x681 0x682 0x684 0x685 0x686 0x688 0x689 0x68A 0x690 0x691 0x692 0x694 0x695 0x696 High High High High High High High High High FilteredOctets
Register ReceiveFrames1024to1518Octets
ReceiveFrames1519toMAXOctets
JumboOctetsReceivedOK
FilteredUnicastFrames
FilteredMulticastFrames
FilteredBroadcastFrames
FramesTransmittedOK
OctetsTransmittedOK
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Address (Hex) 0x598 0x599 0x59A 0x59C 0x59D 0x59E 0x5A0 0x5A1 0x5A2 0x5A4 0x5A5 0x5A6 0x5A8 0x5A9 0x5AA 0x5AC 0x5AD 0x5AE 0x5B0 0x5B1 0x5B2 0x5B4 0x5B5 0x5B6 0x5B8 0x5B9 0x5BA 0x698 0x699 0x69A 0x69C 0x69D 0x69E 0x6A0 0x6A1 0x6A2 0x6A4 0x6A5 0x6A6 0x6A8 0x6A9 0x6AA 0x6AC 0x6AD 0x6AE 0x6B0 0x6B1 0x6B2 0x6B4 0x6B5 0x6B6 0x6B8 0x6B9 0x6BA High High High High High High High High High OctetsTransmitted
Register
TransmitSystemError
UnicastFramesTransmittedOK
MulticastFramesTransmittedOK
BroadcastFramesTransmittedOK
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Address (Hex) 0x5BC 0x5BD 0x5BE 0x5C0 0x5C1 0x5C2 0x5C4 0x5C5 0x5C6 0x5C8 0x5C9 0x5CA 0x5CC 0x5CD 0x5CE 0x5D0 0x5D1 0x5D2 0x5D4 0x5D5 0x5D6 0x5D8 0x5D9 0x5DA 0x5DC 0x5DD 0x5DE 0x6BC 0x6BD 0x6BE 0x6C0 0x6C1 0x6C2 0x6C4 0x6C5 0x6C6 0x6C8 0x6C9 0x6CA 0x6CC 0x6CD 0x6CE 0x6D0 0x6D1 0x6D2 0x6D4 0x6D5 0x6D6 0x6D8 0x6D9 0x6DA 0x6DC 0x6DD 0x6DE High High High High High High High High High
Register PAUSEMACCTRLFramesTransmitted
MACCTRLFramesTransmitted
TransmittedFrames64Octets
TransmittedFrames65to127Octets
TransmittedFrames128to255Octets
TransmittedFrames256to511Octets
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Address (Hex) 0x5E0 0x5E1 0x5E2 0x700 0x701 0x702 0x703 0x704 0x705 0x706 0x707 0x708 0x713 0x714 0x715 0x716 0x717 0x718 0x6E0 0x6E1 0x6E2 High SERDES
Register JumboOctetsTransmittedOK
SERDES Lock Detect Change SERDES Lock Detect Mask Reserved SERDES Port Configuration Reserved SERDES Port Mode Reserved Reserved SERDES Port Mode
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Register 0x0H: Identification Register ID[15:0]: Identification register presents valid product number device. This register read only. default value 3386. Type Function ID[15] ID[14] ID[13] ID[12] ID[11] ID[10] ID[9] ID[8] ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] Default
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Register 0x1H: Product Revision Register 15:0 Type Function Revision Default
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Revision
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This register read only. This register presents current device revision
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Register 0x2H: Reset Control Register 15:7 Type Function Reserved RESET_PL3EPB RESET_PL3IPB DIS_STRETCH Reserved ARESETB DRESETB Default
Reset Control Register generates reset source output used blocks PM3386. DRESETB: Master digital device reset. Performing hardware reset will clear this Setting this will cause digital portion device reset. responsibility programmer de-assert this order perform proper software reset sequence. Please refer operations section this document instructions concerning resetting this device using software. ARESETB: Master analog device reset. Performing hardware reset will clear this Setting this will cause analog portion device reset. responsibility programmer de-assert this order perform proper software reset sequence. Please refer operations section this document instructions concerning resetting this device using software. DIS_STRETCH: default internal digital reset held asserted approximately 10ms after de-assertion RSTB pin. disable this delay DIS_STRETCH logic This will terminate internal digital reset delay. default this disabled. Please refer operations section further information.
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RESET_PL3IPB: This allows software reset PL3IP logic. default this asserted logic reset PL3IP programmer must this logic wait minimum (there maximum), then this back logic RESET_PL3EP: This allows software reset PL3EP logic. default this asserted logic reset PL3EP programmer must this logic wait minimum (there maximum), then this back logic
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Register 0x3H: Interrupt Status Register 15:6 X_INT: Interrupt indication bits. Theses bits indicate that given interrupt currently active. general this global interrupt status indication. Simply reading this register does clear interrupt. Each interrupt source have requirements clearing interrupt condition. Further specification each interrupt found Operation section this document. logical X_INT signals produces active INTB signal used notify external processor interrupt condition. following table provides block source interrupt mask registers that make level interrupt bits listed above. Type Function Reserved DOOL_INT ROOL_INT Reserved Reserved PL3EP_INT PL3IP_INT MSTAT1_INT MSTAT0_INT Default
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Table Level Interrupt DOOL_INT ROOL_INT PL3EP_INT PL3IP_INT MSTAT1_INT
Interrupt Resource Mapping Block Level Interrupt Register (Interrupt Source) Register 0x700 Bits[1:0] Register 0x700 Bits[15],[9:8] Register 0x201 Bits[7:0] Register 0x101 Bits[15:0] Register 0x601 Bits[15], [13:0] Register 0x602 Bits[14:0] Register 0x603 Bits[15:0] Register 0x604 Bits[5:0] Register 0x501 Bits[15], [13:0] Register 0x502 Bits[14:0] Register 0x503 Bits[15:0] Register 0x504 Bits[5:0] Block Level Interrupt Mask Register Register 0x701 Bits[1:0] Register 0x701 Bits[15],[9:8] Register 0x202 Bits[7:0] Register 0x102 Bits[15:0] Register 0x605 Bits[15],[13:0] Register 0x606 Bits[14:0] Register 0x607 Bits[15:0] Register 0x608 Bits[5:0] Register 0x505 Bits[15],[13:0] Register 0x506 Bits[14:0] Register 0x507 Bits[15:0] Register 0x508 Bits[5:0]
MSTAT0_INT
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Register 0x4H: Device Status Register 13:6 Type Function Reserved Reserved Reserved DLL1_ERR DLL1_RUN Reserved Reserved DLL0_ERR DLL0_RUN Default
Device Status Register provides ability monitor device operation. DLL0_RUN: DLL0 status (DLL0_RUN) indicates DLL0 locked reference clock RFCLK input (Active high). DLL0_ERR: DLL0 error status (DLL0_ERR) indicates DLL0 delay line achieve lock (Active High). DLL1_RUN DLL1 status (DLL1_RUN) indicates DLL1 locked reference clock (TFCLK_TREE) input (Active High).
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DLL1_ERR:
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DLL1 error status (DLL1_ERR) indicates DLL1 delay
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Register 0x5H: Reference Lock Status Register 14:2 Type Function TX_ROOL Reserved RX_ROOL1 RX_ROOL0 Default
Reference Lock Status Register provides information from SERDES blocks device. RX_ROOL0: Receive Reference Lock Condition Channel (Active logic receive clock trained reference frequency. RX_ROOL1: Receive Reference Lock Condition Channel (Active logic receive clock trained reference frequency.
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TX_ROOL:
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Transmit Reference Lock Condition (Active logic transmit clock trained reference frequency. ports share single
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Register 0x6H: Data Lock Status Register 15:2 Type Function Reserved RX_DOOL1 RX_DOOL0 Default
Data Lock Status Register provides information SERDES block device. RX_DOOL0: Receive Data Lock Condition Channel (Active logic receive clock aligned selected data steam.
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RX_DOOL1:
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Receive Data Lock Condition Channel (Active logic receive
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Register 0x7H: Software Resource Register 15:0 User_Defined: Software Resource register does control internal function within PM3386. This register reset. This register read/writeable software. Type Function User_Defined Default
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Register 0x101H: PL3IP Interrupt Status 12-8 Type Function IP_IS[15] Reserved IP_IS[13] Reserved IP_IS[7] Reserved IP_IS[5] Reserved Default
PL3IP Interrupt Status register used capture error status bits from both channels. This register used conjunction with PL3IP Interrupt Mask register. This register read only user. read this register will clear register interrupt. IP_IS[5] Channel Software Programmed Fault software programmed fault occurs when user programs PL3IP Channel Watermark Register 0x121 larger value than PL3IP Channel High Watermark Register 0x120. IP_IS[7] Channel Equalization Indication Indicates that some time during operation PL3IP that equalization this channel activated. IP_IS[13] Channel Software Programmed Fault software programmed fault occurs when user programs PL3IP Channel Watermark Register 0x141 larger value then PL3IP Channel High Watermark Register 0x140. IP_IS[15] Channel Equalization Indication Indicates that some time during operation PL3IP that equalization this channel activated.
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Register 0x102H: PL3IP Interrupt Mask 12-8 Type Function IP_IM[15] Reserved IP_IM[13] Reserved IP_IM[7] Reserved IP_IM[5] Reserved Default
PL3IP Interrupt Mask register used mask errors when determining when send interrupt. location will enable corresponding interrupt notification unmasking possible pending interrupt. This user programmable register. IP_IM[5] Channel Software Programmed Fault Mask Mask error type specified corresponding location Pl3IP Interrupt Status register. IP_IM[7] Channel Equalization Indication Mask Mask indication type specified corresponding location Pl3IP Interrupt Status register. IP_IM[13] Channel Software Programmed Fault Mask Mask error type specified corresponding location Pl3IP Interrupt Status register. IP_IM[15] Channel Equalization Indication Mask Mask indication type specified corresponding location Pl3IP Interrupt Status register.
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Register 0x103H: PL3IP Configuration Register Type Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved IP_CR[7] IP_CR[6] IP_CR[5] IP_CR[4] IP_CR[3] IP_CR[2] IP_CR[1] IP_CR[0] Default
PL3IP Configuration Register controls enabling disabling features PL3IP. Writing non-reserved location will cause feature enabled. IP_CR[0] Channel Protocol Check Enable This turns protocol checking feature does allow corrupted packets written into FIFO. Disabling this feature useful system diagnostics. High off. IP_CR[1] Channel Protocol Check Enable This turns protocol checking feature does allow corrupted packets written into FIFO. Disabling this feature useful system diagnostics. High off.
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IP_CR[2] Enable Equalized Transfer Mode Enable equalized transfer mode. When enabled, threshold register limit register will used evaluate state both channels. IP_CR[3] Parity Even Generation Parity Generation mode PL3IP. default mode parity generation (0). high (1), even mode parity generation will used. Once set, same mode used both channels. IP_CR[5:4] RFCLK Transfer Selection Bits [5:4] used transfer selection POS-PHY interface. rate programmable from RFCLK cycles. This will allow user program latency between selection channel transmitting packet. Table 11-14: Transfer Rate IP_CR[5:4] 00(Default) IP_CR[6] Pause Mode Selection Pause Mode Selection controls PAUSE0 PAUSE1 pins used. Pause Mode Selection (default) PAUSE0 PAUSE1 inputs control PAUSE frame generation their respective channels. Setting PAUSE0 PAUSE1 high will cause PM3386 start sending pause frames their corresponding channels described Operations section. Setting PAUSE0 PAUSE1 low, PM3386 previously sending PAUSE frames, PM3386 will send xoff PAUSE frame that channel. Pause Mode Selection high PAUSE0 PAUSE1 pins masked from directly effecting PAUSE frame generation. this case when user asserts PAUSE0 PAUSE1 pins respective channel will finish sending remaining number bytes programmed
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Transfer Rate RFCLKs RFCLKs RFCLKs RFCLKs
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minimum burst size until detected then hold sending data channel until PAUSE0 PAUSE1 pins de-asserted. Upon deassertion, available, data will continue transferred across interface that channel. Please refer Operation section more detail this feature. IP_CR[7] Channel Enable Channel Enable used update configuration values into PL3IP when required configuration change. differing PL3IP configuration registers (0x104, 0x105, 0x120, 0x121, 0x122, 0x140, 0x141, 0x142) written time will only update when this cleared. user programs PL3IP configuration registers then writes zero this update registers within PL3IP. This will automatically return when update complete.
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Register 0x104H: PL3IP Equalization Threshold Limit Type Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IP_ETL[2] IP_ETL[1] IP_ETL[0] Default
PL3IP Equalization Threshold Limit used when equalized transfer mode enabled. This register written time only updated internally using PL3IP Configuration register. IP_ETL[2:0] PL3IP Threshold Limit Register used upper limit bytes equalization support. Please refer Operations section more information equalization. Table provides programmable options.
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Table
Equalization Threshold Limits IP_ETL[2:0] (default) Equalization Threshold Limit 1024 2048 4096 8192 16384 32768 32768
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Register 0x105H: PL3IP Equalization Difference Limit Type Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IP_EDL[2] IP_EDL[1] IP_EDL[0] Default
PL3IP Equalization Difference Limit Register used when equalized transfer mode enabled. This register written time only updated using PL3IP Configuration register. IP_EDL[2:0] PL3IP Equalization Difference Limit used maximum difference bytes between channels FIFOs. Default 32768 bytes, FIFO storage space. lower limit supported hardware bytes. Please refer Operations section more information equalization. Table provides accepted programmable options.
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Table
Equalization Difference Limits IP_EDL[2:0] Equalization Difference Limit 1024 2048 4096 8192 16384 32768 32768
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Register 0x120H, 0x140H: PL3IP Channel High Watermark Type Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IP_PHWM[3] IP_PHWM[2] IP_PHWM[1] IP_PHWM[0] Default
PL3IP High Watermark register written time only updated using PL3IP Configuration register. IP_PHWM[3:0] high water mark sets point which EGMAC begins transmit PAUSE frame enabled). minimum high watermark bytes. watermark will default 8192 bytes.
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Table
PL3IP Channel High Water Mark IP_PHWM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Channel High Water Mark bytes bytes bytes 1024 bytes 2048 bytes 4096 bytes 8192 bytes 16384 bytes 32768 bytes 65500 bytes 4096 bytes 4096 bytes 4096 bytes 4096 bytes 4096 bytes 4096 bytes
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Register 0x121H, 0x141H: PL3IP Channel Watermark 15-4 Type Function Reserved IP_PLWM[3] IP_PLWM[2] IP_PLWM[1] IP_PLWM[0] Default
PL3IP Channel Water Mark register written time only updated using PL3IP Configuration register. IP_PLWM[3:0] watermark sets lower limit that must reached before EGMAC will cease send PAUSE frames. minimum watermark bytes. watermark will default 2048 bytes. Table PL3IP Channel Water Mark IP_PLWM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Channel Water Mark bytes bytes bytes bytes 1024 bytes 2048 bytes 4096 bytes 8192 bytes 16384 bytes 32768 bytes 2048 bytes 2048 bytes 2048 bytes 2048 bytes 2048 bytes 2048 bytes
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Register 0x122H, 0x142H: PL3IP Channel Packet Burst Mask 15-4 Type Function Reserved IP_CFBM[3] IP_CFBM[2] IP_CFBM[1] IP_CFBM[0] Default
PL3IP Channel Packet Burst Mask register written time only updated upon channel update using PL3IP Configuration register. IP_CFBM[3:0] packet burst mask determines amount data transmitted channel before switching other channel. packet detected before burst limit reached, burst will terminate asserting REOP bus. Setting IP_CFBM enables store-andforward mode. PM3386 will store entire packet into ingress FIFO before transmission. entire packet will sent prior re-arbitration between channels. Table Channel Frame Burst Mask IP_CFBM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1XXX Channel Frame Burst Mask bytes bytes bytes bytes bytes bytes 1024 bytes 2048 bytes Burst till
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Register 0x201H: PL3EP Interrupt Status Type Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EP_IS[7] Reserved EP_IS[5] Reserved EP_IS[3] Reserved EP_IS[1] Reserved Default
PL3EP Interrupt Status register used capture error status bits from both PL3EP channels. This register used conjunction with PL3EP Interrupt Mask register. register read only. read this register will clear register. status register written same clock domain only written TSB. Reads this register asynchronous. EP_IS[1] Channel FIFO Truncate Truncation occurs when PL3EP de-asserts DPTA, STPA, PTPA Link Layer data continues sent beyond programmed limitation, filling locations PL3EP FIFO. PL3EP will truncate packet adding packet internally, assert internal TERR indication, ignore data presented externally until PL3EP FIFO capable accepting data.
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EP_IS[3] Channel TDAT Parity Error TPRTY reported from interface different than internally generated parity check this channel. EP_IS[5] Channel FIFO Truncate Truncation occurs when PL3EP de-asserts DPTA, STPA, PTPA Link Layer data continues sent beyond programmed limitation, filling locations PL3EP FIFO. PL3EP will truncate packet adding packet internally, assert internal TERR indication, ignore data presented externally until PL3EP FIFO capable accepting data. EP_IS[7] Channel TDAT Parity Error TPRTY reported from interface different than internally generated parity check this channel.
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Register 0x202H: PL3EP Interrupt Mask Type Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EP_IM[7] Reserved EP_IM[5] Reserved EP_IM[3] Reserved EP_IM[1] Reserved Default
PL3EP Interrupt Mask register used mask errors when determining when send interrupt. location other than reserved locations, will enable that type error cause interrupt. This programmable register. EP_IM[1] Channel FIFO Truncate Mask Mask error type specified corresponding location PL3EP Interrupt Status register. EP_IM[3] Channel TDAT Parity Error Mask Mask error type specified corresponding location PL3EP Interrupt Status register.
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EP_IM[5] Channel FIFO Truncate Mask Mask error type specified corresponding location PL3EP Interrupt Status register. EP_IM[7] Channel TDAT Parity Error Mask Mask error type specified corresponding location PL3EP Interrupt Status register.
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Register 0x203H: PL3EP Configuration Register Type Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EP_CR[3] EP_CR[2] EP_CR[1] EP_CR[0] Default
PL3EP Configuration Register controls enabling disabling features TSB. Writing non-reserved location will cause feature enabled. EP_CR[0] Parity Checking Enable TDAT[31:0] This feature will enable checking parity data from TDAT[31:0] bus. High off. EP_CR[1] even parity generation check mode Parity Check mode determine whether even mode parity check used across egress bus. default mode parity. Parity mode applies both channels.
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EP_CR[2] Channel Update Channel Update used update configuration values into PL3EP when required configuration change. differing PL3EP configuration registers (0x220, 0x221) written time will only update when this cleared. user programs PL3EP configuration registers then writes zero this update registers within channel. This will automatically return when update complete. EP_CR[3] Channel Update Channel Update used update configuration values into PL3EP when required configuration change. differing PL3EP configuration registers (0x240, 0x241) written time will only update when this cleared. user programs PL3EP configuration registers then writes zero this update registers within channel. This will automatically return when update complete.
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Register 0x220H, 0x240H: PL3EP Channel FIFO Reserve 15-3 Type Function Reserved EP_CTR[2] EP_CTR[1] EP_CTR[0] Default
PL3EP Channel FIFO Reserve register user programmable establish amount reserved FIFO space left once DPTA, STPA, PTPA have been de-asserted. default bytes. This register written time internal logic will only updated write update bits within PL3EP configuration register. EP_CTR[2:0] Table PM3386 FIFO Reserve Programming Options EP_CTR[2:0] Reserve Space bytes bytes bytes bytes bytes 1024 bytes 2048 bytes (default) 4096 bytes 8192 bytes
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Register 0x221H, 0x241H: PL3EP Channel Minimum Frame Size 15-3 Type Function Reserved EP_CMF[2] EP_CMF[1] EP_CMF[0] Default
Channel Minimum Frame Size register determines amount data gather prior transmitting data line side EGMAC. logic will compare frame size frame counter look count before pushing data FIFO. before minimum frame size met, PL3EP will send completed frame. default setting bytes data. This register written time internal logic will only updated write update bits within PL3EP Configuration register. EP_CMF[2:0] Table PM3386 Minimum Frame Size Programming Options EP_CMF[2:0] Minimum Frame Size bytes bytes (default) bytes bytes bytes 1024 bytes 2048 bytes 4096 bytes 12288 bytes
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Register 0x300H,0x400H: EGMAC GMACC0 Config Register Word MIIM: Mode select. reset MIIM takes value PMD_SELx pin. value logic selects GMII interface this channel. logic value selects SERDES/TBI interface this channel. L32B: Setting this will cause 32-bit transmit packet data looped back receive logic EGMAC. Clearing this results normal operation, both transmit receive. L10B: Setting this will cause 10-bit encoded transmit data looped back receive logic EGMAC. Clearing this results normal operation, both transmit receive. Please note that after updating this register software reset state logic required using SRST EGMAC GMACC0 Config Register High Word Register Type Function Reserved Reserved Reserved Reserved Reserved Reserved L10B L32B Reserved Reserved Reserved Reserved Reserved Reserved Reserved MIIM Default PMD_SEL
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Register 0x301H,0x401H: EGMAC GMACC0 Config Register High Word SRST: Soft Reset. Setting this will reset internal state EGMAC block load register settings from registers 0x300-0x305 0x400-0x405. Note: Registers 0x300-0x305 0x400-0x405 will retain their written value. This should whenever changes made register bits found register 0x300-0x305 0x400-0x405 except TXEN0 RXEN0 bits. reset update state first write SRST then write Note that address filter registers 0x339-0x35F 0x439-0x45F reset SRST bit. pre-update registers within PM3386 will always contain last loaded address filter information possible write register 0x360 0x460 Update restore PM3386 address filtering registers pre-software reset condition. Type Function SRST Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default
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Register 0x302H,0x402H: EGMAC GMACC1 Config Register Word FULLD: Full-Duplex. This always indicate that always Full-Duplex mode. PADEN: Enable. frames including field with bytes necessary) append thereby ensuring minimum frame size bytes. CRCEN: Enable. this have append each every frame transmits. Clear this when frames from system already have valid CRC. Note: Frames always checked valid CRC. FLCHK: Frame Length Check. this allow check length received frames. will then check frames whose length/type field represents valid length (46-1500 octets) comparing value length/type field actual data field length. Type Function Reserved Reserved Reserved LONGP Reserved FCRX FCTX PUREP Reserved Reserved FLCHK CRCEN Reserved Reserved PADEN FULLD Default
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PUREP: Pure Preamble. this cause EGMAC check content preamble field packet, ensuring data pattern 0x55. Clear this preamble c
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