ADP3421 DACOUT VID4 VID3 VID2 VID1 VID0 CURRENT LIMIT COMPARATOR

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ADP3421 DACOUT VID4 VID3 VID2 VID1 VID0 CURRENT LIMIT COMPARATOR

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Geyserville-Enabled DC-DC Converter Controller Mobile CPUs ADP3421
ADP3421
DACOUT VID4 VID3 VID2 VID1 VID0 CURRENT LIMIT COMPARATOR CORE CONTROLLER CLKDRV CLKFB IODRV CLOCK CONTROLLER LEVEL TRANSLATOR CORE COMPARATOR VHYS RAMP
FEATURES Meets Intel® Mobile Voltage Positioning Requirements Lowest Processor Dissipation Longest Battery Life Best Transient Containment Minimum Number Output Capacitors System Power Management Compliant Fast, Smooth Output Transition During Code Change Programmable Current Limit Power Good Integrated Controllers Clock Supplies Programmable UVLO Soft Start with Restart Lock-In APPLICATIONS Geyserville-Enabled Core DC-DC Converters Fixed Voltage Mobile Core DC-DC Converters Notebook/Laptop Power Supplies Programmable Output Power Supplies
CLSET
SOFT START TIMER POWER GOOD GENERATOR CORE
GENERAL DESCRIPTION
ADP3421 hysteretic dc-dc buck converter controller with auxiliary linear regulator controllers. ADP3421 provides total power conversion control solution microprocessor delivering core, I/O, clock voltages. optimized low-voltage design powered from system supply draws only maximum shutdown. main output voltage 5-bit code. accommodate transition time required newest processors on-thefly changes, ADP3421 features high-speed operation allow minimized inductor size that results fastest change current output. further allow minimum number output capacitors used, ADP3421 features active voltage positioning that optimally compensated ensure superior load transient response. main output signal interfaces with ADP3410 dual MOSFET driver, which optimized high speed high efficiency driving both upper lower (synchronous) MOSFETs buck converter.
IOFB
CONTROLLER
BIAS REFERENCE BIAS
UVLO
VIN/VCC MONITOR UVLO BIAS REFERENCE CONTROLLER PWRGD
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
ADP3421-SPECIFICATIONS1 10100 V,CV
VCORE VDAC, ROUT CLTB unless otherwise noted.)
Unit
VCC, VULVO
Parameter SUPPLY-UVLO-POWER GOOD Supply Current
Symbol ICC(ON) ICC(UVLO) VCCH ICCH VCCL VCCHYS VUVLOTH IUVLO VSDTH VCOREH(UP)1 VCOREH(DN)2 VCOREL(UP)1 VCOREL(DN)2 VPWRGD3
Conditions
VUVLO 1.175 1.225 -0.3 1.10 VDAC 1.08 VDAC 0.90 VDAC 0.88 VDAC 0.95 -0.6 1.53 0.925 -0.85 -1.0 1.70
UVLO Threshold UVLO Hysteresis Battery UVLO Threshold Battery UVLO Hysteresis Shutdown Input Threshold Core Power Good Threshold
VUVLO 1.275 VUVLO 1.175 0.925 VDAC 2.000
PWRGD Output Voltage
VCORE VDAC VCORE VDAC VUVLO VSSC VSSC VUVLO
1.275 +0.3 1.12 VDAC 1.10 VDAC 0.92 VDAC 0.90 VDAC -1.4 1.87 2.000 0.85
CORE CONVERTER SOFT-START TIMER Timing Charge Current ISSC(UP) Discharge Current ISSC(DN) Enable Threshold VSSCEN4 Termination Threshold VSSCTH Input Threshold Input Pull-Up Current Nominal Output Voltage Output Voltage Accuracy Output Voltage Settling Time CORE COMPARATOR Input Offset Voltage Input Bias Current Hysteresis Current VVID0.4 IVID0.4 VDAC VDAC/VDAC tDACS5 VCOREOS IREG IRAMP
Code Table
VREG VREG VRAMP VCORE VRAMP VCS- 1.30 VCS+ 1.28 VREG 1.28 RVHYS Open RVHYS RVHYS VREG 1.32 RVHYS Open RVHYS RVHYS 25°C 100°C
1.53
-113 1.87
Hysteresis Setting Reference Voltage VVHYS Output Voltage VOUTH VOUTL tCOREPD7 Propagation Delay Time6 Rise Fall Time6 tCORER8, tCOREF8
1.70
REV.
ADP3421
Parameter CURRENT LIMIT COMPARATOR Input Offset Voltage Input Bias Current Hysteresis Current Symbol VCLOS ICL+ ICL- Conditions VCS- VCS+ VCORE VRAMP VREG 1.28 VCS- VCS+ 1.28 RIHYS Open RIHYS RIHYS VCS+ 1.32 RIHYS Open RIHYS RIHYS 25°C 100°C VSSC VSSC VUVLO -0.6 1.53 VCLKFB VCLKDRV 2.55 VCLKDRV 2.45 ICLKDRV VIOFB VIODRV 1.53 VIODRV 1.47 ICLKDRV ILTI ILTI VLTI 0.175 Unit
-265
-300
-335 -225 1.87 -1.4 1.87
mA/V mA/V
Hysteresis Setting Reference Voltage VVHYS Propagation Delay Time6 tCLPD7 LINEAR REGULATOR SOFT-START TIMER Charge Current ISSC(UP) Discharge Current ISSC(DN) Enable Threshold VSSCEN4 Termination Threshold VSSCTH CONTROLLER Feedback Bias Current Output Drive Current Transconductance CONTROLLER Feedback Bias Current Output Drive Current Transconductance LEVEL TRANSLATOR Input Clamping Threshold Output Voltage Propagation Delay Time6 ICLKFB ICLKDRV GCLK IIOFB IIODRV VLTIH VLTOH VLTOL tLTPD
-175 1.53
-200 1.70 -1.0 1.70 12.5
0.95 VCCLT
VCCLT
NOTES VCORE ramps monotonically. VCORE ramps down monotonically. During latency time code change, Power Good output signal should considered valid. Internal bias soft start enabled unless soft-start voltage first drops below enable threshold. Measured from code transient amplitude point where settles within steady state value. Guaranteed characterization. amplitude impulse with overdrive. Measure from input threshold intercept point output voltage swing. Measured between points output voltage swing. output tied CCLT rail through pull-up resistor. Specifications subject change without notice.
REV.
ADP3421
ABSOLUTE MAXIMUM RATINGS* CONFIGURATION
VHYS CLSET VID4 VID3
Input Supply Voltage (VCC) -0.3 UVLO Input Voltage -0.3 Other Inputs/Outputs Operating Ambient Temperature Range 100°C Junction Temperature Range 150°C 98°C/W Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, sec.) 300°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RAMP
ADP3421
VIEW VID2 (Not Scale) DACOUT VID1 VID0 CLKDRV CLKFB IODRV
CORE UVLO PWRGD
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
IOFB
ADP3421JRU 100°C
Thin Shrink Small RU-28 Outline (TSSOP)
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADP3421 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality. FUNCTION DESCRIPTIONS
WARNING!
SENSITIVE DEVICE
Mnemonic VHYS CLSET
Function Core Comparator Hysteresis Setting. voltage this held reference level. resistor ground programs ratio current that alternately switched into RAMP pin. Current Limit Setting. voltage this held reference level. resistor ground programs current that gained flowing pin, assuming current limit comparator triggered. Level Translator Output. This must tied through pull-up resistor voltage level desired output high level. That voltage cannot less than Level Translator Input. This should driven from open drain/collector signal. pull-up current provided pull-up resistor pin. However, pull-up current will terminated when reaches Level Translator Bypass. operation level translator with high-speed signals, this should bypassed ground with large value capacitor. Input. Most significant bit. Input Input Input Input. Least significant bit. Linear Regulator Driver Output. This sinks current from base transistor needed keep CLKFB node regulated Linear Regulator Output Feedback. This connected collector transistor whose base driven CLKDRV pin. Linear Regulator Driver Output. This sinks current from base transistor needed keep IOFB node regulated Linear Regulator Output Feedback. This connected collector transistor whose base driven IODRV pin.
VID4 VID3 VID2 VID1 VID0 CLKDRV CLKFB IODRV IOFB
REV.
ADP3421
Mnemonic PWRGD Function Shutdown Input. When this pulled low, shuts down regulation functions will disabled. Power Good Output. This signal will high only when high allow operation, UVLO pins above their respective start-up thresholds, pins above voltage where soft start completed, voltage CORE within specified limits programmed voltage. choosing soft-start capacitor core larger than that linear regulators, start-up core linear outputs should regulation before PWRGD asserted. Undervoltage Lockout Input. This monitors input voltage through resistor divider. When voltage below specified threshold, enters into UVLO mode regardless status When UVLO mode, current source switched this pin, which sinks current from external resistor divider. generated UVLO hysteresis equal current sink value times upper divider resistor. Linear Regulator Soft Start. During power-up, external soft-start capacitor charged current source control ramp-up rates linear regulators. Core Voltage Soft Start. During power-up, external soft-start capacitor charged current source control ramp-up rate core voltage. Core Converter Voltage Monitor. This used monitor core voltage power good verification. VID-Programmed Digital-to-Analog Converter Output. This voltage reference voltage output voltage regulation. Ground Logic-Level Drive Signal Output Core Controller. This provides drive command signal ADP3410 driver. This capable directly driving power MOSFET. Power Supply Current Ramp Input. This provides negative feedback core output voltage. switched sink/ source current from this pin, which VHYS pin, works against terminating resistance this hysteresis hysteretic control. Regulation Voltage Summing Input. recommended configuration, DACOUT voltage core voltage summed this establish regulation with output voltage positioning. Current Limit Positive Sense. This senses positive node current sense resistor. Current Limit Negative Sense. This connects through resistor negative node current sense resistor. current flows pin, programmed CLSET pin. When this more negative than pin, current limit comparator triggered current flowing reduced two-thirds previous value, producing current limit hysteresis.
UVLO
CORE DACOUT RAMP
REV.
ADP3421-Typical Performance Characteristics
100m HIGH NORMAL OPERATING MODE
1000
SUPPLY CURRENT
SOFT-START TIME
CORE FULL-SCALE
UVLO MODE
POWER GOOD
SHUTDOWN MODE
CORE ZERO-SCALE LDOS
TEMPERATURE
-0.15 -0.1 -0.05 0.05 0.15 RELATIVE CORE VOLTAGE VCORE VCORE
TIMING CAPACITANCE
Supply Current Temperature
Power Good Relative Core Voltage Variation
Soft-Start Time Timing Capacitance
2.010 +0.85%
HIGH, RHYS
HYSTERESIS CURRENT
LOW, RCLSET 170k HIGH, RCLSET 170k
OUTPUT
2.000 1.990 0.9375 -0.85%
FULL-SCALE
CURRENT LIMIT THRESHOLD CURRENT
-100
HIGH, RHYS 170k
+0.85%
LOW, RHYS 170k
-200
LOW, RCLSET
0.925 -0.85% 0.9125
ZERO-SCALE
LOW, RHYS -100 AMBIENT TEMPERATURE
-300
HIGH, RCLSET AMBIENT TEMPERATURE
AMBIENT TEMPERATURE
Output Voltage Temperature
Core Hysteresis Current Temperature
Current Limit Threshold Current Temperature
REGULATOR OUTPUT VOLTAGE
VIOFB 1.47V
1.52
REGULATOR OUTPUT VOLTAGE
OUTPUT DRIVE CURRENT
1.55
2.60
2.55 2.50
1.50
VCLKFB 2.45V AMBIENT TEMPERATURE
1.48
2.45
1.45
0.01 LOAD CURRENT
2.40
0.01 LOAD CURRENT
Drive Current Temperature
Load Regulation
Load Regulation
REV.
ADP3421
THEORY OPERATION Supply Voltages
ADP3421 optimized with, specified supply, operate expense increased quiescent current minor tolerance degradation. ADP3410 MOSFET driver accommodate driving upper power MOSFET above rail.
Undervoltage Lockout
applied input. code corresponds that recommended guidelines mobile Pentium® published Intel (see Table
Table Code
VID4
VID3
VID2
VID1
VID0
VOUT 2.000 1.950 1.900 1.850 1.800 1.750 1.700 1.650 1.600 1.550 1.500 1.450 1.400 1.350 1.300 Off* 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.00 0.975 0.950 0.925 Off*
undervoltage lockout (UVLO) circuit comprises detection comparators. UVLO provides system UVLO that monitors battery voltage allows converter operation disabled battery falls below preset threshold. resistor divider UVLO sets UVLO-off level system comparing specified reference. When goes enough activate UVLO, this triggers specified current sink into switched This raises UVLO-on threshold above UVLO-off threshold current sink values times upper resistor divider. resistor divider ratio UVLO used UVLO threshold hysteresis. Hysteresis system UVLO recommended prevent oscillation nonzero battery impedance. UVLO triggered during condition where battery loaded converter operation, converter will turn battery voltage will then rise slightly higher level. good design will ensure that hysteresis sufficient prevent converter from turning again. UVLO provides internally specified UVLO threshold ADP3421 ensure that only operates when applied sufficient ensure that operate properly. Activation either UVLO circuit disables reference bias circuits except that which needed UVLO detection.
Power Good
enabled UVLO mode finished soft-start period, core voltage within programmed value, then high-level signal appears PWRGD pin.
Power Good During Change
shutdown
When change occurs, output responds faster than output voltage, which slew rate limited output filter. this case, PWRGD momentarily low. avoid system interruption, power management system should respond this glitch. PWRGD signal corresponds V_GATE specified Intel's Geyserville Voltage Regulator specification. glitch masked from system using appropriate system programming settings using functionally equivalent gate, which provides blanking signal specified latency period where core voltage allowed settle value. Because minimal output capacitor requirement, response time core voltage well within specified latency period and, when power converter properly compensated, does exhibit overshoot.
VID-Programmed Reference
Core Comparator
core comparator ultrafast hysteretic comparator with typical propagation delay overdrive. This comparator used with switched hysteresis current controlling main feedback loop, described Main Feedback Loop Operation section. This comparator relation CORE pin, which used only core voltage monitoring PWRGD function.
Current Limit Comparator
This 5-bit digital-to-analog converter (DAC) serves programmable reference source dc-dc converter. Programming accomplished CMOS logic-level code
Pentium registered trademark Intel Corp.
current limit comparator monitors voltage across current-sense resistor overrides core comparator forces when current exceeds peak current limit threshold. current control hysteretic, with valley current threshold equal two-thirds peak current limit threshold. When sensed current signal falls two-thirds peak threshold, allowed high again, control main loop reverts back core comparator.
REV.
ADP3421
resistor (RCLS) connected between CLSET ground sets current that internally multiplied factor three flows pin. resistor connected series with negative current sense point (i.e., output voltage) sets voltage that must developed across trip current limit comparator. Once tripped, current scaled down two-thirds, inductor current must ramp down accordingly reset comparator.
Core Converter Soft-Start Timer
time linear regulator output voltages. maximum flexibility controlling start-up sequence, soft-start function linear regulators separated from that core converter.
Level Translator
soft-start function limits ramp-up time core voltage order reduce initial in-rush current core input voltage (battery) rail. soft-start circuit consists internal current source, external soft-start timing capacitor, internal switch across capacitor, comparator monitoring capacitor voltage. soft-start capacitor held discharged when either signal device UVLO mode. soon high, rise above their respective UVLO thresholds, short across external timing capacitor removed, internal soft-start current source begins charge timing capacitor. During charge soft-start capacitor, Power Good signal low. When timing capacitor voltage reaches internally soft-start termination threshold, core monitor window comparator output enabled, allowing Power Good status determined. core voltage already settled within specified limits Power Good signal goes high, otherwise stays low. soft-start capacitor remains charged until either goes low, drop below their respective UVLO thresholds. When this occurs, internal switch quickly discharges soft-start timing capacitor prepare start-up sequence.
Soft-Start Restart Lock
level translator converts digital input signal userprogrammable voltage level. This used translate IO-level signal (i.e., into CLK-level VCC-level even V-level signal. example, FERR# signal converted level PII-X4 chipset. output signal phase with input, necessary have pull-up input signal. ADP3421 provides pull-up input signal only practical restriction input signal that must prevent pull-up external pull-up resistor sets output signal level. Throughput time signal using pull-up resistor (typ).
APPLICATION INFORMATION Overview-Combined ADP3421 ADP3410 Power Controller Systems
ADP3421 power controller that provide regulation solution three power rails Intel Pentium processor. Together with ADP3410 driver these form integral part system, featuring high-speed (<10 level translator, interface with PII-X4 other power management signals, power sequenced switched rail. high-slew-rate microprocessors, this minimizes total solution cost allowing quantity output capacitors minimized limit what buck converter topology capacitor technology allow.
Recommended Configuration
event that UVLO event long enough allow soft-start capacitors discharge (e.g., momentary power glitch), UVLO event captured latch. forced discharge soft-start capacitors will continue until lower threshold reached, which time converter will restart with fully controlled soft start.
Voltage Regulator
pins control external PNP, example, transistor linear regulator output. IODRV directly drives base with support output current high PNP's current gain power dissipation capability will allow. example, with high gain transistor such Zetex ZFT788B (SOT-223), linear regulator capable delivering peak currents greater than output connected IOFB provide feedback.
Voltage Regulator
ADP3421 controls regulation core voltage without amplifiers unique ripple regulator control topology. proprietary optimized compensation configuration offered Analog Devices, Inc., inductor ripple current kept fixed programmable value while output voltage regulated with fully programmable voltage positioning parameters, which tuned optimize design particular regulation specifications. fixing ripple current, frequency variations associated with changes output capacitance standard ripple regulators will appear. Accurate current sensing needed accomplish accurate output voltage positioning, which, turn, required allow minimum number output capacitors used contain transients. current-sense resistor used between inductor output capacitors. allow control operate without amplifiers, negative feedback signal taken from inductor, upstream, side current-sense resistor, positive feedback signal taken from downstream side. Active voltage positioning, whose advantages described later, parameters that separately controlled. negative feedback signal uses resistor divider ground into RAMP create precise offset voltage needed voltage positioning. positive feedback signal DAC's VID-controlled reference summed into through resistors desired voltage positioning gain. proprietary optimal compensation final parameter that must tuned ensure that voltage positioning bandwidth limited. This accomplished using appropriately-sized capacitor parallel with resistor that sums positive feedback signal. REV.
pins control external transistor linear regulator output. CLKDRV pin, example, directly drives base with support output current high PNP's current gain power dissipation capability will allow. example, with high gain transistor such Zetex ZFT788B (SOT-223), linear regulator capable delivering peak currents greater than output connected CLKFB provide feedback.
Linear Regulator Soft-Start Timer
soft-start timer circuit linear regulators similar that core converter, used control ramp-up
ADP3421
optimal compensation also gives ripple current control that adds stability switching frequency.
Standard Hysteretic Control Configuration
voltage positioning-a tolerance analysis show weakness this design technique. Although additional power dissipated current-sense resistor, total power consumption reduced because squared reduction current consumption CPU. example, draws current-sensing resistor supply voltage reduced core dissipation reduced from 0.932 20.76 power dissipated resistor only: [20.76 W/(1.6 0.93)]2 0.58 total power savings from battery 2.65 11.1%.
Optimally Compensated Voltage Positioning
ADP3421 also used conventional hysteretic ripple regulator where output ripple voltage directly programmed. achieve this conventional operation, DAC's output connected directly output voltage connects through resistor RAMP pin. This resistor sets output ripple voltage, which will symmetrically centered around voltage. optimal voltage available, offset could summed into RAMP with another resistor, done with previous configuration.
Intel Mobile Voltage Positioning Implementation
recommended configuration, ADP3421 uses voltage Intel Mobile Voltage positioning technology inherent part architecture. matter fast response switches, even instantaneous, inductor limits response speed output converter. This places primary burden transient response containment output capacitors. size cost output capacitors minimized keeping output voltage higher light load anticipation load increase, lowering output voltage heavier loads anticipation load decrease. Voltage positioning with ADP3421 active, which means voltage positioning controlled loop gain. This increases efficiency compared passive voltage positioning that sometimes used supplementary regulation technique with voltage-mode controllers. Instead sizing series resistor create entire voltage drop (often called "droop" resistor passive voltage positioning implementation), smaller value current-sensing resistor used loop amplify voltage drop position voltage desired without additional power loss.
Voltage Positioning Power Savings
Although voltage positioning helps control initial load transient, high-frequency load repetition rates cause voltage exceed double limits within which transients contained. complete transient containment over bandwidth core's transient activity, solution enhanced optimally compensated version voltage positioning. prevents tendency core voltage "bounce" before settling final positioned value after inductor current been ramped final value.
Main Feedback Loop Operation
addition size cost reduction output capacitors, another advantage using voltage positioning reduction core dissipation. That dissipation equal product applied core voltage current drawn CPU. current primarily capacitive switching load digital circuitry, also proportional applied voltage. result that power dissipation approximately proportional applied voltage squared. PCPU VCPU2 This characteristic, combined with wide tolerance core voltage specification, suggests that maximum power dissipation substantially reduced setting core voltage near lower specified voltage limit. example, processor operated below nominal voltage rating, power dissipation reduced 13.5%. Losses switches inductor power converter also reduced decrease maximum load current. realize full cost-reducing benefits active voltage positioning, current-sensing resistor should used convey accurate current information control loop. This needed accurately position core voltage function load current. Accurate positioning core voltage allows highest reduction output capacitors. common passive voltage positioning implemented sensing voltage drop copper trace across power MOSFET. This causes poor control REV.
conjunction with selected control topology, ADP3421 regulates drive control signal using comparator. inputs pins RAMP (+). bidirectional switched control current used RAMP input establish hysteresis with chosen termination resistance. Beginning drive high state (OUT high), control current sinking current into RAMP pin, output current buck converter increasing VRAMP will eventually exceed VREG. When this happens, control current reverses sources current RAMP provide both hysteresis overdrive comparator. goes buck converter output current decreases until VRAMP VREG, which time comparator switches, control current reverses, process repeats. hysteresis current used (depending control configuration) will determine which parameter hysteretically controlled-presumably either inductor ripple current output ripple voltage, suggested configurations, weighted combination another variable could introduced.
Core Converter Design Procedure
There primary objectives considered optimizing design power converter. first objective meet specifications; second objective lowest cost. Analog Devices, Inc., addresses both these objectives with ADP3421 recommended design procedure. optimized design yields additional benefit reducing maximum power consumption ~10% typical specifications, which created great interest those using CPU. Microprocessors have distinguishing characteristic creating extremely fast load transients from nearly zero maximum load vice versa. advent increasing power management (used interrupt processing) causes
ADP3421
these transients occur with increasing frequency. Since takes longer time (typically order several microseconds) ramp inductor current down correct average value after load transient occurred, output capacitors must supply absorb extra charge during that period time. This causes output voltage down peak contain output voltage within specified limits during load transients, with minimum quantity output capacitors, output voltage must positioned function load, must done accurately. Therefore, current-sensing with discrete resistor (rather than trace resistance) strongly recommended, because allows number capacitors reduced toward theoretical minimum- which nearly half many required standard fixed-regulation technique. This minimizing cost (and size) power converter. voltage should positioned (i.e., regulated) high load maximum load. This means that power supply will appear have initial offset reduced load regulation, because output voltage will regulate higher than nominal load below nominal maximum load. This regulation technique positions voltage anticipation load transient. load, voltage high, when load transient strikes, downward more easily contained within limits. Similarly maximum load, voltage low, when load transient strikes, upward peak more easily contained. Multiple capacitors will always needed output across power pins handle high-frequency component transient with minimized series inductance through bulk capacitors power converter's output filter. Although there numerous trade-offs between size cost various combinations capacitor types meeting given specification, accurate voltage positioning provided ADP3421 will allow overall combination capacitors minimized. requirement optimizing dynamic performance power converter with accurate voltage positioning apply "optimal compensation"-that compensation that creates loop response that causes output voltage settle immediately after load transient, resulting "flat" transient response. ADP3421's unique architecture designed accommodate this proprietary optimal compensation technique core dc-dc converters Mobile CPUs. implemented creating proper frequency response characteristic summing junction output voltage voltage, which occurs pin. complete design procedure supplied separate application note from Analog Devices, Inc., entitled: DC-DC Power Converter Design using ADP3421 Controller.
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
ADP3421 high-speed controller capable providing response time well under avoid having ADP3421 respond noise, first step achieving good noise immunity follow layout considerations. some layouts necessary supplement ADP3421 control design with additional components designed minimize noise problems. this purpose, some additional hysteresis added around core current limit comparators. This takes form adding small capacitor from (for main loop) (for current limit loop), providing some resistance capacitive hysteresis feedback work against. current limit loop, this register already basic circuit. main loop, this resistor must added between standard feedback components. This provides quick dynamic hysteresis with small time constant that chosen only long enough ensure that switching noise ringing through circuit decayed time dynamic hysteresis substantially lost. following guidelines recommended optimal performance ADP3421 ADP3410 power converter. circuitry considered four parts: power switching circuitry, output filter, control circuitry, LDOs.
Placement Overview
ideal component placement, output filter capacitors will divide power switching circuitry from control section. approximate guideline, considered singlesided PCB, best layout would have components aligned following order: ADP3410, MOSFETs input capacitor, output inductor, current-sense resistor, output capacitors, control components, ADP3421. Note that ADP3421 ADP3410 completely separated ideal layout, which only possible with two-chip solution. This will minimize jitter control caused having driver MOSFETs close control give more freedom layout power switching circuitry. Whenever power dissipating component (e.g., power MOSFET) soldered PCB, liberal vias, both directly mounting immediately surrounding recommended. important reasons this are: improved current rating through vias current path) improved thermal performance-especially vias extend opposite side where plane more readily transfer heat air.
-10-
REV.
ADP3421
Power Switching Circuitry ADP3410, MOSFETs, Input Capacitors Control Circuitry ADP3421, Control Components
Locate ADP3410 near MOSFETs parasitic inductance gate drive traces trace small, that ground pins ADP3410 closely connected lower MOSFET's source. Locate least substantial (i.e., input bypass capacitor close MOSFETs that physical area loop enclosed electrical path through bypass capacitor around through bottom MOSFETs (drain-source) small. This switching power path loop. Make provisions thermal management MOSFETs. Heavy copper wide traces ground power planes will help pull heat. Heat sinking metal soldered power plane near MOSFETs will help. Even just small airflow help tremendously. Paralleled MOSFETs will help spread heat, even resistance higher. external "antiparallel" Schottky diode (across bottom MOSFET) help efficiency small amount MOSFET with built-in antiparallel Schottky more effective. external Schottky, should placed next bottom MOSFET effective all. Also, higher current rating (bigger device with lower voltage drop) more effective. Both ground pins ADP3410 should connected into same ground plane with power switching circuitry, bypass capacitor should close connected into same ground plane.
Output Filter Output Inductor Capacitors, Current-Sense Resistor
placement overview cannot followed, ground ADP3421 should Kelvin-connected into ground plane near output capacitors avoid introducing ground noise from power switching stage into control circuitry. other control components should grounded that same signal ground. critical signal lines (i.e., signals from current-sense resistor leading back ADP3421) must cross through power circuitry, best signal ground plane interposed between those signal lines traces power circuitry. This serves shield minimize noise injection into signals expense making signal ground noisier. Absolutely avoid crossing signal lines over switching power path loop, previously described. Accurate voltage positioning depends accurate current sensing, control signals that differentially monitor voltage across current-sense resistor should Kelvin-connected. filter used current-sense signal should located near control components.
LDOs Transistors
maximum steady-state power dissipation expected design should calculated that acceptable package type each output selected properly mounted able dissipate power with acceptable temperature rise. Each transistor should located close load that sources. supply voltage emitters should impedance avoid loop instability. good design practice have least capacitor near each emitters help ensure impedance sufficiently low.
Locate current-sense resistor very near output capacitors. trace resistances from current-sense resistor output capacitors, from output capacitors load, should minimized, known (calculated measured), compensated part design significant. (Remote sensing sufficient relieving this requirement.) square section ounce copper trace resistance ~500 Using squares copper make noticeable impact design. Whenever high currents must routed between layers, vias should used liberally create several parallel current paths that resistance inductance introduced these current paths minimized current rating exceeded. ground connection output capacitors should close ground connection lower MOSFET should ground plane. Current pulsate this path power source ground closer output capacitors than power switching circuitry, close connection will minimize voltage drop.
REV.
-11-
ADP3421
TYPICAL APPLICATION-GEYSERVILLE-ENABLED MOBILE CONVERTER
3.3V
51.1k
ADP3421
VHYS RAMP DACOUT CORE UVLO PWRGD
220k
3.3k
100k
22nF
10BQ040
160k
CLSET VID4 VID3
ADP3410
OVPSET
R21,10k
DRVH SRMON PGND DRVL
100nF
100nF
100nF
100pF
IRF7811
15nF
DRVLSD
10BQ040
CORE
10pF
IRF7811
IRF7811
FROM
VID2 VID1 VID0
1.5nF
7.5k
VCCGD
C4-C6, C11, C12, C26,
2N3906 MJD210
CLKDRV CLKFB IODRV IOFB
470k
CORE SENSE GATE
VRON
Figure Mobile Schematic
OUTLINE DIMENSIONS
Dimensions shown (inches).
28-Lead Thin Shrink Small Outline Package (TSSOP) (RU-28)
9.80 (0.386) 9.60 (0.378)
4.50 (0.177) 4.30 (0.169) 6.50 (0.256) 6.25 (0.246)
0.15 (0.006) 0.05 (0.002) 1.10 (0.043)
SEATING PLANE
0.65 (0.026)
0.30 (0.012) 0.19 (0.008)
0.20 (0.008) 0.09 (0.004)
0.70 (0.028) 0.50 (0.020)
Revision History
Location 5/02-Data Sheet changed from REV. REV. Page
Changed Figures TPCs Renumbered Figure
-12-
REV.
PRINTED U.S.A.
CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
C00152-0-5/02(A)

ADP3421 DACOUT VID4 VID3 VID2 VID1 VID0 CURRENT LIMIT COMPARATOR

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