80KB Controller/Driver AUG. 2001 Version SPL61A Table C
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SPL61A
80KB Controller/Driver
AUG. 2001 Version
SPL61A
Table Contents
PAGE
GENERAL DESCRIPTION. BLOCK DIAGRAM FEATURES. SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. 5.1. AREA 5.2. MEMORY I/OS 5.3. OPERATING STATES 5.4. SPEECH MELODY 5.5. CONTROLLER/DRIVER 5.6. VOLTAGE DOUBLER/REGULATOR 5.7. OUTPUT. 5.8. ASYNCHRONOUS SERIAL INTERFACE 5.9. VOLTAGE DETECTION 5.10. WATCH TIMER (WDT) 5.11. MASK OPTIONS ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS. APPLICATION CIRCUITS. 7.1. POINTS DRIVER, SEGMENTS COMMONS, 32768 MASK OPTION X'TAL 7.2. POINTS DRIVER, SEGMENTS COMMONS, 32768 MASK OPTION R-OSCILLATOR 7.3. SERIAL COMMUNICATIONS BETWEEN SPL61AS PACKAGE/PAD LOCATIONS 8.1. ASSIGNMENT 8.2. ORDERING INFORMATION 8.3. LOCATIONS DISCLAIMER. REVISION HISTORY
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SPL61A
80KB CONTROLLER/DRIVER
GENERAL DESCRIPTION
SPL61A, 8-bit CMOS single chip microprocessor, contains RAM, ROM, I/Os, interrupt/wakeup controller, 8-bit audio output, UART automatic display controller/driver LCD. With dual channel driver, attractive sound effects generated easily. between chips. built-in UART speeds data transmission Furthermore, software controllable standby great
FEATURES
Built-in 8-bit processor bytes SRAM bytes Max. operating speed: 3.0MHz 2.6V clock software programmable, 1/2, 1/4, 1/16 R-oscillator's clock frequency wake-up Provide interrupt sources Asynchronous serial interface Supports rates 115.2 Kbps Programmable driver segments, commons, maximum dots bias capability 1/8, 1/12 duty bytes dedicated com/seg driving strength adjusted
switch also built-in save power consumption.
amount used store both program audio data. (The speech duration approximately seconds 7KHz sampling rate using 4-bit ADPCM). SPL61A designed with state-of-the-art technology fulfill requirements applications especially hand-held products.
BLOCK DIAGRAM
ROSC X32I X32O
compromise display quality current consumption Built-in voltage doubler voltage regulator generate
8-BIT PROCESSOR
TIME BASE INTERRUPT LOGIC
Watchdog Timer
IOCD3 0(I/O)
VLCD driver 16-level VLCD adjustable (3.3V 4.8V) Power saving SLEEP mode voltage detector 2.6V 2.4V detection Peripherals pins (IOEF3 IOCD3 pins shared with segments (mask option) Extra pins (IOEF5 when UART used (mask option) Extra pins (IOEF7 when 1/12 duty (mask option) Built-in 32.768KHz oscillator circuit real time clock function Built-in R-oscillator (only resistor needed) Internal time base generator 16-bit reloadable timer/counters 8-bit resolution, 2-channel outputs (can drive speaker buzzer directly) Watchdog Timer reliable operation Wide operating voltage: 2.4V 3.6V 1.0MHz 3.6V 5.5V 1.0MHz Low-power consumption: typical 3.0V, FCPU 1.0MHz <1µA typical standby current 3.0V
IOEF3 0(I/O)
BYTES
BYTES SRAM
BITS AUTO RELOAD TIMERS
AUDP
AUDN
VOLTAGE DETECTOR
BYTE
TxD/IOEF4
RxD/IOEF5
REGULATOR
DOUBLER
SEGMENTS COMMONS DRIVER
SEG39
COM15
Note1: IOAB3 enabled mask option from Segment Each I/O(segment) mask optioned individually. Note2: optioned IOEF5 when UART used.
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SPL61A
SIGNAL DESCRIPTIONS
Mnemonic SEG39 SEG36 SEG35 COM15 COM13 IOEF3 IOCD3 ROSC RESET AUDP AUDN X32I X32O TEST VLCD HVLCD CUP1 CUP2 AVDD AVSS Power supply voltage input Ground reference Analog power Analog ground reference 32.768KHz crystal input connect through resistor (option) 32.768KHz crystal output Test input voltage. enabled. voltage generation. Charge pump capacitor interconnection pins Connect through capacitor voltage doubler enabled. Connect through capacitor voltage regulator driver common output. IOEF7 COM15 optioned Port bi-directional port. Type driver segment output. IOAB3 Description SEG39 optioned
Port bi-directional port.
Port bi-directional port, software programmed wake I/O. Port bi-directional port. UART input. UART output. optioned IOEF5 optioned IOEF4
ROSC input, connect through resistor System reset input, active. audio output
voltage generation.
Legend: Input, Output, Power
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FUNCTIONAL DESCRIPTIONS
5.1. Area
SPL61A large based micro-controller with dots driver. large defined program ROM, fonts audio data continuously without limitation. operating state, modules (CPU, 32768 oscillator, There timer/counter, driver.) activated. halt/standby
state entered writing SLEEP register ($09).
access area, users should first program BANK SELECT Register ($07) then access bank#1 bank#2 addressing higher bank address, data. $8000 $FFFF, fetch
four wake-up sources SPL61A: port IOEF wake-up, TIMR0 wake-up, 4Hz/8Hz/16Hz/32Hz wake-up 2Hz/1Hz wake-up. continues operating state. When standby, modules will shut down, I/Os remain their previous states. current consumption halt state, minimized standby. writing SLEEP register keeps wake-up event occurs, execution next instruction
5.2. Memory I/Os
*I/O PORT: PORT IOAB $0002 PORT IOCD $0003 PORT IOEF $0004 AB_CTRL $0001 CD_CTRL $0000 EF_CTRL $0006 *NMI SOURCE: INT1 from TIMER *INT SOURCE: INT0 from TIMER INT1 from TIMER 4Hz/8Hz/16Hz/32Hz from IOCD0 UART $13FFF $14000 $17FFF $07FFF $08000 $0FFFF $10000 $0003F $00040 $000FF $00100 $0022F $00300 $0037F $00400 $007FF $00800 MEMORY $00000 registers I/Os WORKING SRAM(192 bytes) SRAM STACK Data Storage (304bytes) Buffer bytes) SUNPLUS TEST PROGRAM
32768 oscillator running, system halt state. overflow) generate wake-up.
clock halted while waits event (key press, timer 32768 related modules (timer/counter, driver.) remain active halt state. Following figure state diagram SPL61A.
Write SLEEP register, 32768 oscillator OPERATING STANDBY Wake-up user reset
cill rite
USER's PROGRAM DATA AREA BANK
BANK
UNUSED
HALT
BANK
State Diagram SPL61A Note: $7FFA $7FFF bank#0, $FFFA $FFFF bank#1 reserved reset vectors. $7FF2 $7FF7 bank#0, $FFF2 $FFF7 bank#1 reserved testing.
5.4. Speech Melody
Since SPL61A provides large wide range operating speed, most appropriate speech melody synthesis. speech synthesis, SPL61A provides Users several timer interrupts precise sampling frequency.
5.3. Operating States
SPL61A supports three operating states: standby, halt, operating. Following table shows differences between three operating states.
record synthesize sound digitize into ROM. sound then played back sequence assigned users' programs. Several algorithms recommended high fidelity good compression sound: such
Operating 32768 oscillator driver
Halt ON/OFF
Standby
ADPCM. melody synthesis, SPL61A provides dual tone mode. Once dual tone mode, users only need program tone frequency each channel writing timer/counter TM1, envelope each channel. hardware will toggle tone wave automatically without users' care.
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SPL61A
5.5. Controller/Driver
SPL61A contains total dots controller driver. Programmers configuration (bias, duty, voltage doubler) writing control register ($20). filling buffer with appropriate data. Once configuration initialized, desired pattern displayed driver also operate during sleep keeping 32768 oscillator running. driver SPL61A designed most specifications. either programmed bias Baud Rate(bps) 1200 2400 4800 9600 19200 38400 51200 57600 102400 115200 Min. Frosc(Hz) 24000 48000 96000 192000 384000 768000 1024000 1152000 2048000 2304000 duty also programmable 1/8, 1/12, 1/16 duty. UART supports clock auto calibration. 115.2kbps available. this clocking
scheme selected, standard baud rates from 1.2kbps baud rate selected writing supported standard baud rate control registers $2F. required shown following table.
baud rates their minimum R-oscillator clock frequency
5.6. Voltage Doubler/Regulator
SPL61A also contains built-in voltage doubler voltage regulator. (HVLCD) voltage regulator provides reference voltage voltage doubler generate VLCD Users desired VLCD changing
charge-pumping).
output reference voltage (writing $23) voltage regulator. enabling voltage doubler regulator, users stable VLCD that will affected VDD. following table. three possible configurations voltage doubler regulator shown
auto calibration clocking scheme selected, users Doubler VLCD (not regulated) 2*VDD (not regulated) 3.3V 4.8V adjustable desired baud rates writing appropriate values prescaler registers, $2D. obtained this way. Non-standard baud rates When using non-calibration mode, should
Regulator
aware that frequency R-oscillator alter manufacturing process variations, supply voltage, operating temperature tolerance external components used.
5.7. Output
Internally, SPL61A pair outputs with sound channels. individually. circuit. Each channel play speech tone SPL61A uses Pulse Width Modulation that could
5.9. Voltage Detection
SPL61A provides 2.6V/2.4V voltage detector detect voltage event. Users turn 2.6V detection read bit1 port periodically monitor lower than 2.6V.
directly drive speaker buzzer without buffer amplification
addition, 2.4V detection turned drops below 2.4V, after SLEEP command issued, system will shut down activities(LCD bias, display, 32768 oscillator) enters standby reduce current consumption. This voltage power Users
5.8. Asynchronous Serial Interface
SPL61A supports 1-channel UART serial communications. supports rates 115.2kbps. UART operation controlled
down awakened PEF0 change RESET. change function.
this feature implement battery check/battery
UART command registers $2A. Configurations such Tx/Rx interrupt, parity check, parity even/odd clock source command registers. received transmitted. interrupts generated
2.4V SLEEP OPERATING STANDBY
interrupt asserts when byte reading status register $2A,
users tell whether interrupt generated Framing, overrun parity errors detected each byte received. error status read from status register $2A.
Port wake-up user reset
State Diagram Voltage Power Down
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5.10. Watch Timer (WDT)
chip watchdog timer available SPL61A. designed recovering from system abnormal operation. system after second.
5.11.3. TxD/RxD select
UART transmit output, UART receive input port EF4, port
system hanged, will generate system reset restart enabled, should Note that only works
5.11.4. Port Bit7 with 600K pull-low
Each optioned Enable/Disable individually.
cleared every seconds avoid accidental reset. cleared writing $0F. when 32768Hz clock available.
5.11.5. driver 5.11. Mask Options 5.11.1. 32768 oscillator
X'TAL R-oscillator COM15 optioned IOEF7 when mode duty 1/12 duty. SEG39 optioned IOAB3 individually.
5.11.2. Watchdog timer
Enable Disable
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SPL61A
ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions AC/DC Electrical Characteristics.
Symbol TSTO
Ratings 7.0V -0.5V 0.5V +150
normal operational
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device.
6.2. Characteristics
Characteristics Symbol Limit Min. Typ. Max. Unit Test Condition 2-battery 3-batter FCPU 1.0MHz 3.0V, load 3.0V, 32768Hz 3.0V, 2.5V 3.0V, 2.0V 3.0V, 0.5V 3.0V, 1.0V 2.6V 5.0V VLCD Variation VLCD_VAR ±0.2 VLCD 4.5V bias strength $04, panel applied Input High Level Input Level Output High Current (I/O) Output Sink Current (I/O) Resistor Clock -800 3.0V 3.0V 3.0V 2.4V 3.0V 0.8V FOSC2 2.0MHz 3.0V FCPU FOSC2 2.6V
Operating Voltage Operating Current Standby Current Audio Output Current
ISTBY
Audio Output Current
ROSC FCPU
1000 220K
Note1: VLCD variation subject change variation process, temperature, supply voltage loadings. Note2: When voltage regulator voltage doubler enabled, should lower than VLCD prevent forward biasing junction I/O's output PMOS.
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APPLICATION CIRCUITS
7.1. Points Driver, Segments Commons, 32768 Mask Option X'TAL
220µF
HVLCD VLCD CUP1 CUP2 IOEF0 IOEF1 IOEF2 IOEF3
0.1µ
BUZZER SPEAKER
Note1: IOEF4, IOEF5 shared with TxD, RxD(UART), UART used, these pins used ports Note2: These capacitors must connected voltage doubler voltage regulator used. Note3: Wire route path from capacitors chip should close possible.
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TEST AUDP AVDD AUDN AVSS SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
Note2
0.1µ
SPL61A
Note1
MODULE
TxD/IOEF4 RxD/IOEF5
RESET
IOCD3 IOCD2 IOCD1 IOCD0 RESET ROSC X32I X32O
0.1µ
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0
32768Hz
200pF
RSYS
20pF
20pF
0.1µ
AUG. 2001 Version:
SPL61A
7.2. Points Driver, Segments Commons, 32768 Mask Option R-Oscillator
220µF
0.1µ
BUZZER SPEAKER
Note1: IOEF4, IOEF5 shared with TxD, RxD(UART), UART used, these pins used ports Note2: These capacitors must connected voltage doubler voltage regulator used. Note3: Wire route path from capacitors chip should close possible.
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TEST AUDP AVDD AUDN AVSS SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 HVLCD VLCD CUP1 CUP2 IOEF0 IOEF1 IOEF2 IOEF3 Note1 TxD/IOEF4 RxD/IOEF5 IOCD3 IOCD2 IOCD1 IOCD0 RESET X32I X32O ROSC Note2
0.1µ
SPL61A
RESET 0.1µ
200PF
R32768
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 MODULE
RSYS
200PF
AUG. 2001 Version:
0.1µ
SPL61A
7.3. Serial Communications between SPL61As
200P 20pF 20pF
200P 20pF 20pF
X32I
X32O
ROSC
X32I
ROSC
X32O
SPL61A
SPL61A
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SPL61A
PACKAGE/PAD LOCATIONS
8.1. Assignment
Chip Size: 3190µm 2620µm This substrate should connected
Note1: Chip size included scribe line. Note2: 0.1µF capacitor between should placed close possible.
8.2. Ordering Information
Product Number SPL61A-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
Package Type Chip form
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SPL61A
8.3. Locations
Name SEG36 AUDP AVDD AUDN AVSS SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 -1420 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1401 -1261 -1133 -1013 -893 -773 -653 -533 -413 -293 -173 1027 1147 1276 1110 -160 -280 -400 -520 -640 -760 -880 -1000 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 Name SEG0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 CUP2 CUP1 HVLCD RESET TEST X32O X32I VLCD ROSC COM15 COM14 IOEF3 IOEF2 IOEF1 IOEF0 IOCD3 IOCD2 IOCD1 IOCD0 SEG39 SEG38 SEG37 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1276 1156 1036 -120 -247 -382 -509 -641 -768 -911 -1038 -1166 -1293 -1131 -986 -851 -724 -601 -481 -361 -241 -121 1129 1129 1129 1129 1129 1129 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110
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DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
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SPL61A
REVISION HISTORY
Date MAR. 1999 MAY. 1999 Revision Original Renew document format Modify Size: Bytes Bytes Modify SRAM Size: Bytes Bytes Modify "5.2 Memory I/Os" "5.3 Operating States" "5.6 Voltage Doubler/Regulator" "5.8 Asynchronous Serial Interface" "8.3. Serial Communications Between SPL61As" DEC. 1999 Delete "PRELIMINARY" Renew document format JUN. 2001 Correct "8.1 Points Driver, Segments Commons, 32768 Mask Option X'TAL" RESET switch 0.1µF capacitor. "Note: 0.1µF capacitor between VSS." Renew document format AUG. 2001 Correct chip size Note1 "8.1 Assignment" Renew document format Description Page
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AUG. 2001 Version:
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