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AIN1 AIN2

Complete 12-Bit 1.25 MSPS Monolithic A / D Converter AD1671

AIN1 AIN2
Complete 12-Bit 1.25 MSPS Monolithic A / D Converter AD1671
FUNCTIONAL BLOCK DIAGRAM
SHA OUT 5k UPO / BPO ENCODE VCC ACOM VEE VLOGIC DCOM S / H RANGE SELECT
3-BIT FLASH
COARSE 4-BIT FLASH 4
8-BIT LADDER MATRIX
3 REF IN REF OUT 2.5V REF
3 CORRECTION LOGIC 8
FINE 4-BIT FLASH 4
LATCHES
AD1671
REF COM OTR MSB
BIT 1 -12
PRODUCT DESCRIPTION
The AD1671 is a monolithic 12-bit, 1.25 MSPS analog-todigital converter with an on-board, high performance sampleand-hold amplifier (SHA) and voltage reference. The AD1671 guarantees no missing codes over the full operating temperature range. The combination of a merged high speed bipolar / CMOS process and a novel architecture results in a combination of speed and power consumption far superior to previously available hybrid implementations. Additionally, the greater reliability of monolithic construction offers improved system reliability and lower costs than hybrid designs. The fast settling input SHA is equally suited for both multiplexed systems that switch negative to positive full-scale voltage levels in successive channels and sampling inputs at frequencies up to and beyond the Nyquist rate. The AD1671 provides both reference output and reference input pins, allowing the on-board reference to serve as a system reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The AD1671 uses a subranging flash conversion technique, with digital error correction for possible errors introduced in the first part of the conversion cycle. An on-chip timing generator provides strobe pulses for each of the four internal flash cycles. A single ENCODE pulse is used to control the converter. The digital output data is presented in twos complement or offset binary output format. An out-of-range signal indicates an overflow condition. It can be used with the most significant bit to determine low or high overflow.
PRODUCT HIGHLIGHTS
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617 / 329-4700 Fax: 617 / 326-8703
AD1671-SPECIFICATIONS
DC SPECIFICATIONS (T
Min 12
AD1671J / A / S Typ
Max 800 Min 12
12 12 Bits Guaranteed 0.1
Volts Volts Volts Volts M k pF ns ps Volts mA mA Volts Volts µA µA pF Volts Volts
Volts Volts Volts mA mA mA mW °C °C °C
NOTES 1 Adjustable to zero with external potentiometers. 2 Includes internal voltage reference error. 3 +25°C to TMIN and +25°C to TMAX 4 Excludes internal reference drift. 5 Change in gain error as a function of the dc supply voltage. 6 Tested under static conditions. See Figure 15 for typical curve of ILOGIC vs. load capacitance at maximum tC. Specifications subject to change without notice.
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AD1671 AC SPECIFICATIONS f
Parameter SIGNAL-TO-NOISE PLUS DISTORTION RATIO (S / N + D) -0.5 dB Input -20 dB Input EFFECTIVE NUMBER OF BITS (ENOB) TOTAL HARMONIC DISTORTION (THD) PEAK SPURIOUS OR PEAK HARMONIC COMPONENT SMALL SIGNAL BANDWIDTH FULL POWER BANDWIDTH INTERMODULATION DISTORTION (IMD) 2nd Order Products 3rd Order Products
AD1671K Typ Max
AD1671J / A / S Typ Max
Units
dB dB Bits
dB dB MHz MHz
SWITCHING SPECIFICATIONS V
Parameters
Symbol tC FS tENC tENCL tDAV tF tR tDD1 tSS2 Min Typ Max 800 1.25 50 300 Units ns MSPS ns ns ns ns ns ns ns
Conversion Time Sample Rate ENCODE Pulse Width High (Figure 1a) ENCODE Pulse Width Low (Figure 1b) DAV Pulse Width ENCODE Falling Edge Delay Start New Conversion Delay Data and OTR Delay from DAV Falling Edge Data and OTR Valid before DAV Rising Edge
NOTES 1 tDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin. 2 tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin. Specifications subject to change without notice.
ENCODE
t ENCL
ENCODE
BIT 1-12 MSB, OTR DATA 0 (PREVIOUS)
DATA 1
BIT 1-12 MSB, OTR DATA 0 (PREVIOUS)
DATA 1
Figure 1a. Encode Pulse HIGH
Figure 1b. Encode Pulse LOW
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AD1671
PIN DESCRIPTION
Symbol ACOM AIN
Pin No. 27 22, 23
Type P AI
BIT 1 (MSB) BIT 12 (LSB) BPO / UPO DAV
Most Significant Bit. Data Bits 2 through 11. Least Significant Bit. Bipolar or Unipolar Configuration Pin. See section on Input Range Connections for details. Data Available Output. The rising edge of DAV indicates an end of conversion and can be used to latch current data into an external register. The falling edge of DAV can be used to latch previous dam into an external register. Digital Ground. The analog input is sampled on the rising edge of ENCODE. Inverted Most Significant Bit. Provides twos complement output data format. Out of Range is Active HIGH when the analog input is out of range. See Output Data Format, Table III. REF COM is the internal reference ground pin. REF COM should be connected as indicated in the Grounding and Decoupling Rules and Optional External Reference Connection Sections. REF IN is the external 2.5 V reference input. REF OUT is the internal 2.5 V reference output. No Connect for bipolar input ranges. Connect SHA OUT to BPO / UPO for unipolar input ranges. +5 V Analog Power. -5 V Analog Power. +5 V Digital Power.
BIT 2-BIT 11 12-3
DCOM ENCODE MSB OTR REF COM REF IN REF OUT SHA OUT VCC VEE VLOGIC
PIN CONFIGURATION
VEE BIT 12 (LSB) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 28 VCC 27 26 25 24 23 ACOM BPO / UPO SHA OUT REF IN AIN1 AIN2 REF OUT
AD1671
TOP VIEW (Not to Scale)
20 REF COM 19 DCOM 18 VLOGIC 17 ENCODE 16 DAV
BIT 4 10 BIT 3 11 BIT 2 12 BIT 1 (MSB) 13 MSB 14
15 OTR
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AD1671
ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE
Parameter
With Respect to
Min -0 5 -6.5 -0.5 -1.0 -6.5 -0.5 -0.5 -11.0 -0.5 -65
Max +6.5 +0.5 +6.5 +1.0 +6.5 VLOGIC + 0.5 VCC + 0.5 +11.0 VCC + 0.5 +150 +150 +300
VCC ACOM VEE ACOM VLOGIC DCOM ACOM DCOM VCC VLOGIC ENCODE DCOM REF IN ACOM AIN ACOM BPO / UPO ACOM Junction Temperature Storage Temperature Lead Temperature (10 sec)
Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -55°C to +125°C
Package Option2, 3 Q-28 Q-28 P-28A P-28A Q-28 P-28A Q-28
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
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AD1671
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
DYNAMIC SPECIFICATIONS
SIGNAL-TO-NOISE PLUS DISTORTION (S / N+D) RATIO
Integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale." The point used as "zero" occurs 1 / 2 LSB (1.22 mV for a 10 V span) before the first code transition (all zeros to only the LSB on). "Full-scale" is defined as a level 1 1 / 2 LSB beyond the last code transition (to all ones). The deviation is measured from the low side transition of each particular code to the true straight line.
DIFFERENTIAL LINEARITY ERROR (NO MISSING CODES)
S / N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components, including harmonics but excluding dc. The value for S / N+D is expressed in decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
TOTAL HARMONIC DISTORTION (THD)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from the ideal value. Thus every code has a finite width. Guaranteed no missing codes to 11- or 12-bit resolution indicates that all 2048 and 4096 codes, respectively, must be present over all operating ranges. No missing codes to 11 bits (in the case of a 12-bit resolution ADC) also means that no two consecutive codes are missing.
UNIPOLAR OFFSET
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.
INTERMODULATION DISTORTION (IMD)
The first transition should occur at a level 1 / 2 LSB above analog common. Unipolar offset is defined as the deviation of the actual from that point. This offset can be adjusted as discussed later. The unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustments.
BIPOLAR ZERO
In the bipolar mode the major carry transition (0111 1111 1111 to 1000 0000 0000) should occur for an analog value 1 / 2 LSB below analog common. The bipolar offset error and temperature coefficient specify the initial deviation and maximum change in the error over temperature.
GAIN ERROR
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest spectral component, excluding the input signal and dc. This value is expressed in decibels relative to the rms value of a fullscale input signal.
APERTURE DELAY
The last transition (from 1111 1111 1110 to 1111 1111 1111) should occur for an analog value 1 1 / 2 LSB below the nominal full scale (4.9963 volts for 5.000 volts full scale). The gain error is the deviation of the actual level at the last transition from the ideal level. The gain error can be adjusted to zero as shown in Figures 4 through 7.
TEMPERATURE COEFFICIENTS
Aperture delay is the difference between thc switch delay and the analog delay of the SHA. This delay represents the point in time, relative to the rising edge of ENCODE input, that the analog input is sampled.
APERTURE JITTER
The temperature coefficients for unipolar offset, bipolar zero and gain error specify the maximum change from the initial (+25°C) value to the value at TMIN or TMAX.
POWER SUPPLY REJECTION
Aperture jitter is the variation in aperture delay for successive samples.
FULL POWER BANDWIDTH
One of the effects of power supply error on the performance of the device will be a small change in gain. The specifications show the maximum full-scale change from the initial value with the supplies at the various limits.
The input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input.
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AD1671
THEORY OF OPERATION
0 TO +2.5V AIN1 5k SHA AIN2 5k -2.5V TO +2.5V AIN1 5k SHA AIN2 5k
an input range that is configured with one bit of overlap with the previous DAC. The overlap allows for errors during the flash conversion. The first residue voltage is connected to the second 3-bit flash and to the noninverting input of a high speed, differential, gain of eight amplifier. The second flash result is passed to the correction logic register and to the second segmented current output DAC. The output of the second DAC is connected to the inverting input of the differential amplifier. The differential amplifier output is connected to a two-step, backend, 8-bit flash. This 8-bit flash consists of coarse and fine flash converters. The result of the coarse 4-bit flash converter, also configured to overlap one bit of DAC 2, is connected to the correction logic register and selects one of 16 resistors from which the fine 4-bit flash will establish its span voltage. The fine 4-bit flash is connected directly to the output latches. The internal timing generator automatically places the SHA into the acquire mode when DAV goes LOW. Upon completion of conversion (when DAV is set HIGH), the SHA has acquired the analog input to the specified level of accuracy and will remain in the sample mode until the next ENCODE command. The AD1671 will flag an out-of-range condition when the input voltage exceeds the analog input range. OTR (Pin 15) is active HIGH when an out-of-range high or low condition exists. Bits 1-12 are HIGH when the analog input voltage is greater than the selected input range and LOW when the analog input is less than the selected input range.
AD1671 DYNAMIC PERFORMANCE
SHA OUT
AD1671
BPO / UPO
AD1671
BPO / UPO
REF IN
REF OUT
a. 0 V to +2.5V Input Range
AIN1 5k SHA AIN2 5k
SHA OUT
AD1671
BPO / UPO
AD1671
BPO / UPO
REF IN
REF OUT
c. 0 V to +5 V Input Range
Figure 2. AD1671 Input Range Connections
SIGNAL AMPLITUDE - dB
The AD1671 conversion cycle begins by simply providing an active HIGH level on the ENCODE pin (Pin 17). The rising edge of the ENCODE pulse starts the conversion. The falling edge of the ENCODE pulse is specified to operate within a window of time, less than 50 ns after the rising edge of ENCODE or after the falling edge of DAV. The time window prevents digitally coupled noise from being introduced during the final stages of conversion. An internal timing generator circuit accurately controls SHA, flash and DAC timing. Upon receipt of an ENCODE command the input voltage is held by the front-end SHA and the first 3-bit flash converts the analog input voltage. The 3-bit result is passed to a correction logic register and a segmented current output DAC. The DAC output is connected through a resistor (within the Range / Span Select Block) to SHA OUT. A residue voltage is created by subtracting the DAC output from SHA OUT, which is less than one eighth of the full-scale analog input. The second flash has
FREQUENCY
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AD1671
Figure 4 plots both S / (N+D) and Effective Number of Bits (ENOB) for a 100 kHz input signal sampled from 666 kHz to 1.25 MHz.
SPURIOUS FREE DYNAMIC RANGE - dB
ANALOG INPUT - dB
EFFECTIVE NUMBER OF BITS
APPLYING THE AD1671 GROUNDING AND DECOUPLING RULES
SAMPLING FREQUENCY - kHz
Figure 5 is a THD plot for a full-scale 100 kHz input signal with the sample frequency swept from 666 kHz to 1.25 MHz.
-68 -70 -72 -74 THD - dB -76 -78 -80 -82 -84 -86 666 714 769 833 909 1000 1111 1250 SAMPLING FREQUENCY - kHz
Proper grounding and decoupling should be a primary design objective in any high speed, high resolution system. The AD1671 separates analog and digital grounds to optimize the management of analog and digital ground currents in a system. The AD1671 is designed to minimize the current flowing from REF COM (Pin 20) by directing the majority of the current from VCC (+5 V-Pin 28) to VEE (-5 V-Pin 1). Minimizing analog ground currents hence reduces the potential for large ground voltage drops. This can be especially true in systems that do not utilize ground planes or wide ground runs. REF COM is also configured to be code independent, therefore reducing input dependent analog ground voltage drops and errors. Code dependent ground current is diverted to ACOM (Pin 27). Also critical in any high speed digital design is the use of proper digital grounding techniques to avoid potential CMOS "ground bounce." Figure 3 is provided to assist in the proper layout, grounding and decoupling techniques.
+5V -5V +5V 0.1µF
SPURIOUS FREE DYNAMIC RANGE - dB -68 -70 -72 -74 -76 -78 -80 -82 -84 -86 -88 -90 666 714 769 833 909 1000 SAMPLING FREQUENCY - kHz 1111 1250
0.1µF
28 VCC 23 AIN1
VEE VLOGIC BIT 1 13
AD1671
AGP DGP
ENCODE 17 DAV 16
GROUND PLANE RECOMMENDED
Figure 8. AD1671 Grounding and Decoupling
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AD1671
Table I is a list of grounding and decoupling rules that should be reviewed before laying out a printed circuit board.
Table I. Grounding and Decoupling Guidelines
VIN 0 TO +5V +5V OFFSET R1 ADJ 10k -5V GAIN ADJ 50k AIN1
Power Supply Decoupling Capacitor Values
Comment 0.1 µF (Ceramic) and 1 µF (Tantalum) Surface Mount Chip Capacitors Recommended to Reduce Lead Inductance Directly at Positive and Negative Supply Pins to Common Ground Plane
5k SHA 5k
SHA OUT
AD1671
BPO / UPO REF IN
Capacitor Locations
Reference (REF OUT) Capacitor Value Grounding Analog Ground Ground Plane or Wide Ground Return Connected to the Analog Power Supply Critical Common Connections Should be Star Connected to REF COM (as Shown in Figure 8) Ground Plane or Wide Ground Return Connected to the Digital Power Supply 1 µF (Tantalum) to ACOM
REF OUT
Figure 9. Unipolar (0 V to +5 V) Calibration
BIPOLAR ( 5 V) CALIBRATION
VIN -5V TO +5V +5V OFFSET R1 ADJ 10k -5V GAIN ADJ 50k
Reference Ground (REF COM) Digital Ground
5k SHA 5k
Analog and Digital Ground Connected Together Once at the AD1671
UNIPOLAR (0 V TO +5 V) CALIBRATION
SHA OUT
AD1671
BPO / UPO REF IN
REF OUT 1µF
Bipolar calibration is similar to unipolar calibration. First, a signal 1 / 2 LSB above negative full scale (-4.9988 V) is applied and R1 is trimmed to give the first transition (0000 0000 0000 to 0000 0000 0001). Then a signal 1 1 / 2 LSB below positive full scale (+4.9963 V) is applied and R2 is trimmed to give the last transition (1111 1111 1110 to 1111 1111 1111).
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AD1671
UNIPOLAR (0 V TO +2.5 V) CALIBRATION
The connections for the 0 V to +2.5 V input range calibration is shown in Figure 11. Figure 11 shows an example of how the offset error can be trimmed in front of the AD1671. The procedure for trimming the offset and gain errors is the same as for the unipolar 5 V range.
+15V 390 OFFSET ADJ R1 1k GAIN R2 ADJ 2k AIN1 5k SHA AIN2 1k SHA OUT 5k
and tSS minimum). To satisfy the requirements of the 574 type latch the recommended logic families are S, AS, ALS, F or BCT. New data from the AD1671 is latched on the rising edge of the DAV (Pin 16) output pulse. Previous data can be latched by inverting the DAV output with a 7404 type inverter.
74HC574
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 DAV 1D 2D 3D 4D 5D 6D 7D 8D CLOCK 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OC DATA BUS
VIN 0 TO +2.5V
AD845
74HC574
BIT 9 BIT 10 BIT 11 BIT 12 1D 2D 3D 4D 5D 6D 7D 8D CLOCK 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OC
AD1671
BPO / UPO REF IN
AD1671
REF OUT 1µF
3-STATE CONTROL
Figure 13. AD1671 to Output Latches
OUT OF RANGE
Figure 11. Unipolar (0 V to +2.5 V) Calibration
BIPOLAR ( 2.5 V) CALIBRATION
VIN -2.5V TO +2.5V
390 OFFSET ADJ R1 1k
GAIN R2 ADJ 2k 10k
5k SHA 5k
AD845
AIN2 1k SHA OUT
Table II. Out-of-Range Truth Table
AD1671
BPO / UPO REF IN
Analog Input Is In Range In Range Underrange Overrange
REF OUT 1µF
OUTPUT LATCHES
Figure 13 shows the AD1671 connected to the 74HC574 octal D-type edge-triggered latches with 3-state outputs. The latch can drive highly capacitive loads (i.e., bus lines, I / O ports) while maintaining the data signal integrity. The maximum setup and hold times of the 574 type latch must be less than 20 ns (tDD
Figure 14. Overrange or Underrange Logic
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AD1671
Table III. Output Data Format
Input Range 0 V to +2.5 V
Coding Straight Binary
Analog Inputl
-0.0003 V 0V +2.5 V +2.5003 V
Digital Output 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1000 0000 0000 1000 0000 0000 0111 1111 1111 0111 1111 1111 1000 0000 0000 1000 0000 0000 0111 1111 1111 0111 1111 1111
Straight Binary
-0.0006 V 0V +5 V +5.0006 V -2.5006 V -2.5 V +2.5 V +2.4994 V -5.0012 V -5 V +5 V +4.9988 V
-2.5 V to +2.5 V Offset Binary
Offset Binary
-2.5 V to +2.5 V Twos Complement -2.5006 V (Using MSB) -2.5 V +2.5 V +2.4994 V -5 V to +5 V Twos Complement -5.0012 V (Using MSB) -5 V +5 V +4.9988 V
NOTES 1 Voltages listed are with offset and gain errors adjusted to zero. 2 Typical performance.
OUTPUT DATA FORMAT
The AD1671 provides both MSB and MSB outputs, delivering data in positive true straight binary for unipolar input ranges and positive true offset binary or twos complement for bipolar input ranges. Straight binary coding is used for systems that accept positive-only signals. If straight binary coding is used with bipolar input signals, a 0 V input would result in a binary output of 2048. The application software would have to subtract 2048 to determine the true input voltage. Host registers typically perform math on signed integers and assume data is in that format. Twos complement format minimizes software overhead which is especially important in high speed data transfers, such as a DMA operation. The CPU is not bogged down performing data conversion steps, hence the total system throughput is increased.
OPTIONAL EXTERNAL REFERENCE
connected to +5 V. It is possible to connect REF OUT to +5 V due to its output circuit implementation which shuts down the reference.
ILOGIC VS. CONVERSION RATE
Figure 15 is the typical logic supply current vs. conversion rate for various capacitor loads on the digital outputs.
Figure 15. ILOGIC vs. Conversion Rate for Various Capacitive Loads on the Digital Outputs
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AD1671
APPLICATIONS
AD1671 TO ADSP-2100A AD1671 TO ADSP-2101 / 2102
Figure 16 demonstrates the AD1671 to ADSP-2100A interface. The 2100A with a clock frequency of 12.5 MHz can execute an instruction in one 80 ns cycle. The AD1671 is configured to perform continuous time sampling. The DAV output of the AD1671 is asserted at the end of each conversion. DAV can be used to latch the conversion result into the two 574 octal D-latches. The falling edge of the sampling clock is used to generate an interrupt (IRQ3) for the processor. Upon interrupt, the ADSP-2100A starts a data memory read by providing an address on the DMA bus. The decoded address generates OE for the latches and the processor reads their output over the DMA bus. The conversion result is read within a single processor cycle.
DMRD DMA0:13 ADDRESS BUS DECODE 8
Figure 17 is identical to the 2100A interface except the sampling clock is used to generate an interrupt (IRQ2) for the processor. Upon interrupt the ADSP-2100A starts a data memory read by providing an address on the address (A) bus. The decode address generates OE for the D-latches and the processor reads their output over the Data (D) bus. Reading the conversion result is thus completed within a single processor cycle.
RD A0:13 ADDRESS BUS 8 DAV
Q0:7 8 D0:7 OE
AD1671
ADSP-2101
DECODE
OE DAV
BIT1:12 4 4 ENCODE
D0:15
DATA BUS 8
D0:3 Q0:7 D0:7
Q0:7 8
AD1671
ADSP2100A
DMA0:15 DMACK
SAMPLING CLOCK
16 DATA BUS 8 +5V SAMPLING CLOCK
BIT1:12 4
D0:3 Q0:7 4 D0:7
Figure 17. AD1671 to ADSP-2101 / ADSP-2102 Interface
ENCODE
Figure 16. AD1671 to ADSP-2100A Interface
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AD1671
COMPONENT LIST
Parts List Reference Designator R1, R2 R3, R4, R5 R6 R7 R8 R9, R11 R10 R12 R13 R14 R15-R28 C1, C3, C5 C2, C4, C6, C8, C10 C7, C9, C15, C16 C11, C12, C13, C14, C17 C18 C19-C22 C23 C24 U1 U2 U3 U4-U5 U6 W1-W3 J1-J15 S1 S2 S3 SW1-SW3 TP1, TP2, TP4-TP6 TP3, TP7, TP10, TP13 TP8, TP9, TP11, TP12, TP14 P1
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AD1671
Figure 18. AD1671 / EB PCB Layout-Silkscreen Layer
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AD1671
Figure 19. AD1671 / EB PCB Layout-Component Side
Figure 20. AD1671 / EB PCB Layout-Solder Side
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AD1671
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead PLCC (P-28A) Package
C1616a-10-10 / 93
28-Pin Cerdip (Q-28) Package
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PRINTED IN U.S.A.