AIN1 AIN2 Complete 12-Bit 1.25 MSPS Monolithic Converter AD1671

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AIN1 AIN2 Complete 12-Bit 1.25 MSPS Monolithic Converter AD1671

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FEATURES Conversion Time: 1.25 Throughput Rate Complete: On-Chip Sample-and-Hold Amplifier Voltage Reference Power Dissipation: Missing Codes Guaranteed Signal-to-Noise Plus Distortion Ratio kHz: Configurable Input Voltage Ranges Twos Complement Offset Binary Output Data 28-Pin 28-Pin Surface Mount Package Range Indicator
AIN1 AIN2
Complete 12-Bit 1.25 MSPS Monolithic Converter AD1671
FUNCTIONAL BLOCK DIAGRAM
UPO/BPO ENCODE ACOM VLOGIC DCOM RANGE SELECT
3-BIT FLASH
3-BIT FLASH
COARSE 4-BIT FLASH
8-BIT LADDER MATRIX
2.5V
CORRECTION LOGIC
FINE 4-BIT FLASH
LATCHES
AD1671
PRODUCT DESCRIPTION
AD1671 monolithic 12-bit, 1.25 MSPS analog-todigital converter with on-board, high performance sampleand-hold amplifier (SHA) voltage reference. AD1671 guarantees missing codes over full operating temperature range. combination merged high speed bipolar/ CMOS process novel architecture results combination speed power consumption superior previously available hybrid implementations. Additionally, greater reliability monolithic construction offers improved system reliability lower costs than hybrid designs. fast settling input equally suited both multiplexed systems that switch negative positive full-scale voltage levels successive channels sampling inputs frequencies beyond Nyquist rate. AD1671 provides both reference output reference input pins, allowing on-board reference serve system reference. external reference also chosen suit accuracy temperature drift requirements application. AD1671 uses subranging flash conversion technique, with digital error correction possible errors introduced first part conversion cycle. on-chip timing generator provides strobe pulses each four internal flash cycles. single ENCODE pulse used control converter. digital output data presented twos complement offset binary output format. out-of-range signal indicates overflow condition. used with most significant determine high overflow.
performance AD1671 made possible using high speed, noise bipolar circuitry linear sections power CMOS logic sections. Analog Devices' ABCMOS-1 process provides both high speed bipolar 2-micron CMOS devices single chip. Laser trimmed thin-film resistors used provide accuracy temperature stability. AD1671 available performance grades three temperature ranges. AD1671J grades available over +70°C temperature range. AD1671A grade available over -40°C +85°C temperature range. AD1671S grade available over -55°C +125°C temperature range.
PRODUCT HIGHLIGHTS
AD1671 offers complete single chip sampling 12-bit, 1.25 MSPS analog-to-digital conversion function 28-pin package. AD1671 consumes fraction power currently available hybrids. RANGE output indicates when input signal beyond AD1671's input range. Input signal ranges unipolar bipolar, selected strapping, with input resistance input signal range also strapped +2.5 unipolar ±2.5 bipolar with input resistance Output data available unipolar, bipolar offset bipolar twos complement binary format.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD1671-SPECIFICATIONS
SPECIFICATIONS
Parameter RESOLUTION CONVERSION TIME ACCURACY Integral Nonlinearity (INL) Grade) Differential Nonlinearity (DNL) Missing Codes Unipolar Offsets1 (+25°C) Bipolar Zero1 (+25°C) Gain Error1, (+25°C) TEMPERATURE COEFFICIENTS3 Unipolar Offset Grade) Bipolar Zero Grade) Gain Error3 Grade) Gain Error4 POWER SUPPLY REJECTION5 0.25 Grade) VLOGIC 0.25 Grade) 0.25 Grade) ANALOG INPUT Input Ranges Bipolar Unipolar Input Resistance +2.5 Range) +5.0 Range) Input Capacitance Aperture Delay Aperture Jitter INTERNAL VOLTAGE REFERENCE Output Voltage Output Current Unipolar Mode Bipolar Mode LOGIC INPUTS High Level Input Voltage, Level Input Voltage, High Level Input Current, (VIN VLOGIC) Level Input Current, (VIN Input Capacitance, LOGIC OUTPUTS High Level Output Voltage, (IOH Level Output Voltage, (IOL POWER SUPPLIES Operating Voltages VLOGIC Operating Current ILOGIC6 POWER CONSUMPTION TEMPERATURE RANGE (SPECIFIED)
TMAX with
VLOGIC
AD1671J/A/S
10%,
unless otherwise noted)
AD1671K Units Bits Bits 0.35 ppm/°C ppm/°C ppm/°C ppm/°C
Bits Guaranteed
0.35
Bits Guaranteed
-2.5 -5.0
+2.5 +5.0 +2.5 +5.0
-2.5 -5.0
+2.5 +5.0 +2.5 +5.0
Volts Volts Volts Volts Volts Volts Volts Volts Volts
2.475
2.525 +2.5 +1.0
2.475
2.525 +2.5 +1.0
+4.75 +4.5 -4.75
+5.25 +5.5 -5.25 +125
+4.75 +4.5 -4.75
+5.25 +5.5 -5.25 +125
Volts Volts Volts
NOTES Adjustable zero with external potentiometers. Includes internal voltage reference error. +25°C TMIN +25°C TMAX Excludes internal reference drift. Change gain error function supply voltage. Tested under static conditions. Figure typical curve ILOGIC load capacitance maximum Specifications subject change without notice.
REV.
AD1671 SPECIFICATIONS
Parameter SIGNAL-TO-NOISE PLUS DISTORTION RATIO (S/N -0.5 Input Input EFFECTIVE NUMBER BITS (ENOB) TOTAL HARMONIC DISTORTION (THD) PEAK SPURIOUS PEAK HARMONIC COMPONENT SMALL SIGNAL BANDWIDTH FULL POWER BANDWIDTH INTERMODULATION DISTORTION (IMD) Order Products Order Products
(TMIN TMAX with VLOGIC lNPUT kHz, unless otherwise noted)
10%,
fSAMPLE MSPS,
AD1671K
AD1671J/A/S
Units
11.2
11.2
Bits
NOTES amplitude -0.5 (9.44 p-p) bipolar mode full scale unless otherwise indicated. measurements referred input signal, unless otherwise indicated. kHz, with fSAMPLE MSPS. Specifications subject change without notice.
SWITCHING SPECIFICATIONS
Parameters
(For grades TMIN TMAX with VLO61C 10%,
Symbol tENC tENCL tDAV tDD1 tSS2 1.25 Units MSPS
Conversion Time Sample Rate ENCODE Pulse Width High (Figure ENCODE Pulse Width (Figure Pulse Width ENCODE Falling Edge Delay Start Conversion Delay Data Delay from Falling Edge Data Valid before Rising Edge
NOTES measured from when falling edge crosses when output crosses with load capacitor each output pin. measured from when outputs cross when rising edge crosses with load capacitor each output pin. Specifications subject change without notice.
ENCODE
ENCL
ENCODE
1-12 MSB, DATA (PREVIOUS)
DATA
1-12 MSB, DATA (PREVIOUS)
DATA
Figure Encode Pulse HIGH
Figure Encode Pulse
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AD1671
DESCRIPTION
Symbol ACOM
Type
Name Function Analog Ground. Analog Inputs, AIN1 AIN2. AD1671 strapped four input ranges: Range +2.5 Strap Connect AIN1 AIN2 Connect AIN1 AIN2 ACOM Signal Input AIN1 AIN2 AIN1 AIN2
(MSB) (LSB) BPO/UPO
Most Significant Bit. Data Bits through Least Significant Bit. Bipolar Unipolar Configuration Pin. section Input Range Connections details. Data Available Output. rising edge indicates conversion used latch current data into external register. falling edge used latch previous into external register. Digital Ground. analog input sampled rising edge ENCODE. Inverted Most Significant Bit. Provides twos complement output data format. Range Active HIGH when analog input range. Output Data Format, Table III. internal reference ground pin. should connected indicated Grounding Decoupling Rules Optional External Reference Connection Sections. external reference input. internal reference output. Connect bipolar input ranges. Connect BPO/UPO unipolar input ranges. Analog Power. Analog Power. Digital Power.
2-BIT 12-3
DCOM ENCODE VLOGIC
TYPE: Analog Input; Analog Output; Digital Input; Digital Outputs; Power.
CONFIGURATION
(LSB) ACOM BPO/UPO AIN1 AIN2
AD1671
VIEW (Not Scale)
DCOM VLOGIC ENCODE
(MSB)
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AD1671
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter
With Respect
-6.5 -0.5 -1.0 -6.5 -0.5 -0.5 -11.0 -0.5
+6.5 +0.5 +6.5 +1.0 +6.5 VLOGIC +11.0 +150 +150 +300
Units Volts Volts Volts Volts Volts Volts Volts Volts Volts Model1 AD1671JQ AD1671KQ AD1671JP AD1671KP AD1671AQ AD1671AP AD1671SQ Linearity
ACOM ACOM VLOGIC DCOM ACOM DCOM VLOGIC ENCODE DCOM ACOM ACOM BPO/UPO ACOM Junction Temperature Storage Temperature Lead Temperature sec)
Temperature Range +70°C +70°C +70°C +70°C -40°C +85°C -40°C +85°C -55°C +125°C
Package Option2, Q-28 Q-28 P-28A P-28A Q-28 P-28A Q-28
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum ratings extended periods effect device reliability.
NOTES details grade package offerings screened accordance with MIL-STD-883, refer Analog Devices' Military Products Databook current AD1671/883 data sheet. Plastic Leaded Chip Carrier, Cerdip. Analog Devices reserves right ship side brazed ceramic packages lieu cerdip.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD1671 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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AD1671
DEFINITIONS SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
DYNAMIC SPECIFICATIONS
SIGNAL-TO-NOISE PLUS DISTORTION N+D) RATIO
Integral nonlinearity refers deviation each individual code from line drawn from "zero" through "full scale." point used "zero" occurs (1.22 span) before first code transition (all zeros only on). "Full-scale" defined level beyond last code transition ones). deviation measured from side transition each particular code true straight line.
DIFFERENTIAL LINEARITY ERROR MISSING CODES)
S/N+D ratio value measured input signal other spectral components, including harmonics excluding value S/N+D expressed decibels.
EFFECTIVE NUMBER BITS (ENOB)
ENOB calculated from expression (S/N+D) 6.02N 1.76 where equal effective number bits.
TOTAL HARMONIC DISTORTION (THD)
ideal exhibits code transitions that exactly apart. deviation from ideal value. Thus every code finite width. Guaranteed missing codes 12-bit resolution indicates that 2048 4096 codes, respectively, must present over operating ranges. missing codes bits case 12-bit resolution ADC) also means that consecutive codes missing.
UNIPOLAR OFFSET
ratio first harmonic components value measured input signal expressed percentage decibels.
INTERMODULATION DISTORTION (IMD)
first transition should occur level above analog common. Unipolar offset defined deviation actual from that point. This offset adjusted discussed later. unipolar offset temperature coefficient specifies maximum change transition point over temperature, with without external adjustments.
BIPOLAR ZERO
bipolar mode major carry transition (0111 1111 1111 1000 0000 0000) should occur analog value below analog common. bipolar offset error temperature coefficient specify initial deviation maximum change error over temperature.
GAIN ERROR
With inputs consisting sine waves frequencies, device with nonlinearities will create distortion products order difference frequencies nfb, where Intermodulation terms those which equal zero. example, second order terms fb), third order terms fb), fb), (2fb fa). products expressed decibel ratio measured input signals distortion terms. signals equal amplitude peak value their -0.5 from full scale. products normalized input signal.
PEAK SPURIOUS PEAK HARMONIC COMPONENT
peak spurious peak harmonic component largest spectral component, excluding input signal This value expressed decibels relative value fullscale input signal.
APERTURE DELAY
last transition (from 1111 1111 1110 1111 1111 1111) should occur analog value below nominal full scale (4.9963 volts 5.000 volts full scale). gain error deviation actual level last transition from ideal level. gain error adjusted zero shown Figures through
TEMPERATURE COEFFICIENTS
Aperture delay difference between switch delay analog delay SHA. This delay represents point time, relative rising edge ENCODE input, that analog input sampled.
APERTURE JITTER
temperature coefficients unipolar offset, bipolar zero gain error specify maximum change from initial (+25°C) value value TMIN TMAX.
POWER SUPPLY REJECTION
Aperture jitter variation aperture delay successive samples.
FULL POWER BANDWIDTH
effects power supply error performance device will small change gain. specifications show maximum full-scale change from initial value with supplies various limits.
input frequency which amplitude reconstructed fundamental reduced full-scale input.
REV.
AD1671
THEORY OPERATION
AD1671 uses successive subranging architecture. analog-to-digital conversion takes place four independent steps flashes. sampled analog input signal subranged intermediate residue voltage final 12-bit result utilizing multiple flashes with subtraction DACs (see AD1671 functional block diagram). AD1671 configured operate with unipolar +2.5 bipolar inputs connecting (Pins 23), (Pin BPO/UPO (Pin shown Figure
+2.5V AIN1 AIN2 -2.5V +2.5V AIN1 AIN2
input range that configured with overlap with previous DAC. overlap allows errors during flash conversion. first residue voltage connected second 3-bit flash noninverting input high speed, differential, gain eight amplifier. second flash result passed correction logic register second segmented current output DAC. output second connected inverting input differential amplifier. differential amplifier output connected two-step, backend, 8-bit flash. This 8-bit flash consists coarse fine flash converters. result coarse 4-bit flash converter, also configured overlap connected correction logic register selects resistors from which fine 4-bit flash will establish span voltage. fine 4-bit flash connected directly output latches. internal timing generator automatically places into acquire mode when goes LOW. Upon completion conversion (when HIGH), acquired analog input specified level accuracy will remain sample mode until next ENCODE command. AD1671 will flag out-of-range condition when input voltage exceeds analog input range. (Pin active HIGH when out-of-range high condition exists. Bits 1-12 HIGH when analog input voltage greater than selected input range when analog input less than selected input range.
AD1671 DYNAMIC PERFORMANCE
AD1671
BPO/UPO
AD1671
BPO/UPO
+2.5V Input Range
AIN1 AIN2
Input Range
AIN1 AIN2
AD1671
BPO/UPO
AD1671
BPO/UPO
Input Range
Input Range
AD1671 specified dynamic performance. sampling converter's dynamic performance reflects both quantizer sample-and-hold amplifier (SHA) performance. Quantizer nonlinearities, such DNL, degrade dynamic performance. However, critical element which accurately sample fast slewing analog input signals. AD1671's high performance, noise, patented on-chip minimizes distortion noise specifications. Nonlinearities minimized using fast slewing, noise architecture subregulation sampling switch provide constant offsets (therefore reducing input signal dependent nonlinearities). Figure typical point Fast Fourier Transform (FFT) plot input signal sampled MHz. fundamental amplitude -0.5 avoid input signal clipping offset gain errors. Note total harmonic distortion approximately signal noise plus distortion spurious free dynamic range
Figure AD1671 Input Range Connections
SIGNAL AMPLITUDE
AD1671 conversion cycle begins simply providing active HIGH level ENCODE (Pin 17). rising edge ENCODE pulse starts conversion. falling edge ENCODE pulse specified operate within window time, less than after rising edge ENCODE after falling edge DAV. time window prevents digitally coupled noise from being introduced during final stages conversion. internal timing generator circuit accurately controls SHA, flash timing. Upon receipt ENCODE command input voltage held front-end first 3-bit flash converts analog input voltage. 3-bit result passed correction logic register segmented current output DAC. output connected through resistor (within Range/Span Select Block) OUT. residue voltage created subtracting output from OUT, which less than eighth full-scale analog input. second flash
-100
FREQUENCY
Figure AD1671 Plot, kHz, fSAMPLE
REV.
AD1671
Figure plots both S/(N+D) Effective Number Bits (ENOB) input signal sampled from 1.25 MHz.
72.5 71.5 11.75
SPURIOUS FREE DYNAMIC RANGE
ANALOG INPUT
70.5 69.5 68.5 1000 1111
11.50
11.25
EFFECTIVE NUMBER BITS
S/(N+D)
11.00 1250
Figure Spurious Free Dynamic Range Input Amplitude,
APPLYING AD1671 GROUNDING DECOUPLING RULES
SAMPLING FREQUENCY
Figure S/(N/D) Sampling Frequency,
Figure plot full-scale input signal with sample frequency swept from 1.25 MHz.
1000 1111 1250 SAMPLING FREQUENCY
Figure Sampling Rate,
Proper grounding decoupling should primary design objective high speed, high resolution system. AD1671 separates analog digital grounds optimize management analog digital ground currents system. AD1671 designed minimize current flowing from (Pin directing majority current from V-Pin V-Pin Minimizing analog ground currents hence reduces potential large ground voltage drops. This especially true systems that utilize ground planes wide ground runs. also configured code independent, therefore reducing input dependent analog ground voltage drops errors. Code dependent ground current diverted ACOM (Pin 27). Also critical high speed digital design proper digital grounding techniques avoid potential CMOS "ground bounce." Figure provided assist proper layout, grounding decoupling techniques.
0.1µF
AD1671's SFDR performance ideal communication systems such high speed modems digital radios. SFDR better than with sample rates 1.11 increases input signal amplitude attenuated approximately Note also SFDR typically better than with input signals attenuated
SPURIOUS FREE DYNAMIC RANGE 1000 SAMPLING FREQUENCY 1111 1250
0.1µF
10µF
0.1µF
10µF
10µF
AIN1
VLOGIC
AD1671
(±5V) AIN2 ACOM DCOM BPO/UPO
AGP* DGP*
ENCODE
Figure Spurious Free Dynamic Range Sampling Rate,
*GROUND PLANE RECOMMENDED
Figure AD1671 Grounding Decoupling
REV.
AD1671
Table list grounding decoupling rules that should reviewed before laying printed circuit board.
Table Grounding Decoupling Guidelines
gain trim done applying signal LSBs below nominal full scale (4.998 range). Trim give last transition (1111 1111 1110 1111 1111 1111). This circuit will give approximately 0.5% adjustment range.
OFFSET GAIN AIN1
Power Supply Decoupling Capacitor Values
Comment (Ceramic) (Tantalum) Surface Mount Chip Capacitors Recommended Reduce Lead Inductance Directly Positive Negative Supply Pins Common Ground Plane
AIN2
AD1671
BPO/UPO
Capacitor Locations
Reference (REF OUT) Capacitor Value Grounding Analog Ground Ground Plane Wide Ground Return Connected Analog Power Supply Critical Common Connections Should Star Connected Shown Figure Ground Plane Wide Ground Return Connected Digital Power Supply (Tantalum) ACOM
Figure Unipolar Calibration
BIPOLAR CALIBRATION
connections bipolar input range shown Figure
OFFSET GAIN
Reference Ground (REF COM) Digital Ground
AIN1
AIN2
Analog Digital Ground Connected Together Once AD1671
UNIPOLAR CALIBRATION
AD1671
BPO/UPO
AD1671 factory trimmed minimize offset, gain linearity errors. some applications offset gain errors AD1671 need externally adjusted zero. This accomplished trimming voltage AIN2 (Pin 22). circuit Figure recommended calibrating offset gain errors AD1671 when configured input range. offset trim resistor used, should trimmed follows, although different offset particular system requirement. This circuit will give approximately offset trim range. Nominally AD1671 intended have offset that exact analog input given code will middle that code (halfway between transitions codes above below it). Thus, first transition (from 0000 0000 0000 0000 0000 0001) will occur input level +1/2 (0.61 range).
Figure Bipolar Calibration
Bipolar calibration similar unipolar calibration. First, signal above negative full scale (-4.9988 applied trimmed give first transition (0000 0000 0000 0000 0000 0001). Then signal below positive full scale (+4.9963 applied trimmed give last transition (1111 1111 1110 1111 1111 1111).
REV.
AD1671
UNIPOLAR +2.5 CALIBRATION
connections +2.5 input range calibration shown Figure Figure shows example offset error trimmed front AD1671. procedure trimming offset gain errors same unipolar range.
+15V OFFSET GAIN AIN1 AIN2
minimum). satisfy requirements type latch recommended logic families ALS, BCT. data from AD1671 latched rising edge (Pin output pulse. Previous data latched inverting output with 7404 type inverter.
74HC574
CLOCK DATA
+2.5V
AD845
74HC574
CLOCK
AD1671
BPO/UPO
AD1671
3-STATE CONTROL
Figure AD1671 Output Latches
RANGE
Figure Unipolar +2.5 Calibration
connections bipolar input range shown Figure
+15V
BIPOLAR CALIBRATION
-2.5V +2.5V
OFFSET
GAIN
AIN1
AD845
AIN2
out-of-range condition exists when analog input voltage beyond input range +2.5 converter (Pin when analog input voltage within analog input range. HIGH will remain HIGH when analog input voltage exceeds input range typically (OTR transition tested LSBs accuracy) from center full-scale output codes. will remain HIGH until analog input within input range another conversion completed. logical ANDing with complement, overrange high underrange conditions detected. Table truth table over/under range circuit Figure Systems requiring programmable gain conditioning prior AD1671 immediately detect out-of-range condition, thus eliminating gain selection iterations.
Table Out-of-Range Truth Table
AD1671
BPO/UPO
Analog Input Range Range Underrange Overrange
Figure Bipolar Calibration
OUTPUT LATCHES
Figure shows AD1671 connected 74HC574 octal D-type edge-triggered latches with 3-state outputs. latch drive highly capacitive loads (i.e., lines, ports) while maintaining data signal integrity. maximum setup hold times type latch must less than (tDD
OVER
UNDER
Figure Overrange Underrange Logic
-10-
REV.
AD1671
Table III. Output Data Format
Input Range +2.5
Coding Straight Binary
Analog Inputl
-0.0003 +2.5 +2.5003
Digital Output 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1000 0000 0000 1000 0000 0000 0111 1111 1111 0111 1111 1111 1000 0000 0000 1000 0000 0000 0111 1111 1111 0111 1111 1111
OTR2
Straight Binary
-0.0006 +5.0006 -2.5006 -2.5 +2.5 +2.4994 -5.0012 +4.9988
-2.5 +2.5 Offset Binary
Offset Binary
-2.5 +2.5 Twos Complement -2.5006 (Using MSB) -2.5 +2.5 +2.4994 Twos Complement -5.0012 (Using MSB) +4.9988
NOTES Voltages listed with offset gain errors adjusted zero. Typical performance.
OUTPUT DATA FORMAT
AD1671 provides both outputs, delivering data positive true straight binary unipolar input ranges positive true offset binary twos complement bipolar input ranges. Straight binary coding used systems that accept positive-only signals. straight binary coding used with bipolar input signals, input would result binary output 2048. application software would have subtract 2048 determine true input voltage. Host registers typically perform math signed integers assume data that format. Twos complement format minimizes software overhead which especially important high speed data transfers, such operation. bogged down performing data conversion steps, hence total system throughput increased.
OPTIONAL EXTERNAL REFERENCE
connected possible connect output circuit implementation which shuts down reference.
ILOGIC CONVERSION RATE
Figure typical logic supply current conversion rate various capacitor loads digital outputs.
100k CONVERSION RATE 30pF
50pF
AD1671 includes onboard +2.5 reference. reference input (REF connected reference output (REF OUT) standard external +2.5 reference selected meet specific system requirements. Fast switching input dependent currents modulated reference input. reference input voltage held with capacitor. prevent AD1671's onboard reference from oscillating when connected must
Figure ILOGIC Conversion Rate Various Capacitive Loads Digital Outputs
REV.
-11-
AD1671
APPLICATIONS
AD1671 ADSP-2100A AD1671 ADSP-2101/2102
Figure demonstrates AD1671 ADSP-2100A interface. 2100A with clock frequency 12.5 execute instruction cycle. AD1671 configured perform continuous time sampling. output AD1671 asserted each conversion. used latch conversion result into octal D-latches. falling edge sampling clock used generate interrupt (IRQ3) processor. Upon interrupt, ADSP-2100A starts data memory read providing address bus. decoded address generates latches processor reads their output over bus. conversion result read within single processor cycle.
DMRD DMA0:13 ADDRESS DECODE
Figure identical 2100A interface except sampling clock used generate interrupt (IRQ2) processor. Upon interrupt ADSP-2100A starts data memory read providing address address bus. decode address generates D-latches processor reads their output over Data bus. Reading conversion result thus completed within single processor cycle.
A0:13 ADDRESS
Q0:7 D0:7
AD1671
ADSP-2101
DECODE
BIT1:12 ENCODE
D0:15
DATA
D0:3 Q0:7 D0:7
Q0:7
AD1671
IRQ2
ADSP2100A
DMA0:15 DMACK
D0:7
SAMPLING CLOCK
DATA SAMPLING CLOCK
BIT1:12
D0:3 Q0:7 D0:7
Figure AD1671 ADSP-2101/ADSP-2102 Interface
IRQ3
ENCODE
Figure AD1671 ADSP-2100A Interface
-12-
REV.
AD1671
COMPONENT LIST
Parts List Reference Designator R15-R28 C15, C11, C12, C13, C14, C19-C22 U4-U5 W1-W3 J1-J15 SW1-SW3 TP1, TP2, TP4-TP6 TP3, TP7, TP10, TP13 TP8, TP9, TP11, TP12, TP14
Type Description Resistor, Resistor, 49.9 Trim Potentiometer Resistor 4.99 Optional Trim Potentiometer, Optional Resistor, 4.99 Resistor, Resistor, 2.49 Resistor, Resistor, Resistor, Cap, Tantalum, Cap, Ceramic, 0.01 Cap, Tantalum, Cap, Ceramic, Cap, Ceramic, Cap, Ceramic, Cap, Mica, Cap, Ceramic, 0.001 78L05 Regulator 79L05 Regulator AD1671 74HC573 Drivers AD568 Jacks Jumpers Headers Metal Binding Posts Wide 28-Pin Socket Narrow 20-Pin Socket Narrow 24-Pin Socket SECMA SPDT Switch Test Point, Test Point, Black Test Point, White 40-Pin Connector Male Hooks
REV.
-13-
AD1671
Figure AD1671/EB Layout-Silkscreen Layer
-14-
REV.
AD1671
Figure AD1671/EB Layout-Component Side
Figure AD1671/EB Layout-Solder Side
REV.
-15-
AD1671
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Lead PLCC (P-28A) Package
C1616a-10-10/93
28-Pin Cerdip (Q-28) Package
-16-
REV.
PRINTED U.S.A.

AIN1 AIN2 Complete 12-Bit 1.25 MSPS Monolithic Converter AD1671

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