CMOS High Performance Programmable Controller 82C37A enhanced ver
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82C37A
CMOS High Performance Programmable Controller
82C37A enhanced version industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Harris' advanced micron CMOS process. compatible with NMOS designs, 82C37A offers increased functionality, improved performance, dramatically reduced power consumption. fully static design permits gated clock operation even further reduction power. 82C37A controller improve system performance allowing external devices transfer data directly from system memory. Memory-to-memory transfer capability also provided, along with memory block initialization feature. requests generated either hardware software, each channel independently programmable with variety features flexible operation. 82C37A designed used with external address latch, such 82C82, demultiplex most significant 8-bits address. 82C37A used with industry standard microprocessors such 80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 others. Multimode programmability allows user select from three basic types services, reconfiguration under program control possible even with clock controller stopped. Each channel full address word count range, programmed autoinitialize these registers following termination (end process).
March 1997
Features
Compatible with NMOS 8237A Four Independent Maskable Channels with Autoinitialization Capability Cascadable Number Channels High Speed Data Transfers: 4MBytes/sec with 8MHz Clock 6.25MBytes/sec with 12.5MHz Clock Memory-to-Memory Transfers Static CMOS Design Permits Power Operation ICCSB 10µA Maximum ICCOP 2mA/MHz Maximum Fully TTL/CMOS Compatible Internal Registers Read from Software
Ordering Information
PART NUMBER 5MHz CP82C37A-5 IP82C37A-5 CS82C37A-5 IS82C37A-5 CD82C37A-5 ID82C37A-5 MD82C37A-5/B 5962-9054301MQA MR82C37A-5/B 5962-9054301MXA 8MHz CP82C37A IP82C37A CS82C37A IS82C37A CD82C37A ID82C37A MD82C37A/B 5962-9054302MQA MR82C37A/B 5962-9054302MXA 12.5MHz CP82C37A-12 IP82C37A-12 CS82C37A-12 IS82C37A-12 CD82C37A-12 ID82C37A-12 MD82C37A-12/B 5962-9054303MQA MR82C37A-12/B 5962-9054303MXA SMD# CLCC SMD# -55oC +125oC CERDIP PLCC PACKAGE PDIP TEMPERATURE RANGE +70oC -40oC +85oC +70oC -40oC +85oC +70oC -40oC +85oC -55oC +125oC PKG. E40.6 E40.6 N44.65 N44.65 F40.6 F40.6 F40.6 F40.6 J44.A J44.A
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
Harris Corporation 1997
File Number
2967.1
4-192
82C37A Pinouts
82C37A (PDIP/CERDIP) VIEW
READY
82C37A (CLCC/PLCC) VIEW
MEMW MEMR DREQ3 DREQ2 DREQ1 DREQ0 DACK3 DACK1 DACK0
MEMR MEMW READY HLDA ADSTB RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 (GND)
DACK0 DACK1
HLDA ADSTB RESET DACK2
Block Diagram
RESET READY ADSTB MEMR MEMW TIMING CONTROL DECREMENTOR TEMP WORD COUNT (16) 16-BIT 16-BIT READ BUFFER BASE ADDRESS (16) BASE WORD COUNT (16) READ WRITE BUFFER CURRENT ADDRESS (16) CURRENT WORD COUNT (16) OUTPUT BUFFER INC/DECREMENTOR TEMP ADDRESS (16) BUFFER
COMMAND CONTROL
WRITE BUFFER
READ BUFFER
DREQ0 DREQ3 HLDA DACK0 DACK3
REQUEST
MODE
STATUS
TEMPORARY
4-193
PRIORITY ENCODER ROTATING PRIORITY LOGIC
COMMAND MASK
INTERNAL DATA
BUFFER
82C37A SYMBOL NUMBER TYPE DESCRIPTION VCC: power supply pin. 0.1µF capacitor between pins recommended decoupling. Ground CLOCK INPUT: Clock Input used generate timing signals which control 82C37A operations. This input driven from 12.5MHz 82C37A-12, from 8MHz 82C37A, from 5MHz 82C37A-5. Clock stopped either state standby operation. CHIP SELECT: Chip Select active input used enable controller onto data communications. RESET: This active high input which clears Command, Status, Request, Temporary registers, First/Last Flip-Flop, mode register counter. Mask register ignore requests. Following Reset, controller idle cycle. READY: This signal used extend memory read write pulses from 82C37A accommodate slow memories devices. READY must make transitions during specified set-up hold times. Figure timing. READY ignored verify transfer mode. HOLD ACKNOWLEDGE: active high Hold Acknowledge from indicates that relinquished control system busses. HLDA synchronous input must transition during specified set-up time. There implied hold time (HLDA inactive) from rising edge CLK, during which time HLDA must transition. REQUEST: Request (DREQ) lines individual asynchronous channel request inputs used peripheral circuits obtain service. Fixed Priority, DREQ0 highest priority DREQ3 lowest priority. request generated activating DREQ line channel. DACK will acknowledge recognition DREQ signal. Polarity DREQ programmable. RESET initializes these lines active high. DREQ must maintained until corresponding DACK goes active. DREQ will recognized while clock stopped. Unused DREQ inputs should pulled High (inactive) corresponding mask set. DATA BUS: Data lines bidirectional three-state signals connected system data bus. outputs enabled Program condition during Read output contents register CPU. outputs disabled inputs read during Write cycle when programming 82C37A control registers. During cycles, most significant 8-bits address output onto data strobed into external latch ADSTB. memory-to-memory operations, data from memory enters 82C37A data during read-from-memory transfer, then during write-to-memory transfer, data outputs write data into memory location. READ: Read bidirectional active three-state line. Idle cycle, input control signal used read control registers. Active cycle, output control signal used 82C37A access data from peripheral during Write transfer. WRITE: Write bidirectional active three-state line. Idle cycle, input control signal used load information into 82C37A. Active cycle, output control signal used 82C37A load data peripheral during Read transfer.
RESET
READY
HLDA
DREQ0DREQ3
16-19
DB0-DB7
21-23 26-30
4-194
82C37A SYMBOL NUMBER (Continued)
TYPE
DESCRIPTION PROCESS: Process (EOP) active bidirectional signal. Information concerning completion services available bidirectional pin. 82C37A allows external signal terminate active service pulling low. pulse generated 82C37A when terminal count (TC) channel reached, except channel memory-to-memory mode. During memory-to-memory transfers, will output when channel occurs. driven open drain transistor on-chip, requires external pull-up resistor VCC. When pulse occurs, whether internally externally generated, 82C37A will terminate service, autoinitialize enabled, base registers will written current registers that channel. mask status word will currently active channel unless channel programmed autoinitialize. that case, mask remains clear.
A0-A3
32-35
ADDRESS: four least significant address lines bidirectional three-state signals. Idle cycle, they inputs used 82C37A address control register loaded read. Active cycle, they outputs provide lower 4-bits output address. ADDRESS: four most significant address lines three-state outputs provide 4-bits address. These lines enabled only during service. HOLD REQUEST: Hold Request (HRQ) output used request control system bus. When DREQ occurs corresponding mask clear, software request made, 82C37A issues HRQ. HLDA signal then informs controller when access system busses permitted. stand-alone operation where 82C37A always controls busses, tied HLDA. This will result state before transfer. ACKNOWLEDGE: acknowledge used notify individual peripherals when been granted cycle. sense these lines programmable. RESET initializes them active low. ADDRESS ENABLE: Address Enable enables 8-bit latch containing upper address bits onto system address bus. also used disable other system drivers during transfers. active high. ADDRESS STROBE: This active high signal used control latching upper address byte. will drive directly strobe input external transparent octal latches, such 82C82. During block operations, ADSTB will only issued when upper address byte must updated, thus speeding operation through elimination states. ADSTB timing referenced falling edge 82C37A clock. MEMORY READ: Memory Read signal active three-state output used access data from selected memory location during Read memory-to-memory transfer. MEMORY WRITE: Memory Write signal active three-state output used write data selected memory location during Write memory-to-memory transfer. CONNECT: open should tested continuity.
A4-A7
37-40
DACK0DACK3
ADSTB
MEMR
MEMW
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82C37A Functional 82C37A direct memory access controller designed improve data transfer rate systems which must transfer data from device memory, move block memory device. will also perform memory-tomemory block moves, fill block memory with data from single location. Operating modes provided handle single byte transfers well discontinuous data streams, which allows 82C37A control data movement with software transparency. controller state-driven address control signal generator, which permits data transferred directly from device memory vice versa without ever being stored temporary register. This greatly increase data transfer rate sequential operations, compared with processor move repeated string instructions. Memory-to-memory operations require temporary internal storage data byte between generation source destination addresses, memory-to-memory transfers take place less than half rate operations, still much faster than with central processor techniques. maximum data transfer rates obtainable with 82C37A shown Figure block diagram 82C37A shown page timing control block, priority block, internal registers main components. Figure lists name size internal registers. timing control block derives internal timing from clock input, generates external control signals. Priority Encoder block resolves priority contention between channels requesting service simultaneously.
82C37A TRANSFER TYPE Compressed Normal Memory-toMemory
example, block data transferred from device, starting address data loaded into 82C37A Current Base Address registers particular channel, length block loaded into channel's Word Count register. corresponding Mode register programmed memory-to-I/O operation (read transfer), various options selected Command register other Mode register bits. channel's mask cleared enable recognition request (DREQ). DREQ either hardware signal software command. Once initiated, block transfer will proceed controller outputs data address, simultaneous MEMR pulses, selects device acknowledge (DACK) outputs. data byte flows directly from device. After each byte transferred, address automatically incremented decremented) word count decremented. operation then repeated next byte. controller stops transferring data when Word Count register underflows, external applied.
NAME Base Address Registers Base Word Count Registers Current Address Registers Current Word Count Registers Temporary Address Register SIZE 16-Bits 16-Bits 16-Bits 16-Bits 16-Bits 16-Bits 8-Bits 8-Bits 8-Bits 6-Bits 4-Bits 4-Bits NUMBER
5MHz 2.50 1.67 0.63
8MHz 4.00 2.67 1.00
12.5MHz 6.25 4.17 1.56
UNIT MByte/sec MByte/sec MByte/sec
Temporary Word Count Register Status Register Command Register Temporary Register Mode Registers
FIGURE TRANSFER RATES
Mask Register Request Register
Operation
system, 82C37A address control outputs data pins basically connected parallel with system busses. external latch required upper address byte. While inactive, controller's outputs high impedance state. When activated request control relinquished host, 82C37A drives busses generates control signals perform data transfer. operation performed activating four request inputs previously been programmed into controller Command, Mode, Address, Word Count registers.
FIGURE 82C37A INTERNAL REGISTERS
further understand 82C37A operation, states generated each clock cycle must considered. controller operates major cycles, active idle. After being programmed, controller normally idle until request occurs unmasked channel, software request given. 82C37A will then request control system busses enter active cycle. active cycle composed several internal states, depending what options have been selected what type operation been requested.
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82C37A
82C37A assume seven separate states, each composed full clock period. State (SI) idle state. entered when 82C37A valid requests pending, transfer sequence, when Reset Master Clear occurred. While controller inactive Program Condition (being programmed processor). State (S0) first state service. 82C37A requested hold processor returned acknowledge. 82C37A still programmed until received HLDA from CPU. acknowledge from will signal transfer begin. working state service. more time needed complete transfer than available with normal timing, wait states (SW) inserted between normal transfers Ready line 82C37A. compressed transfers, wait states inserted between timing Figures Note that data transferred directly from device memory vice versa) with MEMW MEMR IOW) being active same time. data read into driven 82C37A I/O-to-memory memory-to-I/O transfers. Memory-to-memory transfers require read-from writeto memory complete each transfer. states, which resemble normal working states, two-digit numbers identification. Eight states required single transfer. first four states (S11, S12, S13, S14) used read-from-memory half last four state (S21, S22, S23, S24) write-to-memory half transfer. Special software commands executed 82C37A Program Condition. These commands decoded sets addresses with IOR, IOW. commands make data bus. Instructions include Clear First/Last Flip-Flop, Master Clear, Clear Mode Register Counter, Clear Mask Register.
Active Cycle
When 82C37A Idle cycle, software request unmasked channel requests service, device will issue microprocessor enter Active cycle. this cycle that service will take place, four modes: Single Transfer Mode Single Transfer mode, device programmed make transfer only. word count will decremented address decremented incremented following each transfer. When word count "rolls over" from zero FFFFH, terminal count status register set, pulse generated, channel will autoinitialize this option been selected. programmed autoinitialize, mask will set, along with pulse. DREQ must held active until DACK becomes active. DREQ held active throughout single transfer, will inactive release system. will again active and, upon receipt HLDA, another single transfer will performed, unless higher priority channel takes over. 8080A, 8085A, 80C88, 80C86 systems, this will ensure full machine cycle execution between transfers. Details timing between 82C37A other control protocols will depend upon characteristics microprocessor involved. Block Transfer Mode Block Transfer mode, device activated DREQ software request continues making transfers during service until caused word count going FFFFH, external Process (EOP) encountered. DREQ need only held active until DACK becomes active. Again, Autoinitialization will occur service channel been programmed that option. Demand Transfer Mode Demand Transfer mode device continues making transfers until external encountered, until DREQ goes inactive. Thus, transfer continue until device exhausted data capacity. After device chance catch service reestablished means DREQ. During time between services when microprocessor allowed operate, intermediate values address word count stored 82C37A Current Address Current Word Count registers. Higher priority channels intervene demand process, once DREQ gone inactive. Only cause Autoinitialization service. generated either external signal. Cascade Mode This mode used cascade more than 82C37A simple system expansion. HLDA signals from additional 82C37A connected DREQ DACK signals respectively channel
Idle Cycle
When channel requesting service, 82C37A will enter idle cycle perform "SI" states. this cycle, 82C37A will sample DREQ lines falling edge every clock cycle determine channel requesting service. Note that standby operation where clock been stopped, requests will ignored. device will respond (chip select), case attempt microprocessor write read internal registers 82C37A. When HLDA low, 82C37A enters Program Condition. establish, change inspect internal definition part reading from writing internal registers. 82C37A programmed with clock stopped, provided that HLDA least rising clock edge occurred after HLDA driven low, controller state. Address lines A0-A3 inputs device select which registers will read written. lines used select time read write operations. number size internal registers, internal flip-flop called First/Last Flip-Flop used generate additional address. used determine upper lower byte 16-bit Address Work Count registers. flipflop reset Master Clear RESET. Separate software commands also reset this flip-flop.
4-197
82C37A
initial 82C37A.This allows requests additional device propagate through priority network circuitry preceding device. priority chain preserved device must wait turn acknowledge requests. Since cascade channel initial 82C37A used only prioritizing additional device, does output address control signals own. These could conflict with outputs active channel added device. initial 82C37A will respond DREQ generate DACK other outputs except will disabled. external will ignored initial device, will have usual effect added device. Figure shows additional devices cascaded with initial device using initial device's channels. This forms two-level system. More 82C37As could added second level using remaining channels first level. Additional devices also added cascading into channels second level devices, forming third level.
LEVEL 80C86/88 MICROPROCESSOR
Autoinitialize setting Mode register, channel Autoinitialize channel. During Autoinitialization, original values Current Address Current Word Count registers automatically restored from Base Address Base Word Count registers channel following EOP. base registers loaded simultaneously with current registers microprocessor remain unchanged throughout service. mask when channel Autoinitialize mode. Following Autoinitialization, channel ready perform another service, without intervention, soon valid DREQ detected, software request made. Memory-to-Memory perform block moves data from memory address space another with minimum program effort time, 82C37A includes memory-tomemory transfer feature. Setting Command register selects channels operate memory-tomemory transfer channels. transfer initiated setting software hardware DREQ channel 82C37A requests service normal manner. After HLDA true, device, using four-state transfers Block Transfer mode, reads data from memory. channel Current Address register source address used decremented incremented normal manner. data byte read from memory stored 82C37A internal Temporary register. Another four-state transfer moves data memory using address channel one's Current Address register incrementing decrementing normal manner. channel Current Word Count decremented. When word count channel decrements FFFFH, generated causing output, terminating service, setting channel Status register. channel mask will also set, unless channel mode register programmed autoinitialization. Channel word count decrementing FFFFH will channel status register generate EOP, channel mask this mode. will cause autoinitialization channel that option been selected. full Autoinitialization memory-to-memory operation desired, channel channel word counts must equal values before transfer begins. Otherwise, channel underflows before channel will autoinitialize data source address back beginning block. channel word count underflows before channel memory-to-memory service will terminate, channel will autoinitialize channel will not. memory-to-memory mode, Channel programmed retain same address transfers. This allows single byte written block memory. This channel address hold feature selected setting Command register. 82C37A will respond external signals during memory-to-memory transfers, will only relinquish system busses after transfer complete (i.e. after
LEVEL HLDA DREQ DACK
82C37A HLDA
82C37A DREQ DACK INITIAL DEVICE HLDA 82C37A
ADDITIONAL DEVICES
FIGURE CASCADED 82C37As
When programming cascaded controllers, start with first level device (closest microprocessor). After RESET, DACK outputs programmed active held high state. they used drive HLDA directly, second level device(s) cannot programmed until DACK polarity selected active high initial device. Also, initial device's mask bits function normally cascaded channels, they used inhibit secondlevel services.
Transfer Types
Each three active transfer modes perform three different types transfers. These Read, Write Verify. Write transfers move data from device memory activating MEMW IOR. Read transfers move data from memory device activating MEMR IOW. Verify transfers pseudo-transfers. 82C37A operates Read Write transfers generating addresses responding EOP, etc., however memory control lines remain inactive. Verify mode permitted memory-to-memory operation. READY ignored during Verify transfers.
4-198
82C37A
state). should noted that external cannot cause channel Address Word Count registers autoinitialize, even Mode register programmed autoinitialization. external will autoinitialize channel registers, programmed. Data comparators block search schemes input terminate service when match found. timing memory-tomemory transfers found Figure Memory-to-memory operations detected active with DACK outputs. Priority 82C37A types priority encoding available software selectable options. first Fixed Priority which fixes channels priority order based upon descending value their numbers. channel with lowest priority followed highest priority channel, After recognition channel service, other channels prevented from interfering with service until completed. second scheme Rotating Priority. last channel service becomes lowest priority channel with others rotating accordingly. next lower channel from channel serviced highest priority following request. Priority rotates every time control system busses returned processor. Rotating Priority
SERVICE Highest Lowest Service SERVICE Service Request SERVICE Service
address bits external latch from which they placed address bus. falling edge Address Strobe (ADSTB) used load these bits from data lines latch. Address Enable (AEN) used enable bits onto address through three-state enable. lower order address bits output 82C37A directly. Lines A0-A7 should connected address bus. Figure shows time relationships between CLK, AEN, ADSTB, DB0-DB7 A0-A7. During Block Demand Transfer mode service, which include multiple transfers, addresses generated will sequential. many transfers data held external address latch will remain same. This data need only change when carry borrow from takes place normal sequence addresses. save time speed transfers, 82C37A executes states only when updating A8-A15 latch necessary. This means long services, states Address Strobes occur only once every transfers, savings clock cycles each transfers.
Programming
82C37A will accept programming from host processor anytime that HLDA inactive, least rising clock edge occurred after HLDA went low. responsibility host assure that programming HLDA mutually exclusive. Note that problem occur request occurs unmasked channel while 82C37A being programmed. instance, starting reprogram byte Address register channel when channel receives request. 82C37A enabled (bit Command register channel unmasked, service will occur after only byte Address register been reprogrammed. This condition avoided disabling controller (setting Command register) masking channel before programming registers. Once programming complete, controller enabled/unmasked. After power-up suggested that internal locations loaded with some known value, even some channels unused. This will debugging.
With Rotating Priority single chip system, device requesting service guaranteed recognized after more than three higher priority services have occurred. This prevents channel from monopolizing system. Regardless which priority scheme chosen, priority evaluated every time HLDA returned 82C37A. Compressed Timing order achieve even greater throughput where system characteristics permit, 82C37A compress transfer time clock cycles. From Figure seen that state used extend access time read pulse. removing state read pulse width made equal write pulse width transfer consists only state change address state perform read/write. states will still occur when A8-A15 need updating (see Address Generation). Timing compressed transfers found Figure will output compressed timing selected. Compressed timing allowed memory-tomemory transfers. Address Generation order reduce count, 82C37A multiplexes eight higher order address bits data lines. State used output higher order
Register Current Address Register Each channel 16-bit Current Address register. This register holds value address used during transfers. address automatically incremented decremented after each transfer values address stored Current Address register during transfer. This register written read microprocessor successive 8-bit bytes. Figure programming information. also reinitialized Autoinitialize back original value. Autoinitialize takes place only after EOP. memory-tomemory mode, channel Current Address register prevented from incrementing decrementing setting address hold Command register.
4-199
82C37A
Current Word Count Register Each channel 16-bit Current Word Count register. This register determines number transfers performed. actual number transfers will more than number programmed Current Word Count register (i.e., programming count will result transfers). word count decremented after each transfer. When value register goes from zero FFFFH, will generated. This register loaded read successive 8-bit bytes microprocessor Program Condition. Figure programming information. Following service also reinitialized Autoinitialization back original value. Autoinitialization occur only when occurs. Autoinitialized, this register will have count FFFFH after Base Address Base Word Count Registers Each channel pair Base Address Base Word Count registers. These 16-bit registers store original value their associated current registers. During Autoinitialize these values used restore current registers their original values. base registers written simultaneously with their corresponding current register 8-bit bytes Program Condition microprocessor. Figure programming information. These registers cannot read microprocessor. Command Register This 8-bit register controls operation 82C37A. programmed microprocessor cleared RESET Master Clear instruction. following diagram lists function Command register bits. Figure Read Write addresses. Command Register
NUMBER Memory-to-memory disable Memory-to-memory enable Channel address hold disable Channel address hold enable Controller enable Controller disable Normal timing Compressed timing Fixed priority Rotating priority Late write selection Extended write selection DREQ sense active high DREQ sense active DACK sense active DACK sense active high
Mode Register Each channel 6-bit Mode register associated with When register being written microprocessor Program condition, bits determine which channel Mode register written. When processor reads Mode register, bits will both ones. following diagram Figure Mode register functions addresses. Mode Register
NUMBER Channel select Channel select Channel select Channel select Readback Verify transfer Write transfer Read transfer Illegal bits Autoinitialization disable Autoinitialization enable Address increment select Address decrement select Demand mode select Single mode select Block mode select Cascade mode select
Request Register 82C37A respond requests service which initiated software well DREQ. Each channel request associated with 4-bit Request register. These non-maskable subject prioritization Priority Encoder network. Each register reset separately under software control. entire register cleared Reset Master Clear instruction. reset bit, software loads proper form data word. Figure register address coding, following diagram Request register format. software request operation made block single modes. memory-to-memory transfers, software request channel should set. When reading Request register, bits will always read ones, bits will display request bits channels respectively. Request Register
Don't Care, Write Bits Ones, Read NUMBER Select Channel Select Channel Select Channel Select Channel Reset request request
4-200
82C37A
Mask Register Each channel associated with mask which disable incoming DREQ. Each mask when associated channel produces channel programmed Autoinitialize. Each 4-bit Mask register also cleared separately simultaneously under software control. entire register also Reset Master clear. This disables hardware requests until Clear Mask Register instruction allows them occur. instruction separately clear mask bits similar form that used with Request register. Refer following diagram Figure details. When reading Mask register, bits will always read logical ones, bits will display mask bits channels 0-3, respectively. bits Mask register cleared simultaneously using Clear Mask Register command (see software commands section). Mask Register
Don't Care NUMBER Channel reached Select Channel mask Select Channel mask Select Channel mask Select Channel mask Clear mask mask Channel reached Channel reached Channel reached Channel request Channel request Channel request Channel request
Status Register Status register available read 82C37A microprocessor. contains information about status devices this point. This information includes which channels have reached terminal count which channels have pending requests. Bits every time reached that channel external applied. These bits cleared upon RESET, Master Clear, each Status Read. Bits whenever their corresponding channel requesting service, regardless mask state. mask bits set, software poll Status register determine which channels have DREQs, selectively clear mask bit, thus allowing user defined service priority. Status bits updated while clock high, latched falling edge. Status Bits cleared upon RESET Master Clear. Status Register
NUMBER
four bits Mask register also written with single command.
Don't Care, Write Ones, Read NUMBER Clear Channel mask Channel mask Clear Channel mask Channel mask Clear Channel mask Channel mask Clear Channel mask Channel mask
Temporary Register Temporary register used hold data during memory-to-memory transfers. Following completion transfers, last byte moved read microprocessor. Temporary register always contains last byte transferred previous memory-tomemory operation, unless cleared Reset Master Clear.
OPERATION Read Status Register Write Command Register Read Request Register Write Request Register Read Command Register Write Single Mask Read Mode Register Write Mode Register First/Last Clear First/Last Read Temporary Register Master Clear Clear Mode Reg. Counter Clear Mask Register Read Mask Bits Write Mask Bits
FIGURE SOFTWARE COMMAND CODES REGISTER CODES
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82C37A Software Commands
There special software commands which executed reading writing 82C37A. These commands depend specific data pattern data bus, activated operation itself. read type commands, data value guaranteed. These commands are: Clear First/Last Flip-Flop This command executed prior writing reading address word count information 82C37A. This command initializes flip-flop known state (low byte first) that subsequent accesses register contents microprocessor will address upper lower bytes correct sequence. First/Last Flip-Flop This command will flip-flop select high byte first read write operations address word count registers. Master Clear This software instruction same effect hardware Reset. Command, Status, Request, Temporary registers, Internal First/Last Flip-Flop mode register counter cleared Mask register set. 82C37A will enter idle cycle. Clear Mask Register This command clears mask bits four channels, enabling them accept requests. Clear Mode Register Counter Since only address location available reading Mode registers, internal two-bit counter been included select Mode registers during read operation. read Mode registers, first execute Clear Mode Register Counter command, then consecutive reads until desired channel read. Read order channel first, channel last. lower bits Mode registers will read ones.
External Operation
bidirectional, open drain which driven external signals terminate operation. Because open drain external pull-up resistor required. value external pull-up resistor used should guarantee rise time less than 125ns. important note that 82C37A will accept external signals when (Idle) state. controller must active latch EOP. Once latched, will acted upon during next state, unless 82C37A enters idle state first. latter case, latched cleared. External pulses occurring between active transfers demand mode will recognized, since 82C37A state.
SIGNALS FIRST/LAST FLIP-FLOP STATE DATA DB0-DB7 A0-A7 A8-A15 A0-A7 A8-A15 W0-W7 W8-W15 W0-W7 W8-W15 A0-A7 A8-A15 A0-A7 A8-A15 W0-W7 W8-W15 W0-W7 W8-W15 A0-A7 A8-A15 A0-A7 A8-A15 W0-W7 W8-W15 W0-W7 W8-W15 A0-A7 A8-A15 A0-A7 A8-A15 W0-W7 W8-W15 W0-W7 W8-W15
CHANNEL
REGISTER Base Current Address Current Address Base Current Word Count Current Word Count
OPERATION Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read
Base Current Address Current Address Base Current Word Count Current Word Count
Base Current Address Current Address Base Current Word Count Current Word Count
Base Current Address Current Address Base Current Word Count Current Word Count
FIGURE WORD COUNT ADDRESS REGISTER COMMAND CODES
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82C37A Application Information
Figure shows application system utilizing 82C37A controller 80C88 Microprocessor. this application, 82C37A controller used improve system performance allowing device transfer data directly from system memory. Components system clock generated 82C84A clock driver inverted meet clock high times required 82C37A controller. four gates used support 80C88 Microprocessor minimum mode producing control signals used processor access memory I/O. decoder used generate chip select controller memory. most significant bits address output address/data bus. Therefore, 82C82 octal latch used demultiplex address. Hold Acknowledge (HLDA) Address Enable (AEN) "ORed" together insure that controller does have contention with microprocessor. Operation request (DREQ) generated device. After receiving request, controller will issue Hold request (HRQ) processor. system busses released controller until Hold Acknowledge signal returned controller from 80C88 processor. After Hold Acknowledge been received, addresses control signals generated controller accomplish transfers. Data transferred directly from device memory vice versa) with MEMW MEMR IOW) being active. Note that data read into driven controller I/O-to-memory memory-to-I/O data transfers.
MEMCS HLDA 82C84A 82C85 DECODER ADDRESS HLDA M/IO MN/MX 80C88 MEMR MEMW MEMORY MEMCS MEMR MEMW DATA DEVICE ADDRESS DREQ 82C82 DATA 82C82 A0-7 DB0-7 82C37A ADSTB HLDA MEMR MEMW DREQ0 DACK
NOTE:
address lines need pull-up resistors. FIGURE APPLICATION SYSTEM
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82C37A
Figure shows application system using 82C37A controller 80C286 Microprocessor. this application, system clock comes from 82C284 clock generator PCLK signal which inverted provide proper READY setup hold times controller 80C286 system. Read Write signals from controller wired directly Read/Write control signals from 82C288 Controller. octal latch A8-A15 from controller's data local 80C286 address that memory chip selects still generated during transfers. transceiver A0A7 controlled necessary, used drive heavily loaded system address during transfers. data transceivers simply isolate controller from local microprocessor allow programming upper lower half data bus.
DECODE 80C286 A0-A23
CHIP SELECT MEMORY/ PERIPHERALS
LATCH SYSTEM MEMORY
MEMR MEMW MEMCS
TRANSCEIVER D0-D15 READY HLDA
DEVICE DREQ DACK
82C288 IORC IOWC MRDC MWTC MEMR MEMW
LATCH
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
D0-D7
82C284
PCLK READY
D0-D7 ADSTB 82C37A HLDA READY DREQ
A0-A7 MEMR MEMW DACK
MEMR MEMW
CORRESPONDING 82C288 SIGNALS MEMORY/PERIPHERALS
FIGURE 80C286 APPLICATION
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82C37A
Absolute Maximum Ratings
Supply Voltage +8.0V Input, Output Voltage -0.5V +0.5V Classification Class
Thermal Information
Thermal Resistance (Typical) (oC/W) (oC/W) CERDIP Package CLCC Package PDIP Package PLCC Package Storage Temperature Range .-65oC +150oC Maximum Junction Temperature Ceramic Package +175oC Maximum Junction Temperature Plastic Package. +150oC Maximum Lead Temperature Package (Soldering 10s) +300oC (PLCC Lead Tips Only)
Operating Conditions
Operating Voltage Range +4.5V +5.5V Operating Temperature Range C82C37A +70oC I82C37A -40oC +85oC M82C37A -55oC +125oC
Characteristics
Gate Count 2325 Gates
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Electrical Specifications
+5.0 ±10%, +70oC (C82C37A) -40oC +85oC (I82C37A) -55oC +125oC (M82C37A) UNITS -2.5mA -100µA +2.5mA output except EOP, +3.2mA only. VCC, Pins 11-13, 16-19 VOUT VCC, Pins 1-4, 21-23, 26-30, 32-40 5.5V, GND, Outputs Open 5.5V, FREQ Maximum, GND, Outputs Open TEST CONDITIONS C82C37A, I82C37A M82C37A
SYMBOL
PARAMETER Logical Input Voltage
VIHC VILC
Logical Zero Input Voltage Input Logical Voltage Input Logical Zero Voltage Output HIGH Voltage
-0.8 -0.4
Output Voltage
Input Leakage Current Output Leakage Current
ICCSB
Standby Power Supply Current Operating Power Supply Current
ICCOP
mA/MHz
Capacitance
SYMBOL COUT CI/O
+25oC PARAMETER UNITS TEST CONDITIONS FREQ 1MHz, measurements referenced device
Input Capacitance Output Capacitance Capacitance
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82C37A
Electrical Specifications
+5.0V ±10%, +70oC (C82C37A), -40oC +85oC (I82C37A), -55oC +125oC (M82C37A) 82C37A-5 SYMBOL (MASTER) MODE (1)TAEL HIGH from (S1) Delay Time from HIGH (SI) Delay Time Active Float Delay from HIGH READ WRITE Float Delay from HIGH Active Float Delay from HIGH from READ HIGH Hold Time from ADSTB Hold Time from WRITE HIGH Hold Time DACK Valid from Delay Time HIGH from HIGH Delay Time from HIGH Delay Time (10)TASM (11)TASS (12)TCH (13)TCL (14)TCY (15)TDCL Stable from HIGH ADSTB Setup Time HIGH Time (Transitions 10ns) Time (Transitions 10ns) Cycle Time HIGH READ WRITE Delay READ HIGH from HIGH (S4) Delay Time WRITE HIGH from HIGH (S4) Delay Time Valid from HIGH Delay Time Hold Time from (S2) Setup Time PARAMETER 82C37A 82C37A-12 UNITS
(2)TAET
(3)TAFAB
(4)TAFC
(5)TAFDB
(6)TAHR (7)TAHS (8)TAHW (9)TAK
TCY-100 TCL-18 TCY-65
TCY-75 TCL-18 TCY-65
TCY-65 TCL-18 TCY-50
TCH-20
TCH-20
TCH-20
(16)TDCTR
(17)TDCTW
(18)TDQ
(19)TEPH (20)TEPS
4-206
82C37A
Electrical Specifications
+5.0V ±10%, +70oC (C82C37A), -40oC +85oC (I82C37A), -55oC +125oC (M82C37A) (Continued) 82C37A-5 SYMBOL (21)TEPW (22)TFAAB (23)TFAC PARAMETER Pulse Width Valid Delay from HIGH READ WRITE Active from HIGH Valid Delay from HIGH HLDA Valid HIGH Setup Time Input Data from MEMR HIGH Hold Time Input Data MEMR HIGH Setup Time Output Data from MEMW HIGH Hold Time Output Data Valid MEMW HIGH DREQ (SI, Setup Time READY Hold Time READY Setup Time ADSTB HIGH from Delay Time ADSTB from Delay Time READ HIGH Delay from WRITE HIGH READ Pulse Width, Normal Timing ADSTB Pulse Width Extended WRITE Pulse Width WRITE Pulse Width READ Pulse Width, Compressed Valid READ Valid WRITE READ HIGH READ HIGH ADSTB HIGH WRITE HIGH ADSTB HIGH DACK Valid READ 82C37A 82C37A-12 UNITS
(24)TFADB (25)THS (26)TIDH
(27)TIDS
(28)TODH
TCY-50
(29)TODV (30)TQS
TCY-35
TCY-35
TCY-10
(31)TRH (32)TRS (33)TCLSH
(34)TCLSL
(35)TWRRD (36)TRLRH (37)TSHSL (38)TWLWHA (39)TWLWH (40)TRLRHC (56)TAVRL (57)TAVWL (58)TRHAL (59)TRHSH (60)TWHSH (61)TDVRL
2TCY-60 TCY-80 2TCY-100 TCY-100 TCY-60
2TCY-60 TCY-50 2TCY-85 TCY-85 TCY-60
2TCY-55 TCY-35 2TCY-80 TCY-80 TCY-55
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82C37A
Electrical Specifications
+5.0V ±10%, +70oC (C82C37A), -40oC +85oC (I82C37A), -55oC +125oC (M82C37A) (Continued) 82C37A-5 SYMBOL (62)TDVWL (63)TRHDI (64)TAZRL PARAMETER DACK Valid WRITE READ HIGH DACK Inactive Float READ -2.5 82C37A -2.5 82C37A-12 -2.5 UNITS
PERIPHERAL (SLAVE) MODE (41)TAR (42)TAWL (43)TCWL (44)TDW (45)TRA (46)TRDE (47)TRDF (48)TRSTD Valid READ Valid WRITE Setup Time WRITE Setup Time Data Valid WRITE HIGH Setup Time Hold from READ HIGH Data Access from READ Float Delay from READ HIGH Power Supply HIGH RESET Setup Time RESET First RESET Pulse Width READ Pulse Width from WRITE HIGH Hold Time HIGH from WRITE HIGH Hold Time Data from WRITE HIGH Hold Time WRITE Pulse Width
(49)TRSTS (50)TRSTW (51)TRW (52)TWA (53)TWC
2TCY
2TCY
2TCY
(54)TWD (55)TWWS
4-208
82C37A Timing Waveforms
TCWL (43) TAWL (42) INPUT VALID (44) INPUT VALID (54) (53) TWWS (55) (52)
NOTE:
FIGURE SLAVE MODE WRITE Successive WRITE accesses 82C37A must allow least recovery time between accesses. recovery time must allowed before executing WRITE access after READ access.
(41)
ADDRESS MUST VALID (45) (51) TRDE (46) TRDF (47) DATA VALID
-DB7
NOTE:
FIGURE SLAVE MODE READ Successive READ accesses 82C37A must allow least recovery time between accesses. recovery time must allowed before executing READ access after WRITE access.
4-209
82C37A Timing Waveforms
(30) DREQ (18) (18) (30)
(Continued)
(14) (13)
(12)
(25) HLDA TAEL TCLSH (33) ADSTB TFADB (24) DB0-DB7 A8-A15 TFAAB (22) A0-A7 DACK TFAC (23) READ TDVAL (61) TDCL (15) WRITE (FOR EXTENDED WRITE) TDVWL TWLWHA (62) (38) TDCL (15) TDCTW (17) TDCL (15) TASS (11) TAHS TAFDB ADDRESS VALID (64) TAZRL TDCTR (16) TWRRD (35) TASM (10) TAHW ADDRESS VALID TAHR TAVRL (56) TDCL (15) TRLRH (36) TAVWL (57) TAHR TRHDI (63) TCLSL (34) TSHSL (37) TEPS (20) TEPH (19) TAET
TRHAL (58)
TAFAB TAHW
TAFC TDCTR (16)
TDCTW (17) TWLWH (39)
(FOR EXTENDED WRITE) TEPW (21)
FIGURE TRANSFER
4-210
82C37A Timing Waveforms
(33) TCLSH ADSTB TFAAB (22) TASS (11) A0-A7 TFADB (24) DB0-DB7 TDCL (15) TFAC (23) MEMR TFAC (23) MEMW EXTENDED WRITE (19) TEPH TEPW (21) TEPS (20) A8-A15 (16) TDCTR TAZRL (64) TIDS (27) (34) TCLSL TAHS (59) TRHSH ADDRESS VALID TAFDB TASS (11) (33) TCLSH (34) TCLSL TWHSH (60) TAHS ADDRESS VALID TAFDB A8-A15 TODH (28) TAFC TAFC TAFAB TCLSH (33)
(Continued)
S11/SI
(24) TFADB TOVD (29) TIDH (26) TDCTW (17) TDCL (15)
TDCL (15)
FIGURE MEMORY-TO-MEMORY TRANSFER
READ (15) TDCL WRITE EXTENDED WRITE
(15) TDCL
(16) TDCTR
(15)TDCL
(17) TDCTW
READY
(31)TRH (32)TRS
(31)
(32)TRS
FIGURE READY NOTE: READY must transition during specified setup hold times.
4-211
82C37A Timing Waveforms
(Continued)
(10) TASM VALID (15) TDCL TDCTR (16) TRLRHC (40) TDCTW (17)
(10) TASM VALID TDCL (15) TDCTR (16)
A0-A7
READ
WRITE
TDCTW (17)
(31) (32) READY (32)
(31)
FIGURE COMPRESSED TRANSFER
RESET
(48) TRSTD (50) TRSTW
(49) TRSTS
FIGURE RESET
Test Circuits
Testing Input, Output Waveforms
0.4V INPUT 0.4V TEST POINT (NOTE) OUTPUT 2.0V 0.8V -0.45 0.45 OUTPUT 1.5V 1.5V OUTPUT
OUTPUT FROM DEVICE UNDER TEST
NOTE:
Includes STRAY FIXTURE Capacitance TEST CONDITION DEFINITION TABLE NOTE: PINS 1.7V 1.6k 100pF 50pF
Outputs Except
Testing: Parameters tested test circuits. Input RISE FALL times driven Ins/V. input must switch between VIHC +0.4V VILC -0.4V
4-212
82C37A Burn-In Circuits
MD82C37A CERDIP
VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
MR82C37A CLCC
VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
OPEN OPEN VCC/2 VCC/2 VCC/2 VCC/2 OPEN
OPEN
VCC/2
VCC/2
NOTES: 5.5V 0.5V 4.5V -0.2V 0.4V 1.2k 0.01µF minimum 0.1µF minimum 1N4002 100kHz ±10% F0/2, F1/2,., F14/2 outputs from 82C82 Octal Latching Driver
4-213
VCC/2
82C37A Characteristics
DIMENSIONS: ±1mils (3760- 4040 525µm) METALLIZATION: Type: SiAlCu Thickness: Metal Thickness: Metal GLASSIVATION: Type: Nitrox Thickness: WORST CASE CURRENT DENSITY: A/cm2
Metallization Mask Layout
82C37A
4-214
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