AVDD DVDD AVDD CHARGING BALANCING CONVERTER AIN1(+) AIN1(-) AIN2(+) AI
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LC2MOS Loop-Powered Signal Conditioning AD7713*
AVDD DVDD AVDD CHARGING BALANCING CONVERTER AIN1(+) AIN1(-) AIN2(+) AIN2(-) AIN3 INPUT SCALING 200µA AVDD AUTO-ZEROED MODULATOR DIGITAL FILTER SYNC IN(-) IN(+) VBIAS STANDBY
FEATURES Charge Balancing Bits Missing Codes 0.0015% Nonlinearity Three-Channel Programmable Gain Front Gains from Differential Inputs Single Ended High Voltage Input Low-Pass Filter with Programmable Filter Cutoffs Ability Read/Write Calibration Coefficients Bidirectional Microcontroller Serial Interface Single Supply Operation Power (3.5 typ) with Power-Down Mode (150 typ) APPLICATIONS Loop Powered (Smart) Transmitters Transducers Process Control Portable Industrial Instruments GENERAL DESCRIPTION
AD7713
CLOCK GENERATION SERIAL INTERFACE
MCLK MCLK
RTD1 200µA RTD2
CONTROL REGISTER
OUTPUT REGISTER
AGND
DGND
MODE SDATA SCLK DRDY
AD7713 complete analog front frequency measurement applications. device accepts level signals directly from transducer high level signals VREF) outputs serial digital word. employs sigma-delta conversion technique realize bits missing codes performance. input signal applied proprietary programmable gain front based around analog modulator. modulator output processed on-chip digital filter. first notch this digital filter programmed on-chip control register allowing adjustment filter cutoff settling time. part features differential analog inputs singleended high level analog input well differential reference input. operated from single supply (AVDD DVDD part provides current sources which used provide excitation three-wire four-wire configurations. AD7713 thus performs signal conditioning conversion single, dual three-channel system. AD7713 ideal smart, microcontroller-based systems. Gain settings, signal polarity current control configured software using bidirectional serial port. AD7713 contains self-calibration, system calibration background calibration options also allows user read write on-chip calibration registers.
*Protected U.S. Patent 5,134,401.
CMOS construction ensures power dissipation hardware programmable power-down mode reduces standby power consumption only typical. part available 24-pin, inch wide, plastic hermetic dual-in-line package (DIP) well 24-lead small outline (SOIC) package.
PRODUCT HIGHLIGHTS
AD7713 consumes less than total supply current, making ideal loop-powered systems. programmable gain channels allow AD7713 accept input signals directly from transducer removing considerable amount signal conditioning. maximize flexibility part, high level analog input accepts VREF signals. On-chip current sources provide excitation three-wire four-wire configurations. Missing Codes ensures true, usable, 24-bit dynamic range coupled with excellent 0.0015% accuracy. effects temperature drift eliminated on-chip self-calibration, which removes zero-scale full-scale errors. AD7713 ideal microcontroller processor applications with on-chip control register which allows control over filter cutoff, input gain, signal polarity calibration modes. AD7713 allows user read write on-chip calibration registers.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1995 Technology Way, P.O. 9106, Norwood. 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7713-SPECIFICATIONS(AV MCLK unless otherwise noted. specifications
DVDD IN(+) +2.5 IN(-) AGND; unless otherwise noted.)
Conditions/Comments Guaranteed Design. Filter Notches Filter Notch Filter Notch Filter Notch Filter Notch Depends Filter Cutoffs Selected Gain Filter Notches Typically 0.0003% Gains Gains Gains Gains Gains Gains Typically 0.0006% Gains Gains
Parameter STATIC PERFORMANCE Missing Codes
Versions1 Tables 0.0015 Note Note 0.25 Note 0.25 0.004 Table +VREF9 VREF AGND AVDD VREF 0.05
Units Bits Bits Bits Bits Bits µV/°C µV/°C µV/°C µV/°C µV/°C µV/°C ppm/°C µV/°C µV/°C
Output Noise Integral Nonlinearity Positive Full-Scale Error2, Full-Scale Drift5 Unipolar Offset Error2 Unipolar Offset Drift5 Bipolar Zero Error2 Bipolar Zero Drift5 Gain Drift Bipolar Negative Full-Scale Error2 Bipolar Negative Full-Scale Drift5 ANALOG INPUTS Input Sampling Rate, Normal-Mode Rejection6 Normal-Mode Rejection6 AIN1, AIN27 Input Voltage Range8
Filter Notches 0.02 fNOTCH Filter Notches ±0.02 fNOTCH Normal Operation. Depends Gain Selected. Unipolar Input Range (B/U Control Register Bipolar Input Range (B/U Control Register Filter Notches ±0.02 fNOTCH Filter Notches ±0.02 fNOTCH
Common-Mode Rejection (CMR) Common-Mode Rejection6 Common-Mode Rejection6 Common-Mode Voltage Range10 Input Leakage Current +25°C TMIN TMAX Sampling Capacitance6 AIN3 Input Voltage Range Gain Error11 Gain Drift Offset Error11 Input Impedance
ppm/°C
Normal Operation. Depends Gain Selected Additional Error Contributed Resistor Attenuator Additional Drift Contributed Resistor Attenuator Additional Error Contributed Resistor Attenuator
NOTES Temperature range follows: Version, -40°C +85°C; Version, -55°C +125°C. Applies after calibration temperature interest. Positive full-scale error applies both unipolar bipolar input ranges. These errors will order output noise part shown Table after system calibration. These errors will typical after self-calibration background calibration. Recalibration temperature background calibration mode will remove these drift errors. These numbers guaranteed design and/or characterization. AIN1 AIN2 analog inputs presents very high impedance dynamic load which varies with clock frequency input sample rate. maximum recommended source resistance depends selected gain. analog input voltage range AIN1(+) AIN2(+) inputs given here with respect voltage AIN1(-) AIN2 inputs. input voltage range AIN3 input with respect AGND. absolute voltage AIN1 AIN2 inputs should more positive than more negative than AGND VREF IN(+) IN(-). This common-mode voltage range allowed provided that input voltage AIN(+) AIN(-) does exceed AGND This error removed using system calibration capabilities AD7713. This error removed AD7713's self-calibration feature. offset drift AIN3 input four times value given Static Performance section.
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AD7713
Parameter REFERENCE INPUT IN(+) IN(-) Voltage Input Sampling Rate, Normal-Mode Rejection6 Normal-Mode Rejection6 Common-Mode Rejection (CMR) Common-Mode Rejection6 Common-Mode Rejection6 Common-Mode Voltage Range10 Input Leakage Current +25°C TMIN TMAX LOGIC INPUTS Input Current Inputs Except MCLK VINL, Input Voltage VINH, Input High Voltage MCLK Only VINL, Input Voltage VINH, Input High Voltage LOGIC OUTPUTS VOL, Output Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance12 TRANSDUCER BURN-OUT Current Initial Tolerance +25°C Drift EXCITATION CURRENTS (RTD1, RTD2) Output Current Initial Tolerance +25°C Drift Initial Matching +25°C Drift Matching Line Regulation (AVDD) Load Regulation SYSTEM CALIBRATION AIN1, AIN2 Positive Full-Scale Calibration Limit13 Negative Full-Scale Calibration Limit13 Offset Calibration Limit14, Input Span14 AIN3 Positive Full-Scale Calibration Limit13 Offset Calibration Limit15 Input Span Versions1 +2.5 AVDD/1.8 fCLK IN/512 AGND AVDD Units Conditions/Comments Specified Performance. Part Functional with Lower VREF Voltages Filter Notches Filter Notches Filter Notches Filter Notches ±0.02 NOTCH ±0.02 NOTCH ±0.02 NOTCH ±0.02 NOTCH
%/°C
ISINK ISOURCE
ppm/°C ppm/°C nA/V nA/V
Matching Between RTD1 RTD2 Currents Matching Between RTD1 RTD2 Current Drift AVDD
+(1.05 VREF)/GAIN -(1.05 VREF)/GAIN -(1.05 VREF)/GAIN +0.8 VREF/GAIN +(2.1 VREF)/GAIN +(4.2 VREF)/GAIN VREF/GAIN +3.2 VREF/GAIN +(4.2 VREF)/GAIN
GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128)
NOTES Guaranteed design, production tested. After calibration, analog input exceeds positive full scale, converter will output analog input less than negative full scale, then device will output These calibration span limits apply provided absolute voltage AIN1 AIN2 analog inputs does exceed more negative than AGND offset calibration limit applies both unipolar zero point bipolar zero point.
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AD7713-SPECIFICATIONS
Parameter POWER REQUIREMENTS Power Supply Voltages AVDD Voltage DVDD Voltage16 Power Supply Currents AVDD Current DVDD Current Power Supply Rejection17 (AVDD DVDD) Power Dissipation Normal Mode Standby (Power-Down) Mode Versions1 Units Conditions/Comments Note AVDD DVDD fCLK MHz; Typically AVDD DVDD Typically Specified Performance Specified Performance AVDD AVDD fCLK MHz. Digital Inputs DVDD fCLK MHz. Digital Inputs DVDD Rejection w.r.t. AGND
NOTES tolerance input allowed provided that does exceed AVDD more than Measured applies selected passband. PSRR will exceed with filter notches PSRR will exceed with filter notches PSRR depends gain: gain typ; gain typ; gain typ; gains typ. Specifications subject change without notice.
TIMING CHARACTERISTICS1, Input Logic Logic
Parameter fCLK IN3, tCLK tCLK Self-Clocking Mode Limit TMIN, TMAX Versions) tCLK tCLK 1000 tCLK tCLK tCLK tCLK IN/2 tCLK IN/2 tCLK IN/2 tCLK IN/2 tCLK tCLK Units
(DVDD AVDD AGND DGND fCLKIN MHz; unless otherwise noted.)
Conditions/Comments Master Clock Frequency: Crystal Oscillator Externally Supplied Specified Performance Master Clock Input Time; tCLK 1/fCLK Master Clock Input High Time Digital Output Rise Time; Typically Digital Output Fall Time; Typically SYNC Pulse Width DRDY Setup Time DRDY Hold Time Setup Time Hold Time SCLK Falling Edge Data Access Time (RFS Data Valid) SCLK Falling Edge Data Valid Delay SCLK High Pulse Width SCLK Pulse Width Setup Time Hold Time SCLK Falling Edge Delay Time SCLK Falling Edge Hold Time Data Valid SCLK Setup Time Data Valid SCLK Hold Time
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AD7713
Parameter External-Clocking Mode fSCLK t246 t256 t297 t317 Limit TMIN, TMAX Versions) fCLK IN/5 tCLK tCLK tCLK tCLK tCLK tCLK tCLK tCLK IN/2 tCLK tCLK SCLK High Units Conditions/Comments Serial Clock Input Frequency DRDY Setup Time DRDY Hold Time Setup Time Hold Time Data Access Time (RFS Data Valid) SCLK Falling Edge Data Valid Delay SCLK High Pulse Width SCLK Pulse Width SCLK Falling Edge DRDY High SCLK Data Valid Hold Time RFS/TFS SCLK Falling Edge Hold Time Data Valid Hold Time Setup Time Hold Time SCLK Falling Edge Hold Time Data Valid SCLK Setup Time Data Valid SCLK Hold Time
NOTES Guaranteed design, production tested. input signals specified with (10% timed from voltage level Figures duty cycle range 55%. must supplied whenever AD7713 STANDBY mode. clock present this case, device draw higher current than specified possibly become uncalibrated. AD7713 production tested with MHz. guaranteed characterization operate kHz. Specified using points waveform interest. These numbers measured with load circuit Figure defined time required output cross These numbers derived from measured time taken data output change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that times quoted timing characteristics true relinquish times part and, such, independent external loading capacitances.
1.6mA
OUTPUT 100pF
+2.1V
200µA
Figure Load Circuit Access Time Relinquish Time
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AD7713
ABSOLUTE MAXIMUM RATINGS*
+25°C, unless otherwise noted)
AVDD AGND -0.3 AVDD DGND -0.3 DVDD AGND -0.3 DVDD DGND -0.3 AGND DGND -0.3 AIN1, AIN2 Input Voltage AGND -0.3 AVDD AIN3 Input Voltage AGND -0.3 Reference Input Voltage AGND AVDD Digital Input Voltage DGND AVDD Digital Output Voltage DGND DVDD Operating Temperature Range Commercial Version) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature Range -65°C +150°C
Junction Temperature +150°C Plastic Package, Power Dissipation Thermal Impedance 105°C/W Lead Temperature, Soldering sec) +260°C Cerdip Package, Power Dissipation Thermal Impedance 70°C/W Lead Temperature, Soldering +300°C SOIC Package, Power Dissipation Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared secs) +220°C Power Dissipation (Any Package) +75°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 which readily accumulate human body test equipment, discharge without detection. Although devices feature proprietary protection circuitry, permanent damage still occur these devices they subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
ORDERING GUIDE
Model AD7713AN AD7713AR AD7713AQ AD7713SQ EVAL-AD7713EB
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C Evaluation Board
Package Option* N-24 R-24 Q-24 Q-24
Plastic DIP; Cerdip; SOIC.
CONFIGURATION SOIC
SCLK MCLK MCLK SYNC DGND DVDD SDATA DRDY
AD7713
MODE VIEW AIN1(+) (Not Scale) AGND AIN1(-) AIN2(+) AIN2(-) STANDBY AVDD AIN3 RTD2 IN(+) IN(-) RTD1
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AD7713
FUNCTION DESCRIPTION
Mnemonic SCLK
Function Serial Clock. Logic input/output depending status MODE pin. When MODE high, device self-clocking mode SCLK provides serial clock output. This SCLK becomes active when goes goes high impedance when either returns high when device completed transmission output word. When MODE low, device external clocking mode SCLK acts input. This input serial clock continuous clock with data transmitted continuous train pulses. Alternatively, noncontinuous clock with information being transmitted AD7713 smaller batches data. Master Clock signal device. This provided form crystal external clock. crystal tied across MCLK MCLK pins. Alternatively, MCLK driven with CMOS-compatible clock MCLK left unconnected. clock input frequency nominally MHz. When master clock device crystal, crystal connected between MCLK MCLK OUT. Address Input. With this input low, reading writing device control register. With thisinput high, access either data register calibration registers. Logic Input which allows synchronization digital filters when using number AD771 resets nodes digital filter. Logic Input. When this high, device self-clocking mode; with this low, device external clocking mode. Analog Input Channel Positive input programmable gain differential analog input. AIN1(+) input connected output current source which used check that external transducer burnt gone open circuit. This output current source turned on/off control register. Analog Input Channel Negative input programmable gain differential analog input. Analog Input Channel Positive input programmable gain differential analog input. Analog Input Channel Negative input programmable gain differential analog input. Logic Input. Taking this shuts down internal analog digital circuitry, reducing power consumption less than Analog Positive Supply Voltage, Constant Current Output. nominal constant current provided this this used excitation current RTDs. This, current turned control register. Reference Input. IN(-) anywhere between AVDD AGND provided IN(+) greater than IN(-). Reference Input. reference input differential providing that IN(+) greater than IN(-). IN(+) anywhere between AVDD AGND. Constant Current Output. nominal constant current provided this this used excitation current RTDs. This, current turned control register. This second current used eliminate lead resistanced errors three-wire configurations. Analog Input Channel High level analog input which accepts analog input voltage range VREF/GAIN. nominal VREF +2.5 gain AIN3 input voltage range Ground Reference Point Analog Circuitry. Transmit Frame Synchronization. Active logic input used write serial data device with serial data expected after falling edge this pulse. self-clocking mode, serial clock becomes active after goes low. external clocking mode, must before first data word written part. Receive Frame Synchronization. Active logic input used access serial data from device. self-clocking mode, SCLK SDATA lines both become active after goes low. external clocking mode, SDATA line becomes active after goes low.
MCLK
MCLK SYNC MODE AIN1(+)
AIN1(-) AIN2(+) AIN2(-) STANDBY AVDD RTD1 IN(-) IN(+) RTD2
AIN3
AGND
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AD7713
Mnemonic DRDY Function Logic output. falling edge indicates that output word available transmission. DRDY will return high upon completion transmission full output word. DRDY also used indicate when AD7713 completed on-chip calibration sequence. Serial Data. Input/Output with serial data being written either control register calibration registers serial data being accessed from control register, calibration registers data register. During output data read operation, serial data becomes active after goes (provided DRDY low). During write operation, valid serial data expected rising edges SCLK when low. output data coding natural binary unipolar inputs offset binary bipolar inputs. Digital Supply Voltage, DVDD should exceed AVDD more than normal operation. Ground reference point digital circuitry.
SDATA
DVDD DGND
TERMINOLOGY
INTEGRAL NONLINEARITY POSITIVE FULL-SCALE OVERRANGE
This maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero scale (not confused with bipolar zero), point below first code transition (000 001) full scale, point above last code transition (111 111). error expressed percentage full scale.
POSITIVE FULL-SCALE ERROR
Positive full-scale overrange amount overhead available handle input voltages AIN1(+) AIN2(+) inputs greater than (AIN1(-) VREF/GAIN) AIN3 greater than VREF /GAIN (for example, noise peaks excess voltages system gain errors system calibration routines) without introducing errors overloading analog modulator overflowing digital filter.
NEGATIVE FULL-SCALE OVERRANGE
Positive full-scale error deviation last code transition (111 111) from ideal input full-scale voltage. AIN1(+) AIN2(+), ideal full-scale input voltage (AIN1(-) VREF/GAIN LSBs) where AIN(-) either AIN1(-) AIN2(-) appropriate; AIN3, ideal full-scale voltage VREF/GAIN LSBs. Positive fullscale error applies both unipolar bipolar analog input ranges.
UNIPOLAR OFFSET ERROR
This amount overhead available handle voltages AIN1(+) AIN2(+) below (AIN1(-) VREF/GAIN) without overloading analog modulator overflowing digital filter.
OFFSET CALIBRATION RANGE
system calibration modes, AD7713 calibrates offset with respect analog input. offset calibration range specification defines range voltages that AD7713 accept still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGE
Unipolar offset error deviation first code transition from ideal voltage. AIN1(+) AIN2(+), ideal input voltage (AIN1(-) LSB); AIN3, ideal input when operating Unipolar Mode.
BIPOLAR ZERO ERROR
This range voltages that AD7713 accept system calibration mode still calibrate full scale correctly.
INPUT SPAN
This deviation midscale transition (0111 1000 000) from ideal input voltage. AIN1(+) AIN2(+), ideal input voltage (AIN1(-) LSB); AIN3 only accommodate unipolar input ranges.
BIPOLAR NEGATIVE FULL-SCALE ERROR
system calibration schemes, voltages applied sequence AD7713's analog input define analog input range. input span specification defines minimum maximum input voltages from zero full scale that AD7713 accept still calibrate gain accurately.
This deviation first code transition from ideal input voltage. AIN1(+) AIN2(+), ideal input voltage (AIN1(-) VREF/GAIN LSB); AIN3 only accommodate unipolar input ranges.
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AD7713
CONTROL REGISTER BITS)
write device with input writes data control register. read device with input accesses contents control register. control register bits wide when writing register bits data must written otherwise data will loaded control register. other words, possible write just first bits data into control register. more than clock pulses provided before returns high, then clock pulses after 24th clock pulse ignored. Similarly, read operation from control register should access bits data. FS11
FS10
Operating Mode
Operating Mode Normal Mode. This normal mode operation device whereby read device with high accesses data from data register. This default condition these bits after internal power-on reset. Activate Self-Calibration. This activates self-calibration channel selected CH1. This one-step calibration sequence, when complete, part returns Normal Mode (with MD2, MD1, control registers returning DRDY output indicates when this selfcalibration complete. this calibration type, zero-scale calibration done internally shorted (zeroed) inputs full-scale calibration done VREF. Activate System Calibration. This activates system calibration channel selected CH1. This two-step calibration sequence, with zero-scale calibration done first selected input channel DRDY indicating when this zero-scale calibration complete. part returns Normal Mode this first step two-step sequence. Activate System Calibration. This second step system calibration sequence with full-scale calibration being performed selected input channel. Once again, DRDY indicates when fullscale calibration complete. When this calibration complete, part returns Normal Mode. Activate System Offset Calibration. This activates system offset calibration channel selected CH1. This one-step calibration sequence and, when complete, part returns Normal Mode with DRDY indicating when this system offset calibration complete. this calibration type, zero-scale calibration done selected input channel full-scale calibration done internally VREF. Activate Background Calibration. This activates background calibration channel selected CH1. background calibration mode then AD7713 provides continuous selfcalibration reference shorted (zeroed) inputs. This calibration takes place part conversion sequence, extending conversion time reducing word rate factor six. major advantage that user does have worry about recalibrating device when there change ambient temperature. this mode, shorted (zeroed) inputs VREF, well analog input voltage, continuously monitored calibration registers device updated. Read/Write Zero-Scale Calibration Coefficients. read device with high accesses contents zero-scale calibration coefficients channel selected CH1. write device with high writes data zero-scale calibration coefficients channel selected CH1. word length reading writing these coefficients bits, regardless status control register. Therefore, when writing calibration register, bits data must written, otherwise data will transferred calibration register. Read/Write Full-Scale Calibration Coefficients. read device with high accesses contents full-scale calibration coefficients channel selected CH1. write device with high writes data full-scale calibration coefficients channel selected CH1. word length reading writing these coefficients bits, regardless status control register. Therefore, when writing calibration register, bits data must written, otherwise data will transferred calibration register.
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AD7713
Gain
Gain
(Default Condition After Internal Power-On Reset)
Channel Selection
Channel AIN1 AIN2 AIN3
(Default Condition After Internal Power-On Reset)
Word Length Output Word Length
16-Bit 24-Bit
(Default Condition After Internal Power-On Reset)
Excitation Currents
(Default Condition After Internal Power-On Reset)
Burn-Out Current
(Default Condition After Internal Power-On Reset)
Bipolar/Unipolar Selection (Both Inputs)
Bipolar Unipolar
(Default Condition After Internal Power-On Reset)
Filter Selection (FS11-FS0)
on-chip digital filter provides Sinc3 (Sinx/x)3) filter response. bits data programmed into these bits determine filter cutoff frequency, position first notch filter data rate part. association with gain selection, also determines output noise (and hence effective resolution) device. first notch filter occurs frequency determined relationship: filter first notch frequency (fCLK IN/512)/code where code decimal equivalent code bits FS11 range 2,000. With nominal fCLK MHz, this results first notch frequency range from 1.952 205.59 kHz. ensure correct operation AD7713, value code loaded these bits must within this range. Failure this will result unspecified operation device. Changing filter notch frequency, well selected gain, impacts resolution. Tables Figure show effect filter notch frequency gain effective resolution AD7713. output data rate effective conversion time) device equal frequency selected first notch filter. example, first notch filter selected then word available rate every first notch word available every settling time filter full-scale step input change worst case 1/(output data rate). This settling time 100% final value. example, with first filter notch settling time filter full-scale step input change max. first notch settling time filter full-scale input step max. This settling time reduced l/(output data rate) synchronizing step input change reset digital filter. other words, step input takes place with SYNC low, settling time will l/(output data rate). change channels takes place, settling time l/(output data rate) regardless SYNC input. frequency determined programmed first notch frequency according relationship: filter frequency 0.262 first notch frequency.
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AD7713
Tables show output noise some typical notch frequencies. numbers given bipolar input ranges with VREF +2.5 These numbers typical generated with analog input voltage output noise from part comes from sources. First, there electrical noise semiconductor devices used implementation modulator (device noise). Secondly, when analog input signal converted into digital domain, quantization noise added. device noise level largely independent frequency. quantization noise starts even lower level rises rapidly with increasing frequency become dominant noise source. Consequently, lower filter notch settings (below approximately) tend device noise dominated while higher notch settings dominated quantization noise. Changing filter notch cutoff frequency quantization noise dominated region results more dramatic improvement noise performance than does device noise dominated region shown Table Furthermore, quantization noise added after PGA, effective resolution independent gain higher filter notch frequencies. Meanwhile, device noise added and, therefore, effective resolution suffers little high gains lower notch frequencies. lower filter notch settings (below Hz), missing codes performance device 24-bit level. higher settings, more codes will missed until notch setting, missing codes performance only guaranteed 12-bit level. However, since effective resolution part 10.5 bits this filter notch setting, this missing codes performance should more than adequate applications. effective resolution device defined ratio output noise input full scale. This does remain constant with increasing gain with increasing bandwidth. Table shows same table Table except that output expressed terms effective resolution (the magnitude noise with respect VREF/GAIN, i.e., input full scale). possible post filtering device improve output data rate given frequency also further reduce output noise (see Digital Filtering section).
Table Output Noise Gain First Notch Frequency First Notch Filter Data Rate1 Frequency 0.52 1.31 1.57 2.62 3.14 5.24 13.1 26.2 52.4 Typical Output Noise (µV) Gain Gain Gain 0.48 0.63 0.84 1.33 0.33 0.57 0.64 0.87 0.29 0.25 0.44 0.46 0.54 0.63
Gain 4.33 5.28
Gain 0.78 1.31 2.06 2.36 0.26
Gain 0.25 0.41 0.43 0.46 0.62
Gain 0.25 0.38 0.46 0.65
Gain 0.25 0.38 0.46 0.56 0.65
NOTES default condition (after internal power-on reset) first notch filter these filter notch frequencies, output noise primarily dominated device noise result independent value reference voltage. Therefore, increasing reference voltage will give increase effective resolution device (i.e., ratio noise input full scale increased since output noise remains constant input full scale increases). these filter notch frequencies, output noise dominated quantization noise result proportional value reference voltage.
Table Effective Resolution Gain First Notch Frequency First Notch Filter Data Rate Frequency 0.52 1.31 1.57 2.62 3.14 5.24 13.1 26.2 52.4 Effective Resolution1 (Bits) Gain Gain Gain 21.5 20.5 18.5 15.5 19.5 19.5 18.5 15.5 20.5 19.5 19.5 15.5
Gain 22.5 21.5 18.5 10.5
Gain 21.5 18.5 10.5
Gain 19.5 18.5 18.5 18.5 17.5 15.5 12.5 10.5
Gain 18.5 17.5 17.5 17.5 12.5
Gain 17.5 16.5 16.5 16.5 14.5 12.5
NOTE Effective resolution defined magnitude output noise with respect input full scale (i.e., VREF/GAIN). above table applies VREF +2.5 resolution numbers rounded nearest LSB.
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AD7713
Figure gives similar information that outlined Table this plot, output noise shown full range available cutoff frequencies rather than some typical cutoff frequencies Tables numbers given these plots typical values 25°C.
10000 GAIN 1000 GAIN GAIN
1000
GAIN GAIN GAIN GAIN
OUTPUT NOISE
0UTPUT NOISE
GAIN
1000
10000
1000
10000
NOTCH FREQUENCY
NOTCH FREQUENCY
Figure Plot Output Noise Gain Notch Frequency (Gains
CIRCUIT DESCRIPTION
Figure Plot Output Noise Gain Notch Frequency (Gain 128)
AD7713 sigma-delta converter with on-chip digital filtering, intended measurement wide dynamic range, frequency signals such those industrial control process control applications. contains sigma-delta charge balancing) ADC, calibration microcontroller with onchip static RAM, clock oscillator, digital filter bidirectional serial communications port. part contains three analog input channels, programmable gain differential input programmable gain highlevel single-ended input. gain range both inputs from 128. AIN1 AIN2 inputs, this means that input accept unipolar signals between +2.5 bipolar signals range from when reference input voltage equals +2.5 input voltage range AIN3 input VREF/GAIN with nominal reference +2.5 gain input signal selected analog input channel continuously sampled rate determined frequency master clock, MCLK selected gain (see Table III). charge balancing converter (Sigma-Delta Modulator) converts sampled signal into digital pulse train whose duty cycle contains digital information. programmable gain function analog input also incorporated this sigma-delta modulator with input sampling frequency being modified give higher gains. sinc3 digital low-pass filter processes output sigma-delta modulator updates output register rate determined first notch frequency this filter. output data read from serial port randomly periodically rate output register update rate. first notch this digital filter (and hence frequency) programmed on-chip control register. programmable range this first notch frequency from 1.952 205.59 giving programmable range frequency 0.52 53.9 basic connection diagram part shown Figure This shows AD7713 external clocking mode with both AVDD DVDD pins AD7713 being driven
from analog supply. Some applications will have separate supplies both AVDD DVDD some these cases analog supply will exceed digital supply (see Power Supplies Grounding section).
ANALOG SUPPLY 10µF 0.1µF 0.1µF
AVDD DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT
DVDD DRDY
DVDD
AIN1(+) AIN1(-) AIN2(+) AIN2(-) AIN3
DATA READY TRANSMIT (WRITE) RECEIVE (READ) SERIAL DATA SERIAL CLOCK ADDRESS INPUT DVDD
SINGLE-ENDED ANALOG INPUT
AD7713
SDATA SCLK MODE SYNC
STANDBY ANALOG GROUND DIGITAL GROUND +2.5V REFERENCE AGND DGND
IN(+) IN(-)
MCLK MCLK
Figure Basic Connection Diagram
AD7713 provides number calibration options which programmed on-chip control register. calibration cycle initiated time writing this control register. part perform self-calibration using on-chip calibration microcontroller SRAM store calibration parameters. Other system components also included calibration loop remove offset gain errors input channel using system calibration mode. Another option background calibration mode where part continuously performs self-calibration updates calibration coefficients. Once part this mode, user does have worry about issuing periodic calibration commands device asking device recalibrate when there change ambient temperature power supply voltage. REV.
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AD7713
AD7713 gives user access on-chip calibration registers allowing microprocessor read device's calibration coefficients also write calibration coefficients part from prestored values E2PROM. This gives microprocessor much greater control over AD7713's calibration procedure. also means that user verify that device performed calibration correctly comparing coefficients after calibration with prestored values E2PROM. battery operation power systems, AD7713 offers standby mode (controlled STANDBY pin) that reduces idle power consumption typically
THEORY OPERATION
Sigma-delta ADCs generally described order analog low-pass filter. simple example first order sigmadelta shown Figure This contains only first order low-pass filter integrator. also illustrates derivation alternative name these devices: Charge Balancing ADCs
DIFFERENTIAL AMPLIFIER INTEGRATOR
COMPARATOR
general block diagram sigma-delta shown Figure contains following elements: sample-hold amplifier. differential amplifier subtracter. analog low-pass filter. 1-bit converter (comparator). 1-bit DAC. digital low-pass filter.
ANALOG LOW-PASS FILTER COMPARATOR DIGITAL FILTER
Figure Basic Charge-Balancing
consists differential amplifier (whose output difference between analog input output 1-bit DAC), integrator comparator. term charge balancing, comes from fact that this system negative feedback loop that tries keep charge integrator capacitor zero balancing charge injected input voltage with charge injected 1-bit DAC. When analog input zero, only contribution integrator output comes from 1-bit DAC. charge integrator capacitor zero, output must spend half time half time -FS. Assuming ideal components, duty cycle comparator will 50%. When positive analog input applied, output 1-bit must spend larger proportion time +FS, duty cycle comparator increases. When negative input voltage applied, duty cycle decreases. AD7713 uses second-order sigma-delta modulator digital filter that provides rolling average sampled output. After power-up there step change input voltage, there settling time that must elapse before valid data obtained.
Input Sample Rate
DIGITAL DATA
Figure General Sigma-Delta
operation, analog signal sample subtracter, along with output 1-bit DAC. filtered difference signal comparator, whose output samples difference signal frequency many times that analog signal sampling frequency (oversampling). Oversampling fundamental operation sigma-delta ADCs. Using quantization noise formula ADC: (6.02 number bits 1.76) 1-bit comparator yields 7.78 AD7713 samples input signal frequency greater (see Table III). result, quantization noise spread over much wider frequency than that band interest. noise band interest reduced still further analog filtering modulator loop, which shapes quantization noise spectrum move most noise energy frequencies outside bandwidth interest. noise performance thus improved from this 1-bit level performance outlined Tables Figure output comparator provides digital input 1-bit DAC, that system functions negative feedback loop that tries minimize difference signal. digital data that represents analog input voltage contained duty cycle pulse train appearing output comparator. retrieved parallel binary data word using digital filter.
modulator sample frequency device remains fCLK IN/512 (3.9 fCLK MHz) regardless selected gain. However, gains greater than achieved combination multiple input samples modulator cycle scaling ratio reference capacitor input capacitor. result multiple sampling, input sample rate device varies with selected gain (see Table III). effective input impedance where input sampling capacitance input sample rate.
Table III. Input Sampling Frequency Gain
Gain
Input Sampling Frequency (fS) fCLK IN/256 (7.8 fCLK MHz) fCLK IN/256 (15.6 fCLK MHz) fCLK IN/256 (31.2 fCLK MHz) fCLK IN/256 (62.4 fCLK MHz) fCLK IN/256 (62.4 fCLK MHz) fCLK IN/256 (62.4 fCLK MHz) fCLK IN/256 (62.4 fCLK MHz) fCLK IN/256 (62.4 fCLK MHz)
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AD7713
DIGITAL FILTERING Post Filtering
AD7713's digital filter behaves like similar analog filter, with minor differences. First, since digital filtering occurs after A-to-D conversion process, remove noise injected during conversion process. Analog filtering cannot this. other hand, analog filtering remove noise superimposed analog signal before reaches ADC. Digital filtering cannot this, noise peaks riding signals near full scale have potential saturate analog modulator digital filter, even though average value signal within limits. alleviate this problem, AD7713 overrange headroom built into sigma-delta modulator digital filter which allows overrange excursions above analog input range. noise signals larger than this, consideration should given analog input filtering, reducing input channel voltage that full scale half that analog input channel full scale. This will provide overrange capability greater than 100% expense reducing dynamic range (50%).
Filter Characteristics
on-chip modulator provides samples output rate. on-chip digital filter decimates these samples provide data output rate which corresponds programmed first notch frequency filter. Since output data rate exceeds Nyquist criterion, output rate given bandwidth will satisfy most application requirements. However, there some applications which require higher data rate given bandwidth noise performance. Applications that need this higher data rate will require some post filtering following digital filter AD7713. example, required bandwidth 1.57 required update rate data taken from AD7713 rate giving bandwidth 5.24 Post filtering applied this reduce bandwidth output noise, 1.57 bandwidth level, while maintaining output rate Post filtering also used reduce output noise from device bandwidths below 0.52 gain 128, output noise This essentially device noise white noise, since input chopped, noise flat frequency response. reducing bandwidth below 0.52 noise resultant passband reduced. reduction bandwidth factor results reduction output noise. This additional filtering will result longer settling time.
Antialias Considerations
cutoff frequency digital filter determined value loaded bits FS11 control register. maximum clock frequency MHz, minimum cutoff frequency filter 0.52 while maximum programmable cutoff frequency 53.9 Figure shows filter frequency response cutoff frequency 0.52 which corresponds first filter notch frequency This (sinx/x)3 response (also called sinc3)
GAIN
-100 -120 -140 -160 -180 -200 -220 -240 FREQUENCY
digital filter does provide rejection integer multiples modulator sample frequency kHz, where This means that there frequency bands, wide cutoff frequency selected FS11) where noise passes unattenuated output. However, AD7713's high oversampling ratio, these bands occupy only small fraction spectrum most broadband noise filtered. case, because high oversampling ratio simple, single pole filter generally sufficient attenuate signals these bands analog input thus provide adequate antialiasing filtering. passive components placed front AIN1 AIN2 inputs AD7713, care must taken ensure that source impedance enough introduce gain errors system. input impedance AIN1 AIN2 inputs over input appears dynamic load that varies with clock frequency with selected gain (see Figure input sample rate, shown Table III, determines time allowed analog input capacitor, CIN, charged. External impedances result longer charge time this capacitor, this result gain errors being
Figure Frequency Response AD7713 Filter
that provides >100 rejection. Programming different cutoff frequency FS0-FS11 does alter profile filter response; changes frequency notches outlined Control Register section. Since AD7713 contains this on-chip, low-pass filtering, there settling time associated with step function inputs, data output will invalid after step change until settling time elapsed. settling time depends upon notch frequency chosen filter. output data rate equates this filter notch frequency, settling time filter full-scale step input four times output data period. applications using both input channels, settling time filter must allowed elapse before data from second channel accessed.
RINT typ) CINT (11.5pF typ) VBIAS SWITCHING FREQ DEPENDS fCLK SELECTED GAIN
HIGH IMPEDANCE
Figure AIN1, AIN2 Input Impedance
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AD7713
introduced analog inputs. Both inputs differential input channels look into similar input circuitry. case, error introduced longer charging times gain error which removed using system calibration capabilities AD7713 provided that resultant span within span limits system calibration techniques AD7713. AIN3 input contains resistive attenuation network outlined Figure typical input impedance this input result, AIN3 input should driven from impedance source.
AIN3 MODULATOR CIRCUIT VBIAS
four-wire applications, these excitation currents used provide excitation current RTD; second current source left unconnected. three-wire configurations, second on-chip current source used eliminate errors voltage drops across lead resistances. Figures Application section show some configurations with AD7713. temperature coefficient current sources typically ppm/°C with typical matching between temperature coefficients both current sources ppm/°C. applications where absolute value temperature coefficient large, following schemes used remove drift error. conversion result from AD7713 ratiometric VREF voltage. Therefore, VREF voltage varies with temperature coefficient, temperature drift from current source will removed. four-wire applications, reference voltage made ratiometric current source using second current with resistor generate reference voltage part. this case 12.5 resistor used, current source generates +2.5 across resistor. This +2.5 applied IN(+) input AD7713 IN(-) input ground will supply VREF part. three-wire configurations, reference voltage part generated placing resistor (12.5 reference) series with constant current sources. current sources driven within AVDD. reference input AD7713 differential IN(+) IN(-) AD7713 driven from either side resistor. Both schemes ensure that reference voltage part tracks current sources over temperature and, thereby, removes temperature drift error.
Bipolar/Unipolar Inputs
Figure AIN3 Input Impedance
ANALOG INPUT FUNCTIONS Analog Input Ranges
analog inputs AD7713 provide user with considerable flexibility terms analog input voltage ranges. inputs differential, programmable-gain, input channels which handle either unipolar bipolar input signals. common-mode range these inputs from AGND AVDD provided that absolute value analog input voltage lies between AGND AVDD third analog input single-ended, programmable gain high-level input which accepts analog input ranges VREF/GAIN. input leakage current AIN1 AIN2 inputs maximum 25°C over temperature). This results offset voltage developed across source impedance. However, this offset effect compensated combination differential input capability part system calibration mode. input current AIN3 input depends input voltage. nominal input voltage range input current typ.
Burn Current
AIN1(+) input AD7713 contains current source which turned on/off control register. This current source used checking that transducer burnt gone open circuit before attempting take measurements that channel. current turned allowed flow into transducer measurement input voltage AIN1 input taken, indicate that transducer functioning correctly. normal operation, this burn current turned writing control register.
Excitation Currents
analog inputs AD7713 accept either unipolar bipolar input voltage ranges while third channel accepts only unipolar signals. Bipolar unipolar options AIN1 AIN2 chosen programming control register. This programs both channels either unipolar bipolar operation. Programming part either unipolar bipolar operation does change input signal conditioning; simply changes data output coding. data coding binary unipolar inputs offset binary bipolar inputs. AIN1 AIN2 input channels differential, result, voltage which unipolar bipolar signals referenced voltage AIN1(-) AIN2(-) inputs. example, AIN1(-) +1.25 AD7713 configured unipolar operation with gain VREF +2.5 input voltage range AIN1(+) input +1.25 +3.75 AIN3 input, input signals referenced AGND.
REFERENCE INPUT
AD7713 also contains matched constant current sources which provided RTD1 RTD2 pins device. These currents turned on/off control register. Writing control register enables these excitation currents.
reference inputs AD7713, IN(+) IN(-) provide differential reference input capability. common-mode range these differential inputs from AVDD. nominal differential voltage, VREF (REF IN(+) IN(-)), +2.5 specified operation, reference
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voltage with degradation performance provided that absolute value IN(+) IN(-) does exceed AVDD AGND limits. part also functional with VREF voltages down with degraded performance output noise will, terms size, larger. IN(+) must always greater than IN(-) correct operation AD7713. Both reference inputs provide high impedance, dynamic load similar analog inputs. maximum input leakage current over temperature) source resistance result gain errors part. reference inputs look like AIN1 analog input (see Figure this case, RINT CINT varies with gain. input sample rate fCLK IN/256 does vary with gain. gains CINT gain gain gain gain 1.25 digital filter AD7713 removes noise from reference input just does with analog input, same limitations apply regarding lack noise rejection integer multiples sampling frequency. output noise performance outlined Tables assumes clean reference. reference noise bandwidth interest excessive, degrade performance AD7713. recommended reference source AD7713 AD680, reference.
USING AD7713 SYSTEM DESIGN CONSIDERATIONS System Synchronization
multiple AD7713s operated from common master clock, they synchronized update their output registers simultaneously. falling edge SYNC input resets filter places AD7713 into consistent, known state. common signal AD7713s' SYNC inputs will synchronize their operation. This would normally done after each AD7713 performed calibration calibration coefficients loaded SYNC input also used reset digital filter systems where turn-on time digital power supply (DVDD) very long. such cases, AD7713 will start operating internally before DVDD line reached minimum operating level, +4.75 With DVDD voltage, AD7713's internal digital filter logic does operate correctly. Thus, AD7713 have clocked itself into incorrect operating condition time that DVDD reached correct level. digital filter will reset upon issue calibration command (whether self-calibration, system calibration background calibration) AD7713. This ensures correct operation AD7713. systems where power-on default conditions AD7713 acceptable, calibration performed after power-on, issuing SYNC pulse AD7713 will reset AD7713's digital filter logic. SYNC line, with time constant longer than DVDD power-on time, will perform SYNC function.
ACCURACY
AD7713 operates differently from successive approximation ADCs integrating ADCs. Since samples signal continuously, like tracking ADC, there need start convert command. output register updated rate determined first notch filter output read time, either synchronously asynchronously.
Clocking
AD7713 requires master clock input, which external TTL/CMOS compatible clock signal applied MCLK with MCLK left unconnected. Alternatively, crystal correct frequency connected between MCLK MCLK OUT, which case clock circuit will function crystal controlled oscillator. lower clock frequencies, ceramic resonator used instead crystal. these lower frequency oscillators, external capacitors required either ceramic resonator crystal. input sampling frequency, modulator sampling frequency, frequency, output update rate calibration time directly related master clock frequency, fCLK Reducing master clock frequency factor will halve above frequencies update rate will double calibration time. current drawn from DVDD power supply also directly related fCLK Reducing fCLK factor will halve DVDD current will affect current drawn from AVDD power supply.
Sigma-delta ADCs, like VFCs other integrating ADCs, contain source nonmonotonicity inherently offer missing codes performance. AD7713 achieves excellent linearity high quality, on-chip silicon dioxide capacitors, which have very capacitance/voltage coefficient. device also achieves input drift through chopper stabilized techniques input stage. ensure excellent performance over time temperature, AD7713 uses digital calibration techniques that minimize offset gain error.
AUTOCALIBRATION
Autocalibration AD7713 removes offset gain errors from device. calibration routine should initiated device whenever there change ambient operating temperature supply voltage. should also initiated there change selected gain, filter notch bipolar/unipolar input range. However, AD7713 background calibration mode, above changes automatically taken care (after settling time filter been allowed for). AD7713 offers self-calibration, system calibration background calibration facilities. calibration occur selected channel, on-chip microcontroller must record modulator output different input conditions. These "zero-scale" "full-scale" points. With these readings, microcontroller calculate gain slope input output transfer function converter. Internally, part works with resolution bits determine conversion result either bits bits.
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AD7713
AD7713 also provides facility write on-chip calibration registers, this manner span offset part adjusted user. offset calibration register contains value which subtracted from conversion results, while full-scale calibration register contains value which multiplied conversion results. offset calibration coefficient subtracted from result prior multiplication full-scale coefficient. first three modes outlined here, DRDY line indicates that calibration complete going low. DRDY before goes during) calibration command, take modulator cycle before DRDY goes high indicate that calibration progress. Therefore, DRDY line should ignored modulator cycle after last calibration command written control register.
Self-Calibration
system calibration performed between endpoints transfer function; bipolar mode, performed between midscale positive full scale. This two-step system calibration mode offers another feature. After sequence been completed, additional offset gain calibrations performed themselves adjust zero reference point system gain. This achieved performing first step system calibration sequence writing MD2, MD1, MD0). This will adjust zero-scale offset point will change slope factor from what during full system calibration sequence. System calibration also used remove errors from antialiasing filter analog input. simple antialiasing filter front introduce gain error analog input voltage system calibration used remove this error.
System Offset Calibration
self-calibration mode with unipolar input range, zero-scale point used determining calibration coefficients with both inputs shorted (i.e., AIN1(+) AIN1(-) VBIAS AIN1 AIN2 AIN3 VBIAS AIN3 full-scale point VREF. zero-scale coefficient determined converting internal shorted inputs node. full-scale coefficient determined from span between this shorted inputs conversion conversion internal VREF node. self-calibration mode invoked writing appropriate values MD2, bits control register. this calibration mode, shorted inputs node switched modulator first conversion performed; VREF node then switched another conversion performed. When calibration sequence complete, calibration coefficients updated filter resettled analog input voltage, DRDY output goes low. self-calibration procedure takes into account selected gain PGA. bipolar input ranges self-calibrating mode, sequence very similar that just outlined. this case, points that AD7713 calibrates midscale (bipolar zero) positive full scale.
System Calibration
System offset calibration variation both system calibration self-calibration. this case, zero-scale point system presented input converter. System offset calibration initiated writing MD2, MD1, MD0. system zero-scale coefficient determined converting voltage applied input, while fullscale coefficient determined from span between this conversion conversion VREF. zero-scale point should applied input duration calibration sequence. This one-step calibration sequence with DRDY going when sequence completed. unipolar mode, system offset calibration performed between endpoints transfer function; bipolar mode, performed between midscale positive full scale.
Background Calibration
System calibration allows AD7713 compensate system gain offset errors well internal errors. System calibration performs same slope factor calculations selfcalibration uses voltage values presented system inputs zero full-scale points. System calibration two-step process. zero-scale point must presented converter first. must applied converter before calibration step initiated remain stable until step complete. System calibration initiated writing appropriate values MD2, bits control register. DRDY output from device will signal when step complete going low. After zero-scale point calibrated, full-scale point applied second step calibration process initiated again writing appropriate values MD2, MD0. Again full-scale voltage must before calibration initiated, must remain stable throughout calibration step. DRDY goes this second step indicate that system calibration complete. unipolar mode,
AD7713 also offers background calibration mode where part interleaves calibration procedure with normal conversion sequence. background calibration mode, same voltages used calibration points used self-calibration mode, i.e., shorted inputs VREF. background calibration mode invoked writing MD2, MD1, control register. When invoked, background calibration mode reduces output data rate AD7713 factor while bandwidth remains unchanged. advantage that part continually performing calibration automatically updating calibration coefficients. result, effects temperature drift, supply sensitivity time drift zero- full-scale errors automatically removed. When background calibration mode turned part will remain this mode until bits MD2, control register changed. With background calibration mode first result from AD7713 will incorrect full-scale calibration will have been performed. step change input, second output update will have settled 100% final value. Table summarizes calibration modes calibration points associated with them. also gives duration from when calibration invoked when valid data available user.
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Table Calibration Truth Table
Type Self-Cal System System System Offset Background
MD2, MD1,
Zero-Scale Shorted Inputs Shorted Inputs
Full-Scale VREF VREF VREF
Sequence Step Step Step Step Step
Duration 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate
Span Offset Limits
Whenever system calibration mode used, there limits amount offset span that accommodated. range input span both unipolar bipolar modes AIN1 AIN2 minimum value VREF/GAIN maximum value VREF/GAIN. AIN3, minimum value VREF/GAIN while maximum value VREF/GAIN. amount offset which accommodated depends whether unipolar bipolar mode being used. This offset range limited requirement that positive full-scale calibration limit 1.05 VREF/GAIN AIN1 AIN2. Therefore, offset range plus span range cannot exceed 1.05 VREF/GAIN AIN1 AIN2. span minimum (0.8 VREF/GAIN) maximum offset (0.25 VREF/GAIN) AIN1 AIN2. AIN3, both ranges multiplied factor four. bipolar mode, system offset calibration range again restricted span range. span range converter bipolar mode equidistant around voltage used zero-scale point, thus offset range plus half span range cannot exceed (1.05 VREF/GAIN) AIN1 AIN2. span VREF/GAIN, offset span cannot move more than (0.05 VREF/GAIN) before endpoints transfer function exceed input overrange limits (1.05 VREF/GAIN) AIN1. span range minimum (0.4 VREF/GAIN), maximum allowable offset range (0.65 VREF/GAIN) AIN1 AIN2. AIN3 input only used unipolar mode.
POWER-UP CALIBRATION
rent essentially independent selected gain. Gain drift within converter depends primarily upon temperature tracking internal capacitors. affected leakage currents. Measurement errors offset drift gain drift eliminated time recalibrating converter operating part background calibration mode. Using system calibration mode also minimize offset gain errors signal conditioning circuitry. Integral differential linearity errors significantly affected temperature changes.
POWER SUPPLIES GROUNDING
analog digital supplies AD7713 independent separately pinned minimize coupling between analog digital sections device. digital filter will provide rejection broadband noise power supplies, except integer multiples modulator sampling frequency. digital supply (DVDD) must exceed analog positive supply (AVDD) more than separate analog digital supplies used, recommended decoupling scheme shown Figure systems where AVDD DVDD recommended that AVDD DVDD driven from same supply, although each supply should decoupled separately shown Figure preferable that common supply system's analog supply. also important that power applied AD7713 before signals logic input pins order avoid excessive current. separate supplies used AD7713 system digital circuitry, then AD7713 should powered first. possible guarantee this, then current limiting resistors should placed series with logic inputs.
ANALOG SUPPLY 10µF 0.1µF AVDD DVDD DIGITAL SUPPLY 0.1µF
power-up, AD7713 performs internal reset which sets contents control register known state. However, ensure correct calibration device calibration routine should performed after power-up. power dissipation temperature drift AD7713 warm-up time required before initial calibration performed. However, external reference must have stabilized before calibration initiated.
Drift Considerations
AD7713
AD7713 uses chopper stabilization techniques minimize input offset drift. Charge injection analog switches leakage currents sampling node primary sources offset voltage drift converter. input leakage cur-
Figure Recommended Decoupling Scheme
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AD7713
DIGITAL INTERFACE
AD7713's serial communications port provides flexible arrangement allow easy interfacing industry-standard microprocessors, microcontrollers digital signal processors. serial read AD7713 access data from output register, control register from calibration registers. serial write AD7713 write data control register calibration registers. different modes operation available, optimized different types interface where AD7713 either master system provides serial clock) slave external serial clock provided AD7713). These modes, labelled self-clocking mode external clocking mode, discussed detail following sections.
Self-Clocking Mode
output data register. reset high when last data (either 16th 24th bit) read from output register. data read from output register, DRDY line will remain low. output register will continue updated output update rate DRDY will indicate this. read from device this circumstance will access most recent word output register. data word becomes available output register while data being read from output register, DRDY will indicate this data word will lost user. DRDY affected reading from control register calibration registers. Data only accessed from output data register when DRDY low. goes with DRDY high, data transfer will take place. DRDY does have effect reading data from control register from calibration registers. Figure shows timing diagram reading from AD7713 self-clocking mode. This read operation shows read from AD7713's output data register. read from control register calibration registers similar, these cases DRDY line related read function. Depending output update rate, stage control/calibration register read cycle without affecting read status should ignored. read operation from either control calibration registers must always read bits data from respective register. Figure shows read operation from AD7713. timing diagram shown, assumed that there pull-up resistor SCLK output. With DRDY low, input brought low. going enables serial clock AD7713 also places word serial data line. subsequent data bits clocked high transition serial clock valid prior following rising edge this clock. final active falling edge SCLK clocks LSB, this valid prior final active rising edge SCLK. Coincident with next falling edge SCLK, DRDY reset high. DRDY going high turns SCLK SDATA outputs. This means that data hold time slightly shorter than other bits.
AD7713 configured self-clocking mode tying MODE high. this mode, AD7713 provides serial clock signal used transfer data from AD7713. This self-clocking mode used with processors that allow external device clock their serial port including most digital signal processors microcontrollers such 68HC11 68HC05. also allows easy interfacing serial parallel conversion circuits systems with parallel data communication, allowing interfacing 74XX299 Universal Shift registers without additional decoding. case shift registers, serial clock line should have pull-down resistor instead pull-up resistor shown Figure Figure
Read Operation
Data read from either output register, control register calibration registers. determines whether data read accesses data from control register from output/calibration registers. This signal must remain valid duration serial read operation. With high, data accessed from either output register from calibration registers. With low, data accessed from control register. function DRDY line dependent only output update rate device reading output data register. DRDY goes when data word available
DRDY
SCLK
SDATA
3-STATE
Figure Self-Clocking Mode, Output Data Read Operation
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SCLK
SDATA
Figure Self-Clocking Mode, Control/Calibration Register Write Operation
Write Operation
Data written either control register calibration registers. either case, write operation affected DRDY line write operation does have effect status DRDY. write operation control register calibration register must always write bits respective register. Figure shows write operation AD7713. determines whether write operation transfers data control register calibration registers. This signal must remain valid duration serial write operation. falling edge enables internally generated SCLK output. serial data loaded AD7713 must valid rising edge this SCLK signal. Data clocked into AD7713 rising edge SCLK signal with transferred first. last active high time SCLK, loaded AD7713. Subsequent next falling edge SCLK, SCLK output turned off. (The timing diagram Figure assumes pull-up resistor SCLK line.)
External Clocking Mode
able output register while data being read from output register, DRDY will indicate this data word will lost user. DRDY affected reading from control register calibration register. Data only accessed from output data register when DRDY low. goes while DRDY high, data transfer will take place. DRDY does have effect reading data from control register from calibration registers. Figures show timing diagrams reading from AD7713 external clocking mode. Figure shows situation where data read from AD7713 read operation. Figure shows situation where data read from AD7713 over number read operations. Both read operations show read from AD7713's output data register. read from control register calibration registers similar, these cases DRDY line related read function. Depending output update rate, stage control/calibration register read cycle without affecting read status should ignored. read operation from either control calibration registers must always read bits data from respective register. Figure shows read operation from AD7713 where remains duration data word transmission. With DRDY low, input brought low. input SCLK signal should between read write operations. going places word read serial data line. subsequent data bits clocked high transition serial clock valid prior following rising edge this clock. penultimate falling edge SCLK clocks final falling edge resets DRDY line high. This rising edge DRDY turns serial data output. Figure shows timing diagram read operation where returns high during transmission word returns again access rest data word. Timing parameters functions very similar that outlined Figure 12a, Figure number additional times show timing relationships when returns high middle transferring word. should return high during time SCLK. rising edge RFS, SDATA output turned off. DRDY remains will remain until bits data word read from AD7713, regardless number times changes state during read operation. Depending time between falling edge SCLK rising edge
AD7713 configured external clocking mode tying MODE low. this mode, SCLK AD7713 configured input, external serial clock must provided this SCLK pin. This external clocking mode designed direct interface systems which provide serial clock output which synchronized serial data output, including microcontrollers such 80C51, 87C51, 68HC11 68HC05 most digital signal processors.
Read Operation
with self-clocking mode, data read from either output register, control register calibration registers. determines whether data read accesses data from control register from output/calibration registers. This signal must remain valid duration serial read operation. With high, data accessed from either output register from calibration registers. With low, data accessed from control register. function DRDY line dependent only output update rate device reading output data register. DRDY goes when data word available output data register. reset high when last data (either 16th 24th bit) read from output register. data read from output register, DRDY line will remain low. output register will continue updated output update rate, DRDY will indicate this. read from device this circumstance will access most recent word output register. data word becomes avail-
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DRDY
SCLK
SDATA
3-STATE
Figure 12a. External Clocking Mode, Output Data Read Operation
DRDY
SCLK
SDATA
3-STATE
Figure 12b. External Clocking Mode, Output Data Read Operation (RFS Returns High During Read Operation)
RFS, next (BIT appear databus before goes high. When returns again, activates SDATA output. When entire word transmitted, DRDY line will high, turning SDATA output Figure 12a.
Write Operation
Data written either control register calibration registers. either case, write operation affected DRDY line, write operation does have effect status DRDY. write operation control register calibration register must always write bits respective register. Figure shows write operation AD7713 with remaining duration write operation. determines whether write operation transfers data control
register calibration registers. This signal must remain valid duration serial write operation. before, serial clock line should between read write operations. serial data loaded AD7713 must valid high level externally applied SCLK signal. Data clocked into AD7713 high level this SCLK signal with transferred first. last active high time SCLK, loaded AD7713. Figure shows timing diagram write operation AD7713 with returning high during write operation returning again write rest data word. Timing parameters functions very similar that outlined Figure 13a, Figure number additional times show timing relationships when returns high middle transferring word.
SCLK
SDATA
Figure 13a. External Clocking Mode, Control/Calibration Register Write Operation
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AD7713
SCLK
SDATA
Figure 13b. External Clocking Mode, Control/Calibration Register Write Operation (TFS Returns High During Write Operation)
Data loaded AD7713 must valid prior rising edge SCLK signal. should return high during time SCLK. After returns again, next data word loaded AD7713 clocked next high level SCLK input. last active high time SCLK input, loaded AD7713.
SIMPLIFYING EXTERNAL CLOCKING MODE INTERFACE
flowchart Figure continuous read operations from AD7713 output register. example shown, DRDY line continuously polled. Depending microprocessor configuration, DRDY line come interrupt input which case DRDY will automatically generate interrupt without being polled. reading serial buffer could anything from read operation three read
START
many applications, user require facility writing on-chip calibration registers. this case, serial interface AD7713 external clocking modecan simplified connecting line input AD7713 (see Figure 14). This means that write device will load data control register (since while low) read device will access data from output data register from calibration registers (since high while low). should noted that this arrangement user does have capability reading from control register.
SDATA SCLK
CONFIGURE INITIALIZE µC/µP SERIAL PORT
BRING RFS, HIGH
POLL DRDY
FOUR INTERFACE LINES
DRDY LOW?
AD7713
BRING
Figure Simplified Interface with Connected
READ SERIAL BUFFER
Another method simplifying interface generate signal from inverted signal. However, generating signals opposite around (RFS from inverted TFS) will cause writing errors.
MICROCOMPUTER/MICROPROCESSOR INTERFACING
BRING HIGH
AD7713's flexible serial interface allows easy interface most microcomputers microprocessors. Figure shows flowchart diagram typical programming sequence reading data from AD7713 microcomputer while Figure shows flowchart diagram writing data AD7713. Figures show some typical interface circuits.
REVERSE ORDER BITS
Figure Flowchart Continuous Read Operations AD7713
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operations (where bits data read into 8-bit serial register). read operation control/calibration registers similar, this case status DRDY ignored. line brought when line brought when reading from control register. flowchart also shows bits being reversed after they have been read from serial port. This depends whether microprocessor expects word first word first. AD7713 outputs first. flowchart Figure single 24-bit write operation AD7713 control calibration registers. This shows data being transferred from data memory accumulator before being written serial buffer. Some microprocessor systems will allow data written directly serial buffer from data memory. writing data serial buffer from accumulator will generally consist either three write operations, depending size serial buffer. flowchart also shows option bits being reversed before being written serial buffer. This depends whether first transmitted microprocessor LSB. AD7713 expects first data stream. cases where data being read being written bytes data reversed, bits will have reversed every byte.
START
AD7713 8051 Interface
Figure shows interface between AD7713 8XC51 microcontroller. AD7713 configured external clocking mode while 8XC51 configured Mode serial interface mode. DRDY line from AD7713 connected Port P1.2 input 8XC51 DRDY line polled 8XC51. DRDY line connected INT1 input 8XC51 interrupt driven system preferred.
DVDD SYNC P1.0 P1.1 DRDY SDATA SCLK MODE
8XC51
P1.2 P1.3 P3.0 P3.1
AD7713
Figure AD7713 8XC51 Interface
CONFIGURE INITIALIZE µC/µP SERIAL PORT
BRING RFS, HIGH
Table shows some typical 8XC51 code used single 24-bit read from output register AD7713. Table shows some typical code single write operation control register AD7713. 8XC51 outputs first write operation while AD7713 expects first, data transmitted rearranged before being written output serial register. Similarly, AD7713 outputs first during read operation while 8XC51 expects first. Therefore, data which read into serial buffer needs rearranged before correct data word from AD7713 available accumulator.
Table 8XC51 Code Reading from AD7713 SCON,#00010001B; IE,#00010000B; SETB 90H; SETB 91H; SETB 93H; R1,#003H; R0,#030H; Configure 8051 MODE Disable Interrupts P1.0, Used P1.1, Used P1.3, Used Sets Number Bytes Read Read Operation Start Address Where Bytes Will Loaded P1.2 DRDY
LOAD DATA FROM ADDRESS ACCUMULATOR
REVERSE ORDER BITS
BRING
WRITE DATA FROM ACCUMULATOR SERIAL BUFFER
BRING HIGH
Figure Flowchart Single Write Operation AD7713
R6,#004H; WAIT: NOP; A,P1; A,R6; READ; SJMP WAIT; READ: 90H; 98H; POLL: 98H, READ1 SJMP POLL
Read Port Mask Bits Except DRDY Zero Read Otherwise Keep Polling Bring Clear Receive Flag Tests Receive Interrupt Flag continued next page
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AD7713
READ A,SBUF; Read Buffer Rearrange
B.0,C; Reverse Order Bits B.1,C; B.2,C; B.3,C; B.4,C; B.5,C; B.6,C; B.7,C; A,B; @R0,A; Write Data Memory Increment Memory Location Decrement Byte Counter A,R1 Jump Zero WAIT Fetch Next Byte END: SETB Bring High FIN: SJMP
Table 8XC51 Code Writing AD7713 SCON,#00000000B; IE,#10010000B; IP,#00010000B; SETB 91H; SETB 90H; R1,#003H; R0,#030H; A,#00H; SBUF,A; WAIT: WAIT; ROUTINE: NOP; A,R1; FIN; A,@R; Configure 8051 MODE Operation Enable Serial Reception Enable Transmit Interrupt Prioritize Transmit Interrupt Bring High Bring High Sets Number Bytes Written Write Operation Start Address Bytes Clear Accumulator Initialize Serial Port Wait Interrupt
which single chip mode. DRDY line from AD7713 connected Port input 68HC11 DRDY line polled 68HC11. DRDY line connected input 68HC11 interrupt driven system preferred. 68HC11 MOSI MISO lines should configured wired-or operation. Depending interface configuration, necessary provide bidirectional buffers between 68HC11's MOSI MISO lines. 68HC11 configured master mode with CPOL logic zero CPHA logic one.
DVDD DVDD SYNC DRDY SCLK SDATA MODE
68HC11
MISO MOSI
AD7713
Figure AD7713 68HC11 Interface
AD7713 ADSP-2105 Interface
Interrupt Subroutine Load Accumulator Zero Jump Decrement Byte Counter Move Byte into Accumulator Increment Address Rearrange Data-From First First B.0,C; B.1,C; B.2,C; B.3,C; B.4,C; B.5,C; B.6,C; B.7,C; A,B; 93H; Bring 91H; Bring SBUF,A; Write Serial Port RETI; Return from Subroutine FIN: SETB 91H; High SETB 93H; High RETI; Return from Interrupt Subroutine AD7713 68HC11 Interface
interface circuit between AD7713 ADSP-2105 microprocessor shown Figure this interface, AD7713 configured self-clocking mode while pins ADSP-2105 configured inputs ADSP-2105 serial clock line also configured input. When ADSP-2105's serial clock configured input needs couple clock pulses initialize itself correctly before accepting data. Therefore, first read from AD7713 read correct data. interface shown, read operation AD7713 accesses either output register calibration registers. Data cannot read from control register. write operation always writes control calibration registers. DRDY used frame synchronization pulse read operations from output register decoded with drive inputs both AD7713 ADSP-2105. latched line drives inputs both AD7713 ADSP-2105 well AD7713 input.
DVDD MODE DRDY
ADSP-2105
DMWR
AD7713
SDATA 74HC74
Figure shows interface between AD7713 68HC11 microcontroller. AD7713 configured external clocking mode while port used 68HC11
SCLK SCLK
Figure AD7713 ADSP-2105 Interface
-24-
REV.
AD7713
APPLICATIONS Four-Wire Configurations
Figure shows four-wire application where transducer interfaced directly AD7713. four-wire configuration, there errors associated with lead resistances current flows measurement leads connected AIN1(+) AIN1(-). current sources used provide excitation current RTD. common nominal resistance value and, therefore, will generate signal which handled directly analog input AD7713. circuit shown, second excitation current used generate reference voltage AD7713. This reference voltage developed across RREF applied differential reference inputs. nominal reference voltage +2.5 RREF 12.5 This scheme ensures that analog input voltage span remains ratiometric reference voltage. errors analog input voltage temperature drift current source compensated variation reference voltage. typical matching between current sources less than ppm/°C.
AVDD 200µA RTD2 IN(+) RREF INTERNAL CIRCUITRY DVDD
voltage developed across since this common-mode voltage will introduce errors. reference voltage derived from current sources. This gives benefits eliminating tempco errors outlined Figure voltage either input within AVDD supply. circuit shown +2.5 reference.
AVDD DVDD 200µA RTD1 12.5k AIN(-) RTD2 200µA AIN(+) INTERNAL CIRCUITRY
IN(-)
IN(+)
AD7713
AGND
DGND
Figure Three-Wire Application with AD7713
4-20 Loop
IN(-)
200µA RTD1
AD7713's high level input used measure current 4-20 loop applications shown Figure this case, system calibration capabilities AD7713 used remove offset caused flowing through resistor. AD7713 handle input span VREF with VREF +2.5 even though nominal input voltage range input Therefore, full span converter used measuring current between
ANALOG SUPPLY AVDD DVDD IN(-) IN(+)
AD7713
AIN1(+) AIN1(-) AGND
AVDD INTERNAL CIRCUITRY
DGND
AIN1(+) AIN1(-)
VOLTAGE ATTENUATION
Figure Four-Wire Application with AD7713
Three-Wire Configurations
AIN3 4-20mA LOOP
AD7713
DGND
Figure shows three-wire configuration using AD7713. three-wire configuration, lead resistances will result errors only current source used will flow through developing voltage error between AIN1(+) AIN1(-). scheme outlined below, second current source used compensate error introduced flowing through RL1. second current flows through RL2. Assuming equal (the leads would normally same material equal length) RTD1 RTD2 match, then error voltage across equals error voltage across error voltage developed between AIN1(+) AIN1(-). Twice
AGND
Figure 4-20 Measurement Using AD7713
REV.
-25-
AD7713
OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE FROM ANALOG DEVICES
AD7710
FEATURES Charge Balancing Bits Missing Codes 0.0015% Nonlinearity Two-Channel Programmable Gain Front Gains from Differential Inputs Low-Pass Filter with Programmable Filter Cutoffs Ability Read/Write Calibration Coefficients Bidirectional Microcontroller Serial Interface Internal/External Reference Option Single Dual Supply Operation Power typ) with Power-Down Mode typ} APPLICATIONS Weigh Scales Thermocouples Process Control Smart Transmitters Chromatography AVDD DVDD AVDD 2.5V REFERENCE 4.5µA CHARGING BALANCING CONVERTER AIN1(+) AIN1(-) AIN2(+) AIN2(-) AVDD 20µA CURRENT CLOCK GENERATION SERIAL INTERFACE CONTROL REGISTER OUTPUT REGISTER AUTO-ZEROED MODULATOR DIGITAL FILTER SYNC IN(-) IN(+) VBIAS
MCLK MCLK
AD7710
AGND DGND MODE SDATA SCLK DRDY
AD7711
FEATURES Charge Balancing Bits Missing Codes 0.0015% Nonlinearity Two-Channel Programmable Gain Front Gains from Differential Input Single-Ended Input Low-Pass Filter with Programmable Filter Cutoffs Ability Read/Write Calibration Coefficients Excitation Current Sources Bidirectional Microcontroller Serial Interface Internal/External Reference Option Single Dual Supply Operation Power typ) with Power-Down Mode typ) APPLICATIONS Transducers Process Control Smart Transmitters Portable Industrial Instruments
AVDD DVDD AVDD 2.5V REFERENCE 4.5µA CHARGING BALANCING CONVERTER AIN1(+) AIN1(-) AIN2 200µA RTD1 200µA RTD2 SERIAL INTERFACE CONTROL REGISTER OUTPUT REGISTER AVDD CLOCK GENERATION AUTO-ZEROED MODULATOR DIGITAL FILTER SYNC IN(-) IN(+) VBIAS
MCLK MCLK
AD7711
AGND DGND MODE SDATA SCLK DRDY
-26-
REV.
AD7713
AD7712
FEATURES Charge Balancing Bits Missing Codes 0.0015% Nonlinearity High Level Level Analog Input Channels Programmable Gain Both Inputs Gains from Differential Input Level Channel Low-Pass Filter with Programmable Filter Cutoffs Ability Read/Write Calibration Coefficients Bidirectional Microcontroller Serial Interface Internal/External Reference Option Single Dual Supply Operation Power typ) with Power-Down Mode (100 typ} APPLICATIONS Process Control Smart Transmitters Portable Industrial Instruments AVDD DVDD AVDD 2.5V REFERENCE 4.5µA AIN1(+) AIN1(-) AIN2 VOLTAGE ATTENUATION CLOCK GENERATION SERIAL INTERFACE CONTROL REGISTER OUTPUT REGISTER CHARGING BALANCING CONVERTER SYNC AUTO-ZEROED MODULATOR DIGITAL FILTER STANDBY IN(-) IN(+) VBIAS
MCLK MCLK
AD7712
AGND DGND MODE SDATA SCLK DRDY
REV.
-27-
AD7713
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Plastic (N-24)
0.280 (7.11) 0.240 (6.10)
1.275 (32.30) 1.125 (28.60) 0.060 (1.52) 0.015 (0.38)
0.325 (8.25) 0.300 (7.62)
0.210 (5.33) SEATING PLANE 0.200 (5.05) 0.125 (3.18)
0.195 (4.95) 0.115 (2.93)
0.015 (0.381) 0.008 (0.204) 0.150 (3.81)
0.022 (0.558) 0.014 (0.356)
0.100 (2.54)
0.070 (1.77) 0.045 (1.15)
Cerdip (Q-24)
0.005 (0.13) 0.098 (2.49)
0.320 (8.13) 0.290 (7.37) 0.310 (7.87) 0.220 (5.59 0.060 (1.52) 0.015 (0.38)
1.280 (32.51) 0.200 (5.08)
0.200 (5.08) 0.125 (3.18)
0.150 (3.81) 0.015 (0.38) 0.008 (0.20)
0.023 (0.58) 0.014 (0.36)
0.110 (2.79) 0.090 (2.29)
0.070 (1.78) 0.030 (0.76)
SEATING PLANE
SOIC (R-24)
15.6 (0.614) 15.2 (0.598)
0.419 (10.65) 0.394 (10.00)
0.050 (1.27)
0.019 (0.49) 0.014 (0.35) 0.104 (2.65) 0.093 (2.35) 0.013 (0.32) 0.009 (0.23) 0.050 (1.27) 0.016 (0.40)
0.012 (0.3) 0.004 (0.1)
-28-
REV.
PRINTED U.S.A.
0.299 (7.6) 0.291 (7.4)
C1657b-5-7/95
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