FEATURES Monolithic 16-Bit 0.0015% Linearity Error On-Chip Self-Calibr
|
|
|
Top Searches for this datasheet
LC2MOS 20-Bit Converter AD7703
FEATURES Monolithic 16-Bit 0.0015% Linearity Error On-Chip Self-Calibration Circuitry Programmable Low-Pass Filter Corner Frequency +2.5 Analog Input Range kSPS Output Data Rate Flexible Serial Interface Ultralow Power APPLICATIONS Industrial Process Control Weigh Scales Portable Instrumentation Remote Data Acquisition FUNCTIONAL BLOCK DIAGRAM
AVSS DVSS
AD7703
DVDD AVDD CALIBRATION SRAM CALIBRATION MICROCONTROLLER
20-BIT CHARGE BALANCE CONVERTER ANALOG MODULATOR 6-POLE GAUSSIAN LOW-PASS DIGITAL FILTER
BP/UP
VREF
SLEEP
AGND
CLOCK GENERATOR SERIAL INTERFACE LOGIC SDATA SCLK
DGND
CLKIN
CLKOUT
MODE
DRDY
AD7703 20-bit that uses conversion technique. analog input continuously sampled analog modulator whose mean output duty cycle proportional input signal. modulator output processed on-chip digital filter with six-pole Gaussian response, which updates output data register with 16-bit binary words word rates kHz. sampling rate, filter corner frequency, output word rate master clock input that supplied externally, crystal controlled on-chip clock oscillator. inherent linearity excellent endpoint accuracy ensured self-calibration zero full scale, which initiated time. self-calibration scheme also extended null system offset gain errors input channel. output data accessed through flexible serial port, which asynchronous mode compatible with UARTs synchronous modes suitable interfacing shift registers serial ports industry-standard microcontrollers. CMOS construction ensures power dissipation, powerdown mode reduces idle power consumption only
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
AD7703 offers 20-bit resolution coupled with outstanding 0.0003% accuracy. missing codes ensures true, usable, 20-bit dynamic range, removing need programmable gain level-setting circuitry. effects temperature drift eliminated on-chip self-calibration, which removes zero gain error. External circuits also included calibration loop remove system offsets gain errors. Flexible synchronous/asynchronous interface allows AD7703 interface directly serial ports industrystandard microcontrollers processors. operating power consumption ultralow power standby mode make AD7703 ideal loop-powered remote sensing applications, battery-powered portable instruments.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2003 Analog Devices, Inc. rights reserved.
AVDD DVDD AVSS DVSS VREF +2.5 fCLKIN 4.096 MHz; BP/UP MODE Source Resistance with AGND AIN; unless otherwise noted.)
Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity, TMAX 25°C TMIN TMAX Differential Nonlinearity, TMIN TMAX Positive Full-Scale Error Full-Scale Drift Unipolar Offset Error Unipolar Offset Drift Bipolar Zero Error Bipolar Zero Drift Bipolar Negative Full-Scale Errors Bipolar Negative Full-Scale Drift Noise (Referred Output) DYNAMIC PERFORMANCE Sampling Frequency, Output Update Rate, Filter Corner Frequency, Settling Time ±0.0007% SYSTEM CALIBRATION Positive Full-Scale Calibration Range Positive Full-Scale Overrange Negative Full-Scale Overrange Maximum Offset Calibration Ranges Unipolar Input Range Bipolar Input Range Input Span7 ANALOG INPUT Unipolar Input Range Bipolar Input Range Input Capacitance Input Bias Current LOGIC INPUTS Inputs Except CLKIN VINL, Input Voltage VINH, Input High Voltage CLKIN VINL, Input Voltage VINH, Input High Voltage IIN, Input Current LOGIC OUTPUTS VOL, Output Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance POWER REQUIREMENTS Power Supply Voltages Analog Positive Supply Digital Positive Supply Analog Negative Supply Digital Negative Supply Calibration Memory Retention Power Supply Voltage Version2 Version2 Version2 Unit Test Conditions/Comments
AD7703-SPECIFICATIONS
±0.0015 ±0.003 ±0.003 ±0.5 ±19/±37 +48/-400 +24/-200 ±10/±20 fCLKIN/256 fCLKIN/1024 fCLKIN/409,600 507904/f CLKIN VREF VREF -(VREF 0.1)
±0.0007 ±0.0015 ±0.0015 ±0.5 fCLKIN/256 fCLKIN/1024 fCLKIN/409,600 507904/fCLKIN VREF VREF -(VREF 0.1) -(VREF 0.1) -0.4 VREF +0.4 VREF VREF VREF ±2.5
±0.0003 ±0.0008 ±0.0012 ±0.5 fCLKIN/256 fCLKIN/1024 fCLKIN/409,600 507904/fCLKIN VREF VREF -(VREF 0.1) -(VREF 0.1) -0.4 VREF +0.4 VREF VREF VREF ±2.5
Bits
Guaranteed Missing Codes
Temp Range: +70°C Specified Temp Range
Temp Range: +70°C Specified Temp Range
Full-Scale Input Step System calibration applies unipolar bipolar ranges. After calibration, VREF, device will output (unipolar) (bipolar), device will output
-(VREF 0.1) -0.4 VREF +0.4 VREF VREF VREF ±2.5
DVDD
DVDD
DVDD
ISINK ISOURCE
4.5/5.5 4.5/AVDD -4.5/-5.5 -4.5/-5.5
4.5/5.5 4.5/AVDD -4.5/-5.5 -4.5/-5.5
4.5/5.5 4.5/AVDD -4.5/-5.5 -4.5/-5.5
min/V Specified Performance min/V min/V min/V
REV.
AD7703
Parameter POWER REQUIREMENTS Power Supply Currents Analog Positive Supply Digital Positive Supply Analog Negative Supply Digital Negative Supply Power Supply Rejection Positive Supplies Negative Supplies Power Dissipation Normal Operation Standby Operations Version2 Version2 Version2 Unit Test Conditions/Comments
Typically Typically Typically Typically 0.03
SLEEP Logic Typically SLEEP Logic Typically
NOTES presents very high impedance dynamic load that varies with clock frequency. ceramic capacitor from AGND necessary. Source resistance should less. Temperature ranges follows: Versions: -40°C +85°C; Version: -55°C +125°C. Applies after calibration temperature interest. Full-scale error applies both unipolar bipolar input ranges. Total drift over specified temperature range after calibration power-up This guaranteed design and/or characterization. Recalibration temperature will remove these errors. Unipolar mode, offset have negative value REF) such that Unipolar mode mimic Bipolar mode operation. specifications input overrange input span apply additional constraints offset calibration range. Unipolar mode, input span difference between full scale zero scale. Bipolar mode, input span difference between positive negative full-scale points. When using less than maximum input span, span range placed anywhere within range (VREF 0.1). digital outputs unloaded. digital inputs CMOS levels. Applies bandwidth. PSRR will exceed digital filter. CLKIN stopped. digital inputs grounded. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS
25°C, unless otherwise noted.)
DVDD AGND -0.3 DVDD AVDD -0.3 +0.3 DVSS AGND +0.3 AVDD AGND -0.3 AVSS AGND +0.3 AGND DGND -0.3 +0.3 Digital Input Voltage DGND -0.3 DVDD Analog Input Voltage AGND AVSS AVDD Input Current Except Supplies2 Operating Temperature Range Industrial Versions) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, secs) 300°C Power Dissipation (DIP Package) 75°C Derates above 75°C mW/°C Power Dissipation (SOIC Package) 75°C Derates above 75°C mW/°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Transient currents will cause latch-up.
ORDERING GUIDE
Model AD7703AN AD7703BN AD7703CN AD7703AR AD7703BR AD7703CR AD7703AQ AD7703BQ AD7703CQ AD7703SQ
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C
Linearity Error FSR) 0.003 0.0015 0.0012 0.003 0.0015 0.0012 0.003 0.0015 0.0012 0.003
Package Options* N-20 N-20 N-20 R-20 R-20 R-20 Q-20 Q-20 Q-20 Q-20
Plastic DIP; SOIC; CERDIP.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7703 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
REV.
AD7703 TIMING CHARACTERISTICS1,
Parameter fCLKIN
(AVDD DVDD 10%; AVSS DVSS 10%; AGND DGND CLKIN 4.096 MHz; Input Levels: Logic Logic DVDD; unless otherwise noted.)
Conditions/Comments Master Clock Frequency: Internal Gate Oscillator Typically 4.096 Master Clock Frequency: Externally Supplied Digital Output Rise Time. Typically Digital Output Fall Time. Typically SC1, High Setup Time SC1, Hold Time after Goes High SLEEP High CLKIN High Setup Time Data Access Time Data Valid) SCLK Falling Edge Data Valid Delay typ) Data Setup Time. Typically SCLK High Pulsewidth. Typically SCLK Pulsewidth. Typically SCLK Rising Edge Hi-Z Delay (l/fCLKIN typ) High Hi-Z Delay Serial Clock Input Frequency SCLK Input High Pulsewidth SCLK Pulsewidth Data Access Time Data Valid). Typically SCLK Falling Edge Data Valid Delay. Typically High Hi-Z Delay SCLK Falling Edge Hi-Z Delay. Typically
Limit TMIN, TMAX Versions) 1000 3/fCLKIN l/fCLKIN 4/fCLKIN
Limit TMIN, TMAX Versions) Unit 1000 3/fCLKIN l/fCLKIN 4/fCLKIN
MODE
t108, MODE fSCLK t137, t1411 t158 t168
NOTES Sample tested 25°C ensure compliance. input signals specified with (10% timed from voltage level Figures CLKIN duty cycle range 80%. CLKIN must supplied whenever AD7703 SLEEP mode. clock present this case, device draw higher current than specified possibly become uncalibrated. AD7703 production tested with CLKIN 4.096 MHz. guaranteed characterization operate kHz. Specified using points waveform interest. order synchronize several AD7703s together using SLEEP pin, this specification must met. measured with load circuit Figure defined time required output cross t10, t15, derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that time quoted Timing Characteristics true relinquish time part such independent external loading capacitance. returned high before bits output, SDATA SCLK outputs will complete current data then high impedance. activated asynchronously DRDY, will recognized occurs when DRDY high four clock cycles. propagation delay time great four CLKIN cycles plus guarantee proper clocking SDATA when using asynchronous SCLK input should taken high sooner than four CLKIN cycles plus after goes low. SDATA clocked falling edge SCLK input. Specifications subject change without notice.
1.6mA
SC1,
SC1, VALID
OUTPUT
2.1V
Figure Calibration Control Timing
100pF
Figure Load Circuit Access Time Relinquish Time
CLKIN
SLEEP
Figure Sleep Mode Timing
REV.
AD7703
SDATA DATA VALID HI-Z
SDATA DATA VALID HI-Z
Figure Mode Data Hold Time
CLKIN
DRDY
Figure Mode Data Hold Time
SCLK HI-Z
HI-Z
SCLK
DB19 DB18
HI-Z
SDATA
HI-Z
SDATA
HI-Z DB19 DB18
HI-Z
Figure Mode Timing Diagram
Figure Mode Timing Diagram
DEFINITION TERMS Linearity Error
Positive Full-Scale Overrange
This maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero-scale (not confused with bipolar zero), point below first code transition (000 001) full-scale, point above last code transition (111 111). error expressed percentage full scale.
Differential Linearity Error
Positive full-scale overrange amount overhead available handle input voltages greater than +VREF (for example, noise peaks excess voltages system gain errors system calibration routines) without introducing errors overloading analog modulator overflowing digital filter.
Negative Full-Scale Overrange
This difference between code's actual width ideal LSB) width. Differential linearity error expressed LSB. differential linearity specification less guarantees monotonicity.
Positive Full-Scale Error
This amount overhead available handle voltages below -VREF without overloading analog modulator overflowing digital filter. Note that analog input will accept negative voltage peaks even Unipolar mode.
Offset Calibration Range
Positive full-scale error deviation last code transition (111 111) from ideal (VREF LSB). applies both positive negative analog input ranges expressed microvolts.
Unipolar Offset Error
system calibration modes (SC2 low), AD7703 calibrates offset with respect pin. offset calibration range specification defines range voltages, expressed percentage VREF, that AD7703 accept still accurately calibrate offset.
Full-Scale Calibration Range
This range voltages that AD7703 accept system calibration mode still correctly calibrate full scale.
Input Span
Unipolar offset error deviation first code transition from ideal (AGND LSB) when operating Unipolar mode.
Bipolar Zero Error
This deviation midscale transition (0111 1000 000) from ideal (AGND LSB) when operating Bipolar mode. expressed microvolts.
Bipolar Negative Full-Scale Error
system calibration schemes, voltages applied sequence AD7703's analog input define analog input range. input span specification defines minimum maximum input voltages from zero full scale that AD7703 accept still accurately calibrate gain. input span expressed percentage VREF.
This deviation first code transition from ideal (-VREF LSB) when operating Bipolar mode.
REV.
AD7703
CONFIGURATION DIP, CERDIP, SOIC
MODE CLKOUT CLKIN DGND DVSS AVSS AGND
Table Weight Table (2.5 Reference Voltage)
SDATA SCLK DRDY
0.596 1.192 2.384 4.768 9.537
0.25 1.00 2.00 4.00
Unipolar Mode 0.0000238 0.0000477 0.0000954 0.0001907 0.0003814 0.24 0.48 0.95 1.91 3.81
0.13 0.26 1.00 2.00
Bipolar Mode 0.0000119 0.0000238 0.0000477 0.0000954 0.0001907 0.12 0.24 0.48 0.95 1.91
AD7703
VIEW (Not Scale) DVDD
AVDD
BP/UP SLEEP
VREF
FUNCTION DESCRIPTIONS
Mnemonic Description MODE Selects Serial Interface Mode. MODE tied DGND, Synchronous External Clocking (SEC) mode selected. SCLK configured input, output appears without formatting, coming first. MODE tied AD7703 operates Synchronous Self-Clocking (SSC) mode. SCLK configured output, with clock frequency fCLKIN/4 duty cycle. Clock Output Generate Internal Master Clock Connecting Crystal between CLKOUT CLKIN. external clock used, CLKOUT connected. Clock Input External Clock. System Calibration Pins. state these pins, when taken high, determines type calibration performed. Digital Ground. Ground reference digital signals. Digital Negative Supply, Nominal. Analog Negative Supply, Nominal. Analog Ground. Ground reference analog signals. Analog Input. Voltage Reference Input, Nominal. This determines value positive full scale Unipolar mode value both positive negative full scale Bipolar mode. Sleep Mode Pin. When this taken low, AD7703 goes into power mode with typically power consumption. Bipolar/Unipolar Mode Pin. When this low, AD7703 configured unipolar input range going from AGND VREF. When high, AD7703 configured bipolar input range, ±VREF. Calibration Mode Pin. When taken high more than four cycles, AD7703 reset performs calibration cycle when brought again. also used strobe synchronize operation several AD7703s. Analog Positive Supply, Nominal. Digital Positive Supply, Nominal. Chip Select Input. When brought low, AD7703 will begin transmit serial data format determined state MODE pin. Data Ready Output. DRDY when valid data available output register. goes high after transmission word completed. also goes high four clock cycles when data-word being loaded into output register, indicate that valid data available, irrespective whether data transmission complete not. Serial Clock Input/Output. SCLK configured input output, dependent type serial data transmission that been selected MODE pin. When configured output Synchronous Self-Clocking mode, frequency fCLKIN/4 duty cycle 25%. Serial Data Output. AD7703's output data available this 20-bit serial word.
REV.
CLKOUT CLKIN SC1, DGND DVSS AVSS AGND VREF SLEEP BP/UP
AVDD DVDD DRDY
SCLK
SDATA
AD7703
GENERAL DESCRIPTION
1-bit converter (comparator) 1-bit digital low-pass filter
ANALOG LOW-PASS FILTER COMPARATOR DIGITAL FILTER
AD7703 20-bit converter with on-chip digital filtering, intended measurement wide dynamic range, frequency signals such those representing chemical, physical, biological processes. contains charge-balancing ADC, calibration microcontroller with on-chip static RAM, clock oscillator, serial communications port. analog input signal AD7703 continuously sampled rate determined frequency master clock, CLKIN. charge-balancing converter modulator) converts sampled signal into digital pulse train whose duty cycle contains digital information. six-pole Gaussian digital low-pass filter processes output modulator updates 20-bit output register rate. output data read from serial port randomly periodically rate kHz.
ANALOG SUPPLY
DIGITAL DATA
Figure General
AVDD
DVDD SLEEP MODE
operation, analog signal sample subtracter, along with output 1-bit DAC. filtered difference signal comparator, whose output samples difference signal frequency many times that analog signal sampling frequency (oversampling). Oversampling fundamental operation ADCs. Using quantization noise formula (6.02 number bits 1.76) 1-bit comparator yields 7.78 AD7703 samples input signal kHz, which spreads quantization noise from kHz. Since specified analog input bandwidth AD7703 only noise energy this bandwidth would only 1/800 total quantization noise, even noise energy were spread evenly throughout spectrum. reduced still further analog filtering modulator loop, which shapes quantization noise spectrum move most noise energy frequencies above performance range conditioned 20-bit level this fashion. output comparator provides digital input 1-bit DAC, system functions negative feedback loop that minimizes difference signal. digital data that represents analog input voltage duty cycle pulse train appearing output comparator. retrieved parallel binary data-word using digital filter. ADCs generally described order analog low-pass filter. simple example first-order, shown Figure This contains only first-order, low-pass filter integrator. also illustrates derivation alternative name these devices: charge-balancing ADCs. AD7703 uses second-order, modulator sophisticated digital filter that provides rolling average sampled output. After power-up there step change input voltage, there settling time that must elapse before valid data obtained.
VOLTAGE REFERENCE
2.5V VREF
DRDY
DATA READY READ (TRANSMIT) SERIAL CLOCK SERIAL DATA
AD7703
RANGE SELECT CALIBRATE ANALOG INPUT ANALOG GROUND BP/UP
SCLK SDATA CLKIN CLKOUT AGND AVSS ANALOG SUPPLY DGND
DVSS
Figure Typical System Connection Diagram
AD7703 perform self-calibration using on-chip calibration microcontroller SRAM store calibration parameters. calibration cycle initiated time using control input. Other system components also included calibration loop remove offset gain errors input channel. battery operation, AD7703 also offers standby mode that reduces idle power consumption typically
THEORY OPERATION
general block diagram shown Figure contains following elements: sample-hold amplifier differential amplifier subtracter analog low-pass filter
REV.
AD7703
DIGITAL FILTERING
AD7703's digital filter behaves like analog filter, with minor differences. First, since digital filtering occurs after analog-to-digital conversion, remove noise injected during conversion process. Analog filtering cannot this. other hand, analog filtering remove noise superimposed analog signal before reaches ADC. Digital filtering cannot this noise peaks riding signals near full scale have potential saturate analog modulator digital filter, even though average value signal within limits. alleviate this problem, AD7703 overrange headroom built into modulator digital filter that allows overrange excursions noise signals larger than this, consideration should given analog input filtering, reducing gain input channel that full-scale input (2.5 gives only half-scale input AD7703 (1.25 This will provide overrange capability greater than 100% expense reducing dynamic range (50%).
FILTER CHARACTERISTICS
output settling AD7703 response step input change shown Figure Gaussian response fast settling with overshoot, worst-case settling time ±0.0007% with 4.096 master clock frequency.
PERCENT FINAL VALUE
TIME
Figure AD7703 Step Response
USING AD7703 SYSTEM DESIGN CONSIDERATIONS
cutoff frequency digital filter fCLK/409600. maximum clock frequency 4.096 MHz, cutoff frequency filter data update rate kHz. Figure shows filter frequency response. This six-pole Gaussian response that provides rejection cutoff frequency. clock frequency halved give cutoff, rejection better than
GAIN
AD7703 operates differently from successive approximation ADCs integrating ADCs. Since samples signal continuously, like tracking ADC, there need start convert command. 20-bit output register updated rate, output read time, either synchronously asynchronously.
CLOCKING
fCLK 4MHz
fCLK 2MHz
AD7703 requires master clock input, which external TTL/CMOS compatible clock signal applied CLKIN (CLKOUT used). Alternatively, crystal correct frequency connected between CLKIN CLKOUT, when clock circuit will function crystal controlled oscillator. Figure shows simple model on-chip gate oscillator Table gives some typical capacitor values used with various resonators.
-100 -120
fCLK 1MHz
-140 -160
FREQUENCY
Figure Frequency Response AD7703 Filter
Since AD7703 contains this low-pass filtering, there settling time associated with step function inputs, data will invalid after step change until settling time elapsed. AD7703 therefore, unsuitable high speed multiplexing, where channels switched converted sequentially high rates, switching between channels cause step change input. However, slow multiplexing AD7703 possible, provided that settling time allowed elapse before data channel accessed.
1500
10pF
10pF
AD7703
*SEE TABLE
Figure On-Chip Gate Oscillator
REV.
AD7703
Table Resonator Loading Capacitors
Resonators Ceramic Crystal 2.000 3.579 4.096
(pF) None
(pF) None
capacitance/voltage coefficient. device also achieves input drift through chopper-stabilized techniques input stage. ensure excellent performance over time temperature, AD7703 uses digital calibration techniques that minimize offset gain error typically LSB.
AUTOCALIBRATION
input sampling frequency, output data rate, filter characteristics, calibration time directly related master clock frequency, fCLKIN, ratios given Specification table under Dynamic Performance. Therefore, first step system design with AD7703 select master clock frequency suitable bandwidth output data rate required application.
ANALOG INPUT RANGES
AD7703 offers both self-calibration system-calibration facilities. calibration occur, on-chip microcontroller must record modulator output different input conditions. These zero-scale full-scale points. Unipolar self-calibration mode, zero-scale point VAGND full-scale point VREF. With these readings, microcontroller calculate gain slope input output transfer function converter. Unipolar mode, slope factor determined dividing span between zero full scale 220. Bipolar mode, determined dividing span since inputs applied represent only half total codes. both Unipolar Bipolar modes, slope factor saved used calculate binary output code when analog input applied device. Table gives output code size after calibration. System calibration allows AD7703 compensate system gain offset errors. typical circuit where this might used shown Figure System calibration performs same slope factor calculations self-calibration uses voltage values presented system zero- full-scale points. There system calibration modes. first mode offers system level calibration system offset system gain. This step operation. zero-scale point must presented converter first. must applied converter before calibration step initiated remain stable until step complete. DRDY output from device will signal when step complete going low. After zero-scale point calibrated, full-scale point applied second calibration step initiated. Again, voltage must remain stable throughout calibration step. step calibration mode offers another feature. After sequence been completed, additional offset calibrations performed themselves adjust zero reference point system zero reference value. This second system calibration mode uses input voltage zero-scale calibration point uses VREF value full-scale point.
AD7703 performs conversion relative externally supplied reference voltage that allows easy interfacing ratiometric systems. addition, either unipolar bipolar input voltage ranges selected using BP/UP input. With BP/UP tied low, input range unipolar span (VREF VAGND), where VAGND voltage device AGND pin. With BP/UP tied high, input range bipolar span 2VREF. Bipolar mode, both positive negative full scale directly determined VREF. This offers superior tracking positive negative full scale better midscale (bipolar zero) stability than bipolar schemes that simply scale offset input range. digital output coding unipolar range unipolar binary; bipolar range offset binary. weights Unipolar Bipolar modes shown Table ADCs, like VFCs other integrating ADCs, contain source nonmonotonicity inherently offer no-missing-codes performance. AD7703 achieves excellent linearity high quality, on-chip silicon dioxide capacitors, which have very
ACCURACY
SYSTEM SYSTEM ANALOG SIGNAL CONDITIONING
SCLK SDATA MICROCOMPUTER
AD7703
Figure Typical Connections System Calibration
REV.
AD7703
Initiating Calibration
Table illustrates calibration modes available AD7703. shown table function BP/UP pin, which determines whether converter been calibrated measure bipolar unipolar signals. calibration step initiated bringing high least four CLKIN cycles then bringing again. states along with BP/UP will determine type calibration performed. three signals should stable before taken positive. inputs latched when goes high. BP/UP input latched and, therefore, must remain fixed state throughout calibration measurement cycles. time state BP/UP changed, calibration cycle must performed enable AD7703 function properly mode. When calibration step initiated, DRDY signal will high remain high until step finished. Table shows number clock cycles each calibration requires. Once calibration step initiated, must finish before calibration step executed. step system calibration mode, offset calibration step must initiated before initiating gain calibration step.
When self-calibration completed, DRDY falls output port updated with data-word that represents analog input signal. When system calibration step completed, DRDY will fall output port will updated with appropriate data value (all zero-scale point full-scale point). system calibration mode, digital filter must settle before output code will represent value analog input signal. Tables indicate output code size output coding AD7703 various modes. these tables, SOFF measured system offset volts SGAIN measured system gain full-scale point volts.
Span Offset Limits
Whenever system calibration mode used, there limits amount offset span that accommodated. range input span both Unipolar Bipolar modes minimum value VREF maximum value 2(VREF amount offset that accommodated depends whether Unipolar Bipolar mode being used. Unipolar mode, system calibration modes handle maximum offset VREF minimum offset -(VREF Therefore AD7703 Unipolar mode calibrated mimic bipolar operation.
Table III. Calibration Truth Table*
Calibration Type Self-Calibration System Offset System Gain System Offset
Zero-Scale Calibration VAGND
Full-Scale Calibration VREF VREF
Sequence Step First Step Second Step Step
Calibration Time 3,145,655 Clock Cycles 1,052,599 Clock Cycles 1,068,813 Clock Cycles 2,117,389 Clock Cycles
*DRDY remains high throughout calibration sequence. Self-Calibration mode, DRDY falls once AD7703 settled analog input. other modes, DRDY falls device begins settle.
Table Output Code Size After Calibration
Calibration Mode Self-Calibration
Zero Scale VAGND
Gain Factor VREF
Unipolar AGND 1048576 (SGAIN SOFF 1048576
Bipolar AGND 1048576 2(SGAIN SOFF 1048576
System Calibration
SOFF
SGAIN
-10-
REV.
AD7703
Table Output Coding
Input Voltage, Unipolar Mode
System Calibration >(SGAIN -1.5 LSB) SGAIN Self-Calibration >(VREF LSB) VREF Output Codes FFFFF
FFFFF FFFFE 80000 7FFFF 00001 00000
Input Voltage, Bipolar Mode
Self-Calibration >(VREF -1.5 LSB) VREF System Calibration >(SGAIN LSB) SGAIN
(SGAIN SOFF)/2
(VREF VAGND)/2
VAGND
SOFF
SOFF <(SOFF LSB)
VAGND <(VAGND LSB)
-VREF <(-VREF LSB)
-SGAIN SOFF <(-SGAIN SOFF LSB)
00000
Bipolar mode, system offset calibration range restricted ±0.4 VREF. should noted that span restrictions limit amount offset that calibrated. span range converter Bipolar mode equidistant around voltage used zero-scale point. When zero-scale point calibrated, must cause either endpoints bipolar transfer function exceed positive negative input overrange points (+VREF 0.1) (-VREF 0.1) span range minimum (0.8 VREF), offset voltage move +0.4 VREF without causing endpoints transfer function exceed overrange points. Alternatively, span range 2VREF, input offset cannot move more than +0.1 -0.1 before endpoint transfer function exceeds input overrange limit.
POWER-UP CALIBRATION
accordingly. value voltage sample capacitor updated rate determined master clock; therefore, amount offset drift that occurs will proportional elapsed time between samples. Thus, minimize offset drift higher temperatures, higher CLKIN rates recommended. Gain drift within converter depends mainly upon temperature tracking internal capacitors. affected leakage currents significantly less than offset drift. typical gain drift AD7703 less than over specified temperature range. Measurement errors offset drift gain drift eliminated time recalibrating converter. Using system calibration mode also minimize offset gain errors signal conditioning circuitry. Integral differential linearity significantly affected temperature changes.
CLKIN 4.096MHz
BIPOLAR OFFSET LSBs
calibration cycle must carried after power-up initialize device consistent starting condition correct calibration. must held high least four clock cycles, after which calibration initiated falling edge takes maximum 3,145,655 clock cycles (approximately with 4.096 clock). Table III. type calibration cycle initiated determined inputs, accordance with Table III.
Drift Considerations
AD7703 uses chopper stabilization techniques minimize input offset drift. Charge injection analog switches leakage currents sampling node primary sources offset voltage drift converter. Figure indicates typical offset temperature changes after calibration 25°C. Drift relatively flat 75°C. Above this temperature, leakage current becomes main source offset drift. Since leakage current doubles approximately every 10°C, offset drifts
-160
-240
-320
TEMPERATURE
Figure Typical Bipolar Offset Temperature after Calibration 25°C
REV.
-11-
AD7703
INPUT SIGNAL CONDITIONING
Reference voltages from used with AD7703, with little degradation performance. Input ranges that cannot accommodated this range reference voltages achieved input signal conditioning. This take form gain accommodate smaller signal range, passive attenuation reduce larger input voltage range.
Source Resistance
filter added front AD7703 reduce high frequency noise. With external capacitor added from AGND, following equation will specify maximum allowable source resistance:
fCLKIN (CIN CEXT
passive attenuators used front AD7703, care must taken ensure that source impedance sufficiently low. input resistance AD7703 over parallel with this, there small dynamic load that varies with clock frequency (see Figure 14).
practical limit maximum value source resistance thermal (Johnson) noise. practical resistor modeled ideal (noiseless) resistor series with noise voltage source parallel with noise current source:
kTRf Volts
AD7703
Amperes
CEXT 10pF AGND 100mV
where Boltzmann's constant (1.38 10-23 J/K), temperature degrees Kelvin 273). Active signal conditioning circuits such amps generally suffer from problems high source impedance. Their openloop output resistance normally only tens ohms and, case, most modern general-purpose amps have sufficiently fast closed-loop settling time this problem. Offset voltage amps eliminated system calibration routine.
Antialias Considerations
Figure Equivalent Input Circuit Input Attenuator
Each time analog input sampled, capacitor draws charge packet maximum from analog source with frequency fCLKIN/256. 4.096 CLKIN, this yields average current draw After each sample, AD7703 allows clock periods input voltage settle. equation that defines settling time
-t/RC
digital filter AD7703 does provide rejection integer multiples sampling frequency (nfCLKIN/256, where With 4.096 master clock, there narrow (±10 bands kHz, kHz, kHz, where noise passes unattenuated output. However, AD7703's high oversampling ratio Hz), these bands occupy only small fraction spectrum, most broadband noise filtered. reduction broadband noise given
where final settled value, VIN, value input signal, value input source resistance, sample capacitor. value equal 62/fCLKIN. following equation developed, which gives maximum allowable source resistance, RS(MAX), error
fCLKIN (100
eout 0.035
where eout noise terms referred input, filter corner frequency (fCLKIN/409600), sampling frequency (fCLKIN/256). Since ratio fCLKIN fixed, digital filter reduces broadband white noise 96.5% independent master clock frequency.
Provided source resistance less than this value, analog input will settle within desired error band requisite clock periods. Insufficient settling leads offset errors. These calibrated system calibration schemes. limit (0.25 bits) maximum offset voltage, then maximum allowable source resistance from above equation, assuming that there external stray capacitance.
-12-
REV.
AD7703
VOLTAGE REFERENCE CONNECTIONS
voltage applied VREF defines analog input range. specified reference voltage AD7703 will operate with reference voltages from with little degradation performance. reference input presents exactly same dynamic load analog input, case reference input, source resistance long settling time introduce gain errors rather than offset errors. Fortunately, most precision references have sufficiently output impedance wide enough bandwidth settle required accuracy within clock cycles. digital filter AD7703 removes noise from reference input, just does with noise analog input, same limitations apply regarding lack noise rejection integer multiples sampling frequency. Note that reference should chosen minimize noise below AD7703 typically exhibits noise measurements. This specification assumes clean reference. Many monolithic band references available, which supply needed AD7703. However, some these specified noise, especially bandwidth. reference noise this bandwidth excessive, degrade performance AD7703. Recommended references AD580 LT1019. Both these references typically have less than noise band.
POWER SUPPLIES GROUNDING
provide rejection broadband noise power supplies, except integer multiples sampling frequency. Therefore, analog supplies should individually decoupled AGND using ceramic capacitors provide power supply noise rejection these frequencies. digital supplies should similarly decoupled DGND. positive digital supply (DVDD) must never exceed positive analog supply (AVDD) more than Power supply sequencing therefore, important. separate analog digital supplies used, care must taken ensure that analog supply powered first. also important that power applied AD7703 before signals VREF, AIN, logic input pins order avoid possibility latch-up. separate supplies used AD7703 system digital circuitry, AD7703 should powered first. typical scheme powering AD7703 from single rails shown Figure this circuit, AVDD DVDD brought along separate tracks from same supply. Thus, there possibility digital supply coming before analog supply.
SLEEP MODE
AGND ground reference voltage AD7703, completely independent DGND. noise riding AGND input with respect system analog ground will cause conversion errors. AGND should, therefore, used system ground also ground analog input reference voltage. analog digital power supplies AD7703 independent separately pinned minimize coupling between analog digital sections device. digital filter will
power standby mode initiated taking SLEEP input low, which shuts down analog digital circuits reduces power consumption When coming SLEEP mode, sometimes possible (when using crystal generate CLKIN, example) lose calibration coefficients. Therefore, advisable safeguard always calibration cycle after coming SLEEP mode.
DIGITAL INTERFACE
AD7703's serial communications port allows easy interfacing industry-standard microprocessors. different modes operation available, optimized different types interface.
REV.
-13-
AD7703
Synchronous Self-Clocking Mode (SSC)
mode (MODE high) allows easy interfacing serial-parallel conversion circuits systems with parallel data communication. This mode allows interfacing 74XX299 Universal Shift registers without additional decoding. mode also used with microprocessors such 68HC11 68HC05, which allow external device clock their serial port. Figure shows timing diagram mode. Data clocked internally generated serial clock. AD7703 divides each sampling interval into distinct periods. Eight periods clock pulses analog settling eight periods clock pulses digital computation. status polled beginning each digital computation period. these times, then SCLK will become active
data-word currently output register will transmitted, first. After been transmitted, DRDY will high until data-word becomes available. having been brought low, taken high again time during data transmission, SDATA SCLK will three-state after current finishes. subsequently brought low, transmission will resume with next during subsequent digital computation period. transmission been initiated completed time next data-word available, DRDY will high four clock cycles then again word loaded into output register. more detailed diagram data transmission mode shown Figure Data bits change falling edge SCLK valid rising edge SCLK.
1024 CLKIN CYCLES CLKIN CYCLES INTERNAL STATUS ANALOG TIME CLKIN CYCLES DRDY CLKIN CYCLES DIGITAL TIME DIGITAL TIME
POLLED HI-Z SCLK SDATA HI-Z HI-Z HI-Z
Figure Timing Diagram Transmission Mode
CLKIN CLKIN CYCLES DRDY
HI-Z SDATA HI-Z DB19 (MSB) DB18 DB17 (LSB) HI-Z HI-Z
SCLK
Figure Mode Showing Data Timing Relative SCLK
-14-
REV.
AD7703
Synchronous External Clock Mode (SEC) DIGITAL NOISE OUTPUT LOADING
mode (MODE grounded) designed direct interface synchronous serial ports industry-standard microprocessors such 68HC11 68HC05. mode also allows customized interfaces, using port pins, microprocessors that have direct with AD7703's other mode. shown Figure falling edge enables serial data output with initially valid. Subsequent data bits change falling edge externally supplied SCLK. After been transmitted, DRDY SDATA three-state. AD7703 still transmitting data when data-word becomes available, data-word continues transmitted data lost. taken high time during data transmission, SDATA will three-state immediately. returns low, AD7703 will continue transmission with same data bit. transmission been initiated completed time next data-word becomes available, high, DRDY returns high four clock cycles, then falls word loaded into output register.
mentioned earlier, AD7703 divides internal timing into distinct phases, analog sampling settling digital computation. mode, data transmitted only during digital computation periods, minimize effects digital noise analog performance. mode, data transmission externally controlled, this automatic safeguard does exist. compensate, synchronize AD7703 digital system clock CLKIN when used mode. Whatever mode operation used, resistive capacitive loads digital outputs should minimized order reduce crosstalk between analog digital portions circuit. this reason, connection power CMOS logic such 4000 series families recommended.
DRDY
SCLK
HI-Z SDATA DB19 (MSB) DB18 DB17 (LSB)
HI-Z
Figure Timing Diagram Mode
REV.
-15-
AD7703
OUTLINE DIMENSIONS 20-Lead Plastic Dual In-Line Package [PDIP] (N-20)
Dimensions shown inches (millimeters)
0.985 (25.02) 0.965 (24.51) 0.945 (24.00)
20-Lead Ceramic Dual In-Line Package [CERDIP] (Q-20)
Dimensions shown inches (millimeters)
0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62)
0.310 (7.87) 0.220 (5.59)
0.180 (4.57)
0.015 (0.38)
0.150 (3.81) 0.135 (3.43) 0.120 (3.05)
0.200 (5.08)
1.060 (26.92)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81)
0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)
0.150 (3.81) 0.130 (3.30) 0.110 (2.79)
0.200 (5.08) 0.125 (3.18)
0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.100 0.060 (1.52) SEATING (2.54) 0.050 (1.27) PLANE 0.045 (1.14) 0.015 (0.38) 0.010 (0.25) 0.008 (0.20)
0.023 (0.58) 0.014 (0.36)
0.100 (2.54)
0.070 (1.78) SEATING 0.030 (0.76) PLANE
COMPLIANT JEDEC STANDARDS MO-095-AE CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
CONTROLLING DIMENSIONS INCHES; MILLIMETERS DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
20-Lead Standard Small Outline Package [SOIC] Wide Body (R-20)
Dimensions shown millimeters (inches)
13.00 (0.5118) 12.60 (0.4961)
7.60 (0.2992) 7.40 (0.2913)
10.65 (0.4193) 10.00 (0.3937)
0.30 (0.0118) 0.10 (0.0039) 1.27 (0.0500)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
COPLANARITY 0.10
0.51 (0.0201) SEATING 0.32 (0.0126) PLANE 0.33 (0.0130) 0.23 (0.0091)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT JEDEC STANDARDS MS-013AC CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS PARENTHESES) ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
Revision History
Location 4/03-Data Sheet changed from REV. REV. Page
Updated format .Universal Changes SPECIFICATIONS Updated OUTLINE DIMENSIONS -16- REV.
C01165-0-4/03(E)
0.005 (0.13)
0.098 (2.49)
Other recent searches
SN74HC193 - SN74HC193 SN74HC193 Datasheet
SN54HC193 - SN54HC193 SN54HC193 Datasheet
SHD3185P - SHD3185P SHD3185P Datasheet
RM5261ATM - RM5261ATM RM5261ATM Datasheet
BD1416N5050A00 - BD1416N5050A00 BD1416N5050A00 Datasheet
BA6289F - BA6289F BA6289F Datasheet
BA6417F - BA6417F BA6417F Datasheet
BA511 - BA511 BA511 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
