10-Bit, MSPS High Speed TxDAC+ Converter AD9751* FUNCTIONAL BLOCK
|
|
|
Top Searches for this datasheet
FEATURES 10-Bit Dual Muxed Port MSPS Output Update Rate Excellent SFDR Performance SFDR Nyquist Output: Internal Clock Doubling Differential Single-Ended Clock Input On-Chip Reference Single Supply Operation Power Dissipation: 48-Lead LQFP APPLICATIONS Communications: LMDS, LMCS, MMDS Base Stations Digital Synthesis OFDM
10-Bit, MSPS High Speed TxDAC+ Converter AD9751*
FUNCTIONAL BLOCK DIAGRAM
DVDD DCOM AVDD ACOM PORT1 LATCH PORT2 LATCH
LATCH
IOUTA IOUTB
CLK+ CLK- CLKVDD PLLVDD CLKCOM
CLOCK MULTIPLIER
REFERENCE
REFIO FSADJ
AD9751
RESET DIV0 DIV1 PLLLOCK
PRODUCT DESCRIPTION
AD9751 dual muxed port, ultrahigh speed, singlechannel, 10-bit CMOS DAC. integrates high quality 10-bit TxDAC+ core, voltage reference, digital interface circuitry into small 48-lead LQFP package. AD9751 offers exceptional performance while supporting update rates MSPS. AD9751 been optimized ultrahigh speed applications MSPS where data rates exceed those possible single data interface port DAC. digital interface consists buffered latches well control logic. These latches time multiplexed high speed several ways. This drives latch twice speed externally applied clock able interleave data from input channels. resulting output data rate twice that input channels. With disabled, external clock supplied divided internally. inputs (CLK+/CLK-) driven either differentially single-ended, with signal swing p-p.
utilizes segmented current source architecture combined with proprietary switching technique reduce glitch energy maximize dynamic accuracy. Differential current outputs support single-ended differential applications. differential outputs each provide nominal full-scale current from AD9751 manufactured advanced cost 0.35 CMOS process. operates from single supply consumes power.
PRODUCT HIGHLIGHTS
AD9751 member compatible family high speed TxDAC+s, providing 10-, 12-, 14-bit resolution. Ultrahigh Speed MSPS Conversion Rate. Dual 10-Bit Latched, Multiplexed Input Ports. AD9751 features flexible digital interface allowing high speed data conversion through either single dual port input. Power. Complete CMOS function operates from single supply. fullscale current reduced lower power operation. On-Chip Voltage Reference. AD9751 includes 1.20 temperature compensated band voltage reference.
*Protected U.S. Patent numbers 5450084, 5568145, 5689257, 5703519. Other patents pending.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2003 Analog Devices, Inc. rights reserved.
AD9751-SPECIFICATIONS
SPECIFICATIONS
Parameter RESOLUTION ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD PLLVDD CLKVDD Analog Supply Current (IAVDD)4 Digital Supply Current (IDVDD)4 Supply Current (IPLLVDD)4 Clock Supply Current (ICLKVDD)4 Power Dissipation4 IOUTFS Power Dissipation5 IOUTFS Power Supply Rejection Ratio6-AVDD Power Supply Rejection Ratio6-DVDD OPERATING RANGE
NOTES Measured OUTA, driving virtual ground. Nominal full-scale current, OUTFS, IREF current. external buffer amplifier recommended drive external load. MSPS fDAC with fOUT MHz, supplies MSPS fDAC. power supply variation. Specifications subject change without notice.
TMAX, AVDD DVDD PLLVDD CLKVDD IOUTFS unless otherwise noted.)
-0.5 -0.025 -1.0 0.01 0.25 1.14 1.20 1.26 +0.5 +0.025 20.0 +1.25 Unit Bits FSR/C FSR/C FSR/C ppm/C
1.25
10.0
11.5 +0.1 +0.04
-0.1 -0.04
FSR/V FSR/V
REV.
AD9751 DYNAMIC SPECIFICATIONS Transformer Coupled Output,
Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fDAC) Output Settling Time (tST) 0.1%)1 Output Propagation Delay (tPD)1 Glitch Impulse1 Output Rise Time (10% 90%)1 Output Fall Time (90% 10%)1 Output Noise (IOUTFS Output Noise (IOUTFS LINEARITY Spurious-Free Dynamic Range Nyquist fDAC MSPS; fOUT 1.00 dBFS Output dBFS Output dBFS Output fDATA MSPS; fOUT MHz2 fDATA MSPS; fOUT MHz2 fDATA MSPS; fOUT 10.1 MHz2 fDATA MSPS; fOUT 20.1 MHz2 fDATA MSPS; fOUT 30.1 MHz2 fDAC MSPS; fOUT fDAC MSPS; fOUT 11.1 fDAC MSPS; fOUT 31.1 fDAC MSPS; fOUT 51.1 fDAC MSPS; fOUT 71.1 fDAC MSPS; fOUT fDAC MSPS; fOUT 26.1 fDAC MSPS; fOUT 51.1 fDAC MSPS; fOUT 101.1 fDAC MSPS; fOUT 141.1 Spurious-Free Dynamic Range within Window fDAC MSPS; fOUT MHz; Span dBFS fDAC MSPS; fOUT 5.02 MHz; Span fDAC MSPS; fOUT 5.04 MHz; Span Total Harmonic Distortion fDAC MSPS; fOUT 1.00 dBFS fDAC MHz; fOUT 2.00 fDAC MHz; fOUT 2.00 Multitone Power Ratio (Eight Tones Spacing) fDAC MSPS; fOUT 2.00 2.77 dBFS Output dBFS Output dBFS Output
NOTES Measured single-ended into load. Single-Port Mode (PLL disabled, DIV0 DIV1 data Port Specifications subject change without notice.
(TMIN TMAX, AVDD DVDD CLKVDD PLLVDD IOUTFS Differential Doubly Terminated, unless otherwise noted.)
Unit MSPS pV-s pA/÷Hz pA/÷Hz
REV.
AD9751-SPECIFICATIONS
DIGITAL SPECIFICATIONS
Parameter DIGITAL INPUTS Logic Logic Logic Current Logic Current Input Capacitance Input Setup Time (tS), Input Hold Time (tH), Latch Pulsewidth (tLPW), Input Setup Time (tS, PLLVDD Input Hold Time (tH, PLLVDD PLLLOCK Delay (tD, PLLVDD Latch Pulsewidth (tLPW PLLVDD PLLOCK (VOH) PLLOCK (VOL) INPUTS Input Voltage Range Common-Mode Voltage Differential Voltage Frequency*
Specifications subject change without notice.
(TMIN TMAX, AVDD DVDD PLLVDD CLKVDD IOUTFS unless otherwise noted.)
-1.0 -1.5 Unit
0.75 2.25
6.25
*Min Frequency only applies when using internal PLL. When disabled, there minimum frequency.
REV.
AD9751
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD, DVDD, CLKVDD, PLLVDD AVDD, DVDD, CLKVDD, PLLVDD ACOM, DCOM, CLKCOM, PLLCOM REFIO, REFLO, FSADJ IOUTA, IOUTB Digital Data Inputs (DB9 DB0) CLK+/CLK-, PLLLOCK DIV0, DIV1, RESET Junction Temperature Storage Temperature Lead Temperature sec)
With Respect ACOM, DCOM, CLKCOM, PLLCOM ACOM, DCOM, CLKCOM, PLLCOM ACOM, DCOM, CLKCOM, PLLCOM ACOM ACOM DCOM CLKCOM CLKCOM PLLCOM
-0.3 -3.9 -0.3 -0.3 -1.0 -0.3 -0.3 -0.3 -0.3
+3.9 +3.9 +3.9 AVDD AVDD DVDD CLKVDD CLKVDD PLLVDD +150
Unit
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
PORT DATA PORT
ORDERING GUIDE
DATA
Model
DATA
Temperature Range
Package Description 48-Lead LQFP
Package Option ST-48 Evaluation Board
AD9751AST -40C +85C AD9751-EB
INPUT (PLL ENABLED) IOUTA IOUTB
DATA DATA
THERMAL CHARACTERISTIC Thermal Resistance
91C/W
Figure Timing
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9751 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD9751
CONFIGURATION
CLKCOM CLKVDD PLLVDD FSADJ REFIO ACOM
AVDD
IOUTA
IOUTB
DIV1
RESET CLK+ CLK- DCOM DVDD PLLLOCK MSB-P1B9 P1B8 P1B7 P1B6 P1B5 P1B4
DIV0
IDENTIFIER
RESERVED RESERVED RESERVED RESERVED P2B0-LSB P2B1 P2B2 P2B3 P2B4 P2B5 P2B6 P2B7
AD9751
VIEW (Not Scale)
MSB-P2B9
P1B3
P1B2
P1B1
RESERVED
RESERVED
RESERVED
RESERVED
LSB-P1B0
DCOM
DVDD
P2B8
RESERVED USER CONNECTIONS
FUNCTION DESCRIPTIONS
7-16 17-20, 33-36 23-32
Mnemonic RESET CLK+ CLK- DCOM DVDD PLLLOCK P1B9-P1B0 RESERVED P2B9-P2B0 DIV0, DIV1 REFIO FSADJ AVDD IOUTB IOUTA ACOM CLKCOM PLLVDD CLKVDD
Description Internal Clock Divider Reset Differential Clock Input Differential Clock Input Digital Common Digital Supply Voltage Lock Indicator Output Data Bits P1B9 P1B0, Port Data Bits P2B9 P2B0, Port Control Inputs Input Port Selector Mode; Tables details. Reference Input/Output Full-Scale Current Output Adjust Analog Supply Voltage Differential Current Output Differential Current Output Analog Common Clock Phase-Locked Loop Common Loop Filter Phase-Locked Loop Supply Voltage Clock Supply Voltage
REV.
AD9751
DEFINITIONS SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity INL) Power Supply Rejection
Linearity error defined maximum deviation actual analog output from ideal output, determined straight line drawn from zero full scale.
Differential Nonlinearity (DNL)
maximum change full-scale output supplies varied from minimum maximum specified voltages.
Settling Time
measure variation analog value, normalized full scale, associated with change digital input code.
Monotonicity
time required output reach remain within specified error band around final value, measured from start output transition.
Glitch Impulse
converter monotonic output either increases remains constant digital input increases.
Offset Error
Asymmetrical switching times cause undesired output transients that quantified glitch impulse. specified area glitch pV-s.
Spurious-Free Dynamic Range
deviation output current from ideal zero called offset error. IOUTA, output expected when inputs IOUTB, output expected when inputs
Gain Error
difference, between amplitude output signal peak spurious signal over specified bandwidth.
Total Harmonic Distortion (THD)
difference between actual ideal output span. actual span determined output when inputs minus output when inputs
Output Compliance Range
ratio first harmonic components value measured fundamental. expressed percentage decibels (dB).
Signal-to-Noise Ratio (SNR)
range allowable voltage output current-output DAC. Operation beyond maximum compliance limits cause either output stage saturation breakdown, resulting nonlinear performance.
Temperature Drift
ratio value measured output signal other spectral components below Nyquist frequency, excluding first harmonics value expressed decibels.
Adjacent Channel Power Ratio (ACPR)
ratio between measured power within channel relative adjacent channel.
Specified maximum change from ambient (25C) value value either TMIN TMAX. offset gain drift, drift reported full-scale range (FSR) degree reference drift, drift reported degree
3.0V 3.6V AVDD SEGMENTED SWITCHES LATCH DCOM CIRCUITRY MINI CIRCUITS T1-1T ROHDE SCHWARZ FSEA30 SPECTRUM ANALYZER
DVDD 1.2V REFIO RSET FSADJ
IOUTA IOUTB PLLVDD CLKVDD RESET CLKCOM DIV0 DIV1 PLLLOCK MINI CIRCUITS T1-1T
PMOS CURRENT SOURCE ARRAY
AD9751
PORT LATCH ACOM CLK+ CLK- PORT LATCH
DIGITAL DATA INPUTS TEKTRONIX DG2020 AWG2021 w/OPTION
3.0V 3.6V
LECROY 9210 PULSE GENERATOR (FOR DATA RETIMING)
ENABLED DISABLED
HP8644 SIGNAL GENERATOR
Figure Basic Characterization Test Setup
REV.
AD9751-Typical Performance Characteristics
0dBFS
0dBFS -6dBFS
-12dBFS
SFDR
SFDR
SFDR
-6dBFS -12dBFS
-12dBFS
-6dBFS 0dBFS
fOUT
fOUT
fOUT
Single-Tone SFDR fOUT fDAC MSPS; Single Port Mode
Single-Tone SFDR fOUT fDAC MSPS
Single-Tone SFDR fOUT fDAC MSPS
SFDR NEAR CARRIERS (2F1-F2, 2F2-F1)
200MSPS
SFDR NEAR CARRIERS (2F1-F2, 2F2-F1)
SFDR
SFDR
SFDR OVER NYQUIST BAND
SFDR
65MSPS 300MSPS
SFDR OVER NYQUIST BAND
fOUT fOUT
fOUT
SFDR fOUT dBFS
Two-Tone fOUT fDAC MSPS, Spacing between Tones, dBFS
Two-Tone fOUT fDAC MSPS, Spacing between Tones, dBFS
11.82MHz 130MSPS 18.18MHz 200MSPS
18.18/19.18MHz 200MSPS
40MHz 200MSPS
27.27/28.27MHz 300MSPS
SFDR
SFDR
SFDR
26MHz 130MSPS 60MHz 300MSPS
11.82/12.82MHz 130MSPS
27.27MHz 300MSPS
AOUT
AOUT
AOUT
Single-Tone SFDR AOUT fOUT fDAC
Single-Tone SFDR AOUT fOUT fDAC
Two-Tone (Third Order Products) AOUT fOUT fDAC
REV.
AD9751
26MHz/27MHz 130MSPS
18.18MHz/19.18MHz 200MSPS
SFDR
60MHz/61MHz 300MSPS
SFDR
SFDR
26MHz/27MHz 130MSPS
40MHz/41MHz 200MSPS
11.82MHz/12.82MHz 130MSPS
40MHz/41MHz 200MSPS
27.27MHz/28.27MHz 300MSPS
60MHz/61MHz 300MSPS
AOUT
AOUT
AOUT
Two-Tone Nyquist) AOUT fOUT fDAC
Two-Tone (Third Order Products) AOUT fOUT fDAC
Two-Tone Nyquist) AOUT fOUT fDAC/5
SINAD
SFDR
IOUTFS 20mA
fDAC
SFDR
40MHz 120MHz 80MHz 10MHz
IOUTFS
IOUTFS 10mA
fOUT
TEMPERATURE
SINAD fDAC fOUT MHz, dBFS
SFDR IOUTFS, fDAC MSPS dBFS
SFDR Temperature, fDAC MSPS dBFS
0.10
0.18
fDAC 300MSPS fOUT1 24MHz fOUT2 25MHz fOUT3 26MHz fOUT4 27MHz fOUT5 28MHz fOUT6 29MHz fOUT7 30MHz fOUT8 31MHz SFDR 58dBc MAGNITUDE 0dBFS
0.05
0.14
AMPLITUDE
0.10
-0.05
0.06
-0.10
0.02
-0.15 1024 CODE
-0.02 1024 CODE
-100 FREQUENCY
Typical
Typical
Eight-Tone SFDR fOUT fDAC /11, fDAC MSPS
REV.
AD9751
FUNCTIONAL DESCRIPTION REFERENCE OPERATION
Figure shows simplified block diagram AD9751. AD9751 consists PMOS current source array capable providing full-scale current, IOUTFS. array divided into equal sources that make five most significant bits (MSBs). next four bits, middle bits, consist equal current sources whose value 1/16th current source. remaining binary weighted fraction middle current sources. Implementing middle lower bits with current sources, instead R-2R ladder, enhances dynamic performance multitone amplitude signals helps maintain DAC's high output impedance (i.e., >100 kW). current sources switched other outputs (i.e., IOUTA IOUTB) PMOS differential current switches. switches based architecture that significantly improves distortion performance. This switch architecture reduces various timing errors provides matching complementary drive signals inputs differential current switches. analog digital sections AD9751 have separate power supply inputs (i.e., AVDD DVDD) that operate independently over range. digital section, which capable operating MSPS clock rate, consists edge-triggered latches segment decoding logic circuitry. analog section includes PMOS current sources, associated differential switches, 1.20 band voltage reference, reference control amplifier. full-scale output current regulated reference control amplifier from external resistor, RSET. external resistor, combination with both reference control amplifier voltage reference VREFIO, sets reference current IREF, which replicated segmented current sources with proper scaling factor. full-scale current, IOUTFS, times value IREF.
AD9751 contains internal 1.20 band reference. This easily overdriven external reference with effect performance. REFIO serves either input output, depending whether internal external reference used. internal reference, simply decouple REFIO, ACOM with capacitor. internal reference voltage will present REFIO. voltage REFIO used elsewhere circuit, external buffer amplifier with input bias current less than should used. example internal reference given Figure impedance external reference applied REFIO, shown Figure external reference provide either fixed reference voltage enhance accuracy drift performance varying reference voltage gain control. Note that compensation capacitor required since internal reference overdriven, relatively high input impedance REFIO minimizes loading external reference.
REFERENCE CONTROL AMPLIFIER
AD9751 also contains internal control amplifier that used regulate DAC's full-scale output current, IOUTFS. control amplifier configured voltage-to-current converter shown Figure that current output, IREF, determined ratio VREFIO external resistor, RSET, stated Equation IREF applied segmented current sources with proper scaling factor IOUTFS stated Equation control amplifier allows wide (10:1) adjustment span IOUTFS over range setting IREF between 62.5 wide adjustment span IOUTFS provides several application benefits. first benefit relates directly power dissipation AD9751, which proportional IOUTFS (refer Power Dissipation section). second benefit relates adjustment, which useful system gain control purposes. small signal bandwidth reference control amplifier approximately used frequency, small signal multiplying applications.
3.0V 3.6V AVDD SEGMENTED SWITCHES LATCH DCOM CIRCUITRY VDIFF VOUTA VOUT IOUTA IOUTB PLLVDD CLKVDD CLK+ CLK- CLKCOM RESET VOUT RLOAD VOUT RLOAD
DVDD 1.2V REFIO RSET FSADJ
PMOS CURRENT SOURCE ARRAY
AD9751
PORT LATCH ACOM DIGITAL DATA INPUTS DIV0 DIV1 PLLLOCK PORT LATCH
Figure Simplified Block Diagram
-10-
REV.
AD9751
OPTIONAL EXTERNAL REFERENCE BUFFER
AD9751
REFERENCE SECTION 1.2V REFIO
AVDD
PORT DATA
DATA
ADDITIONAL EXTERNAL LOAD
IREF
FSADJ
CURRENT SOURCE ARRAY
PORT
DATA
DATA DATA
Figure Internal Reference Configuration
AD9751
AVDD REFERENCE SECTION 1.2V EXTERNAL REFERENCE REFIO FSADJ CURRENT SOURCE ARRAY AVDD
IOUTA IOUTB CYCLE
Input Timing Requirements with Active, Single Clock Cycle
PORT DATA PORT DATA DATA DATA DATA
IREF
Figure External Reference Configuration
CLOCK MULTIPLIER OPERATION
Phase Locked Loop (PLL) intrinsic operation AD9751 that produces necessary internally synchronized clock edge-triggered latches, multiplexer, DAC. With PLLVDD connected supply voltage, AD9751 ACTIVE mode. Figure shows functional block diagram AD9751 clock control circuitry with active. circuitry consists phase detector, charge pump, voltage controlled oscillator (VCO), input data rate range control, clock logic circuitry, control input/outputs. logic feedback loop allows generate clock needed output latch. Figure defines input output timing AD9751 with active. Figure represents clock that generated external AD9751. input data both Ports latched same rising edge. applied single-ended signal tying CLK- midsupply applying CLK+, differential signal applied CLK+ CLK-. RESET purpose when using internal should grounded. When AD9751 ACTIVE mode, PLLLOCK output internal phase detector. When locked, lock output this mode Logic
CLKVDD (3.1V 3.5V) PLLLOCK 3.0V 3.6V
IOUTA IOUTB
DATA DATA DATA DATA
Figure Input Timing Requirements with Active, Multiple Clock Cycles
Typically, generate outputs MHz. range control used keep operating within designed range while allowing input clocks 6.25 MHz. With active, logic levels DIV0 DIV1 determine divide (prescaler) ratio range controller. Table gives frequency range input clock different states DIV0 DIV1.
Table Rates DIV0, DIV1 Levels with Active
Frequency MHz-150 MHz-100 12.5 MHz-50 6.25 MHz-25
DIV1
DIV0
Range Controller
PLLVDD
resistor capacitor connected series from PLLVDD required optimize phase noise versus settling/acquisition time characteristics PLL. obtain optimum noise distortion performance, PLLVDD should voltage level similar DVDD CLKVDD. general, best phase noise performance range control setting achieved with operating near maximum output frequency MHz.
DIFFERENTIAL SINGLE-ENDED CLK+ CLK-
PHASE DETECTOR
CHARGE PUMP
RANGE CONTROL DIV0 DIV1
INPUT LATCHES
LATCH CLKCOM
AD9751
Figure Clock Circuitry with Active
stated earlier, applications requiring input data rates below 6.25 MSPS must disable clock multiplier provide external reference clock. higher data rates however, applications already containing phase noise (i.e., jitter) reference clock that twice input data rate should consider disabling clock multiplier achieve best performance from AD9751. Note that SFDR performance AD9751 remains unaffected with without clock multiplier enabled. -11-
REV.
AD9751
effects phase noise AD9751's performance become more noticeable higher reconstructed output frequencies signal levels. Figure compares phase noise full-scale sine wave exactly fDATA/4 different data rates (thus carrier frequency) with optimum DIV1, DIV0 setting.
NOISE DENSITY dBm/Hz
TIMING WITH ACTIVE
described Figure ACTIVE mode, Port Port input latches updated rising edge CLK. same rising edge, data previously present input Port latch written output latch. output will update after short propagation delay (tPD). Following rising edge CLK, time equal half period, data Port latch will written output latch, again with corresponding change output. internal PLL, time which data Port Port input latches written latch independent duty cycle CLK. When using PLL,
-100 -110 OFF, fDATA 50MSPS FREQUENCY OFFSET fDATA 50MSPS fDATA 100MSPS fDATA 125MSPS fDATA 150MSPS
external clock operated duty cycle that meets specified input pulsewidth.
next rising edge CLK, cycle begins again with input port latches being updated output latch being updated with current data Port input latch.
DISABLED MODE
Figure Phase Noise Clock Multiplier fOUT fDATA/4 Different fDATA Settings with DIV0/DIV1 Optimized, Using FSEA30 Spectrum Analyzer,
partly function jitter generated clock circuitry. result, noise PLLVDD CLKVDD degrade output DAC. minimize this potential problem, PLLVDD CLKVDD connected DVDD using filter network similar shown Figure
FERRITE BEADS ELECT. F-22 TANT. CLKVDD CER. PLLVDD
When PLLVDD grounded, disabled. external clock must drive inputs desired output update rate. speed timing data present input Ports dependent whether AD9751 interleaving digital input data only responding data single port. Figure functional block diagram AD9751 clock control circuitry with disabled.
PLLLOCK
AD9751
CLKIN+ CLKIN- DIFFERENTIAL SINGLE-ENDED
LATCH CLOCK LOGIC INPUT LATCHES INTERNAL PLLVDD RESET DIV0 DIV1
TTL/CMOS LOGIC CIRCUITS
Figure Clock Circuitry with Disabled
CLKCOM 3.3V POWER SUPPLY
DIV0 DIV1 longer control PLL, used control input either interleaving interleaving input data. different modes states DIV0 DIV1 given Table
Table Input Mode DIV0, DIV1 Levels with Disabled
Figure Network Power Filtering
Input Mode Interleaved Noninterleaved Port Selected Port Selected Invalid
DIV1
DIV0
-12-
REV.
AD9751
INTERLEAVED MODE WITH DISABLED NONINTERLEAVED MODE WITH DISABLED
relationship between internal external clocks this mode shown Figure clock output update data rate input data rate) must applied inputs. Internal dividers then create internal clock necessary input latches. Although input latches updated rising edge delayed internal clock, setup-and-hold times given Digital Specifications table with respect rising edge external clock. With disabled, load-dependent delayed version clock present PLLLOCK pin. This signal used synchronize external data.
PORT DATA PORT EXTERNAL DELAYED INTERNAL EXTERNAL PLLLOCK DATA
data only port required, AD9751 interface operate simple double-buffered latch with interleaving. rising edge clock, input latch updated with present input data (depending state DIV0/ DIV1). next rising edge, latch updated time later, output reflects this change. Figure represents AD9751 timing this mode.
DATA PORT PORT CLOCK
DATA ENTERS INPUT LATCHES THIS EDGE
DATA
DATA PORT PORT
IOUTA IOUTB
Figure Timing Requirements, Noninterleaved Mode with Disabled
TRANSFER FUNCTION
IOUTA IOUTB
DATA
DATA
Figure Timing Requirements, Interleaved Mode with Disabled
Updates data input Ports should synchronized specific rising edge external clock that corresponds rising edge internal clock shown Figure ensure synchronization, Logic must momentarily applied RESET pin. Doing this returning RESET Logic brings clock PLLLOCK Logic next rising edge clock, clock will Logic second rising edge clock, clock (PLLLOCK) will again Logic well update data both input latches. details this given Figure
DATA ENTERS INPUT LATCHES THESE EDGES RESET
AD9751 provides complementary current outputs, IOUTA IOUTB. IOUTA provides near full-scale current output, IOUTFS, when bits high (i.e., CODE 1023) while IOUTB, complementary output, provides current. current output appearing IOUTA IOUTB function both input code IOUTFS, expressed IOUTA CODE 1024) IOUTFS IOUTB (1023 CODE 1024 IOUTFS
where CODE 1023 (i.e., decimal representation). mentioned previously, IOUTFS function reference current IREF, which nominally reference voltage, VREFIO, external resistor RSET. expressed IOUTFS where VREFIO RSET current outputs typically drive resistive load directly transformer. dc-coupling required, IOUTA IOUTB should directly connected matching resistive loads, RLOAD, that tied analog common, ACOM. Note that RLOAD represent equivalent load resistance seen IOUTA IOUTB would case doubly terminated cable. single-ended voltage output appearing IOUTA IOUTB nodes simply: VOUTA IOUTA RLOAD VOUTB IOUTB RLOAD Note that full-scale value VOUTA VOUTB should exceed specified output compliance range maintain specified distortion linearity performance. VDIFF IOUTA IOUTB RLOAD
PLLLOCK
EXTERNAL CLOCK
1.2ns 0.2ns
Figure Reset Function Timing with Disabled
proper synchronization, sufficient delay must present between time RESET goes rising edge clock. RESET going must occur either least before rising edge clock afterwards. former case, immediately occurring rising edge will cause PLLLOCK low. latter case, next rising edge will toggle PLLLOCK.
Substituting values IOUTA, IOUTB, IREF, VDIFF expressed
VDIFF CODE 1023) 1024
(RLOAD
RSET VREFIO
REV.
-13-
AD9751
Equations highlight some advantages operating AD9751 differentially. First, differential operation helps cancel common-mode error sources associated with IOUTA IOUTB such noise, distortion, offsets. Second, differential code-dependent current subsequent voltage, VDIFF, twice value single-ended voltage output (i.e., VOUTA VOUTB), thus providing twice signal power load. Note that gain drift temperature performance singleended (VOUTA VOUTB) differential output (VDIFF) AD9751 enhanced selecting temperature tracking resistors RLOAD RSET their ratiometric relationship, shown Equation
ANALOG OUTPUTS
optimum performance. negative output compliance range -1.0 breakdown limits CMOS process. Operation beyond this maximum limit result breakdown output stage affect reliability AD9751. positive output compliance range slightly dependent full-scale output current, IOUTFS. degrades slightly from nominal 1.25 IOUTFS 1.00 IOUTFS optimum distortion performance singleended differential output achieved when maximum full-scale signal IOUTA IOUTB does exceed Applications requiring AD9751's output (i.e., VOUTA and/or VOUTB) extend output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect AD9751's linearity performance subsequently degrade distortion performance.
DIGITAL INPUTS
AD9751 produces complementary current outputs, IOUTA IOUTB, that configured single-ended differential operation. IOUTA IOUTB converted into complementary single-ended voltage outputs, VOUTA VOUTB, load resistor, RLOAD, described Equations through Transfer Function section. differential voltage, VDIFF, existing between VOUTA VOUTB also converted single-ended voltage transformer differential amplifier configuration. performance AD9751 optimum specified using differential transformer-coupled output which voltage swing IOUTA IOUTB limited single-ended unipolar output desirable, IOUTA should selected output, with IOUTB grounded. distortion noise performance AD9751 enhanced when configured differential operation. common-mode error sources both IOUTA IOUTB significantly reduced common-mode rejection transformer differential amplifier. These common-mode error sources include even-order distortion products noise. enhancement distortion performance becomes more significant frequency content reconstructed waveform increases. This first order cancellation various dynamic common-mode distortion mechanisms, digital feedthrough, noise. Performing differential-to-single-ended conversion transformer also provides ability deliver twice reconstructed signal power load (i.e., assuming source termination). Since output currents IOUTA IOUTB complementary, they become additive when processed differentially. properly selected transformer will allow AD9751 provide required power voltage levels different loads. Refer Applying AD9751 section examples various output configurations. output impedance IOUTA IOUTB determined equivalent parallel combination PMOS switches associated with current sources typically parallel with also slightly dependent output voltage (i.e., VOUTA VOUTB) nature PMOS device. result, maintaining IOUTA and/or IOUTB virtual ground configuration will result optimum linearity. Note that INL/DNL specifications AD9751 measured with IOUTA IOUTB maintained virtual ground amp. IOUTA IOUTB also have negative positive voltage compliance range that must adhered order achieve
AD9751's digital input consists channels data input pins each pair differential clock input pins. 10-bit parallel data inputs follow standard straight binary coding where most significant (MSB) least significant (LSB). IOUTA produces full-scale output current when data bits Logic IOUTB produces complementary output with full-scale current split between outputs function input code. digital interface implemented using edge-triggered master slave latch. With active disabled, output updated twice every input latch rising edge, shown Figures AD9751 designed support input data rate high MSPS, giving output update rate MSPS. setup-and-hold times also varied within clock cycle long specified minimum times met. Best performance typically achieved when input data transitions falling edge duty cycle clock. digital inputs CMOS compatible with logic thresholds, VTHRESHOLD, approximately half digital positive supply (DVDD) VTHRESHOLD DVDD (±20%)
internal digital circuitry AD9751 capable operating over digital supply range result, digital inputs also accommodate levels when DVDD accommodate maximum high level voltage drivers VOH(MAX). DVDD typically ensures proper compatibility with most logic families. Figure shows equivalent digital input circuit data clock inputs.
DVDD
DIGITAL INPUT
Figure Equivalent Digital Input
AD9751 features flexible differential clock input operating from separate supplies (i.e., CLKVDD, CLKCOM) achieve optimum jitter performance. clock inputs, CLK+ REV.
-14-
AD9751
CLK-, driven from single-ended differential clock source. single-ended operation, CLK+ should driven logic source while CLK- should threshold voltage logic source. This done resistor divider/ capacitor network shown Figure 15a. differential operation, both CLK+ CLK- should biased CLKVDD/2 resistor divider network shown Figure 15b. Because output AD9751 updated MSPS, quality clock data input signals important achieving optimum performance. drivers digital data interface circuitry should specified meet minimum setup-and-hold times AD9751 well required min/max input logic level thresholds. Digital signal paths should kept short lengths matched avoid propagation delay mismatch. insertion value resistor network (i.e., between AD9751 digital inputs driver outputs helpful reducing overshooting ringing digital inputs that contribute data feedthrough. longer lengths high data update rates, strip line techniques with proper termination resistors should considered maintain "clean" digital inputs. external clock driver circuitry should provide AD9751 with jitter clock input, meeting min/max logic levels while providing fast edges. Fast clock edges help minimize jitter that manifests itself phase noise reconstructed waveform. Thus, clock input should driven fastest logic family suitable application. clock input could also driven sine wave that centered around digital threshold (i.e., DVDD/2) meets min/max logic threshold. This typically results slight degradation phase noise, which becomes more noticeable higher sampling rates output frequencies. Also, higher sampling rates, tolerance digital logic threshold should considered since affects effective clock duty cycle and, subsequently, cuts into required data setup-andhold times.
RSERIES
INPUT CLOCK DATA TIMING RELATIONSHIP
dependent relationship between position clock edges point time which input data changes. AD9751 rising edge triggered, exhibits sensitivity when data transition close this edge. general, goal when applying AD9751 make data transition close falling clock edge. This becomes more important sample rate increases. Figure shows relationship clock placement with different sample rates. Note that setup hold times implied Figure appear violate maximums stated Digital Specifications table. variation Figure skew present between data bits inherent digital data generator used perform these tests. Figure presented show effects violating setup hold times, show insensitivity AD9751 clock placement when data transitions fall outside so-called "bad window." setup-and-hold times stated Digital Specifications table were measured bitby-bit basis, therefore eliminating skew present digital data generator. higher data rates, becomes very important account skew input digital data when defining timing specifications.
AD9751
CLK+ CLKVDD
TIME DATA TRANSITION RELATIVE PLACEMENT RISING EDGE (ns), fOUT 10MHz, fDAC 300MHz
Figure Time Data Transition Relative Clock Rising Edge
POWER DISSIPATION
VTHRESHOLD
CLK- CLKCOM
Figure 15a. Single-Ended Clock Interface
CLKVDD CLK- CLKCOM
AD9751
CLK+
power dissipation, AD9751 dependent several factors that include: power supply voltages (AVDD DVDD), full-scale current output IOUTFS, update rate fCLOCK, reconstructed digital input waveform. power dissipation directly proportional analog supply current, IAVDD, digital supply current, IDVDD. IAVDD directly proportional IOUTFS, shown Figure insensitive fCLOCK. Conversely, IDVDD dependent both digital input waveform, fCLOCK, digital supply DVDD. Figure shows IDVDD function ratio (fOUT/ fDAC) various update rates. addition, Figure shows effect speed fDAC PLLVDD current, given divider ratio.
Figure 15b. Differential Clock Interface
REV.
-15-
AD9751
12.5 IOUTFS 17.5
APPLYING AD9751
OUTPUT CONFIGURATIONS
following sections illustrate some typical output configurations AD9751. Unless otherwise noted, assumed that IOUTFS nominal applications requiring optimum dynamic performance, differential output configuration suggested. differential output configuration consist either transformer differential configuration. transformer configuration provides optimum high frequency performance recommended application allowing ac-coupling. differential configuration suitable applications requiring dc-coupling, bipolar output, signal gain, and/or level shifting within bandwidth chosen amp.
Figure IAVDD IOUTFS
IAVDD
IDVDD
300MSPS
single-ended output suitable applications requiring unipolar voltage output. positive unipolar output voltage will result IOUTA and/or IOUTB connected appropriately sized load resistor, RLOAD, referred ACOM. This configuration more suitable single-supply system requiring dc-coupled, ground referred output voltage. Alternatively, amplifier could configured converter, thus converting IOUTA IOUTB into negative unipolar voltage. This configuration provides best linearity, since IOUTA IOUTB maintained virtual ground. Note that IOUTA provides slightly better performance than IOUTB.
DIFFERENTIAL COUPLING USING TRANSFORMER
200MSPS 25MSPS 0.001 100MSPS 50MSPS
0.01 RATIO fOUT/f
Figure IDVDD fOUT/fDAC Ratio
SETTING PLL_VDD fDAC SETTING SETTING SETTING
transformer used perform differential-tosingle-ended signal conversion shown Figure differentially coupled transformer output provides optimum distortion performance output signals whose spectral content lies within transformer's pass band. transformer such Mini-Circuits T1-1T provides excellent rejection common-mode distortion (i.e., even-order harmonics) noise over wide frequency range. When IOUTA IOUTB terminated ground with this configuration provides power load secondary with fullscale current transformer, such Coilcraft WB2040-PC, also used configuration which IOUTA IOUTB terminated ground with This configuration improves load matching increases power into load secondary. Transformers with different impedance ratios also used impedance matching purposes. Note that transformer provides coupling only.
AD9751
IOUTA MINI-CIRCUITS T1-1T RLOAD IOUTB
Figure Differential Output Using Transformer
Figure PLLVDD fDAC
-16-
REV.
AD9751
center primary side transformer must connected ACOM provide necessary current path both IOUTA IOUTB. complementary voltages appearing IOUTA IOUTB (i.e., VOUTA VOUTB) swing symmetrically around ACOM should maintained with specified output compliance range AD9751. differential resistor, RDIFF, inserted into applications where output transformer connected load, RLOAD, passive reconstruction filter cable. RDIFF determined transformer's impedance ratio provides proper source termination that results VSWR.
DIFFERENTIAL COUPLING USING
AD9751
IOUTA
IOUTB COPT
AD8041
AVDD
Figure Single-Supply Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
also used perform differential-to-singleended conversion shown Figure AD9751 configured with equal load resistors, RLOAD, differential voltage developed across IOUTA OUTB converted single-ended signal differential configuration. optional capacitor installed across IOUTA IOUTB, forming real pole low-pass filter. addition this capacitor also enhances amp's distortion performance preventing DAC's high slewing output from overloading amp's input.
Figure shows AD9751 configured provide unipolar output range approximately doubly-terminated cable, since nominal full-scale current, IOUTFS, flows through equivalent RLOAD this case, RLOAD represents equivalent load resistance seen IOUTA IOUTB. unused output (IOUTA IOUTB) connected ACOM directly matching RLOAD. Different values IOUTFS RLOAD selected long positive compliance range adhered additional consideration this mode integral nonlinearity (INL) discussed Analog Outputs section. optimum performance, single-ended, buffered voltage output configuration suggested.
AD9751
IOUTFS 20mA
AD9751
IOUTA
VOUTA 0.5V
IOUTB COPT
AD8047
IOUTA
IOUTB
Figure Differential Coupling Using
Figure Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
common-mode rejection this configuration typically
determined resistor matching. this circuit, differential circuit using AD8047 configured provide some additional signal gain. must operate from dual supply since output approximately high speed amplifier capable preserving differential performance AD9751, while meeting other systemlevel objectives (i.e., cost, power), should selected. amp's differential gain, gain setting resistor values, fullscale output swing capabilities should considered when optimizing this circuit. differential circuit shown Figure provides necessary level-shifting required single supply system. this case, AVDD, which positive analog supply both AD9751 amp, also used level-shift differential output AD9751 midsupply (i.e., AVDD/2). AD8041 suitable this application.
Figure shows buffered single-ended output configuration which performs conversion AD9751 output current. maintains IOUTA IOUTB) virtual ground, thus minimizing nonlinear output impedance effect DAC's performance discussed Analog Output section. Although this single-ended configuration typically provides best linearity performance, distortion performance higher update rates limited amp's slewing capabilities. provides negative unipolar output voltage full-scale output voltage simply product IOUTFS. full-scale output should within amp's voltage output swing capabilities scaling IOUTFS and/or RFB. improvement distortion performance result with reduced IOUTFS, since signal current will required sink will subsequently reduced.
REV.
-17-
AD9751
COPT
AD9751
IOUTA IOUTB VOUT IOUTFS
Figure Unipolar Buffered Voltage Output
POWER GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
Note that units Figure given units (amps out/ volts in). Noise analog power supply effect modulating internal switches, therefore output current. voltage noise AVDD thus added nonlinear manner desired IOUT. relative different size these switches, PSRR very code-dependent. This produce mixing effect that modulate frequency power supply noise higher frequencies. Worst-case PSRR either differential outputs occurs when full-scale current directed toward that output. result, PSRR measurement Figure represents worst-case condition which digital inputs remain static full-scale output current directed output being measured. example serves illustrate effect supply noise analog supply. Suppose switching regulator with switching frequency produces noise and, sake simplicity (i.e., ignore harmonics), this noise concentrated kHz. calculate much this undesired noise will appear current noise superimposed DAC's full-scale current, IOUTFS, must determine PSRR using Figure kHz. calculate PSRR given RLOAD, such that units PSRR converted from V/V, adjust curve Figure scaling factor (RLOAD). instance, RLOAD PSRR reduced i.e., PSRR kHz, which Figure becomes VOUT/VIN. Proper grounding decoupling should primary objective high speed, high resolution system. AD9751 features separate analog digital supply ground pins optimize management analog digital ground currents system. general, AVDD, analog supply, should decoupled ACOM, analog common, close chip physically possible. Similarly, DVDD, digital supply, should decoupled DCOM close chip physically possible. those applications that require single supply both analog digital supplies, clean analog supply generated using circuit shown Figure circuit consists differential filter with separate power supply return lines. Lower noise attained using type electrolytic tantalum capacitors.
FERRITE BEADS AVDD ELECT. F-22 TANT. CER. ACOM
Many applications seek high speed high performance under less than ideal operating conditions. these applications, implementation construction printed circuit board important circuit design. Proper techniques must used device selection, placement, routing, well power supply bypassing grounding, ensure optimum performance. Figures illustrate recommended printed circuit board ground, power, signal plane layouts that implemented AD9751 evaluation board. factor that measurably affect system performance ability output reject variations noise superimposed analog digital power distribution. This referred Power Supply Rejection Ratio. variations power supply, resulting performance directly corresponds gain error associated with DAC's full-scale current, IOUTFS. noise supplies common applications where power distribution generated switching power supply. Typically, switching power supply noise occurs over spectrum from tens several MHz. PSRR versus frequency AD9751 AVDD supply over this frequency range shown Figure
PSRR
FREQUENCY
3.3V POWER SUPPLY TTL/CMOS LOGIC CIRCUITS
Figure Power Supply Rejection Ratio
Figure Differential Filter Single Application
-18-
REV.
AD9751
APPLICATIONS QAM/PSK Synthesis
Quadrature modulation (QAM PSK) consists baseband (Pulse Amplitude Modulated) data channels. Both channels modulated common frequency carrier. However, carriers each channel phase-shifted from each other. This orthogonality allows twice spectral efficiency (data given bandwidth) digital data transmitted Receivers designed selectively choose phase" "quadrature" carriers, then recombine data. recombination data mapped points representing digital words two-dimensional constellation shown Figure Each point, symbol, represents transmission multiple bits symbol period.
figure merit wideband signal synthesis ratio signal power transmitted band power adjacent channel. Figure adjacent channel power ratio (ACPR) output AD9751 measured limitation making measurement this type often noise inherent creating digital data record using computer tools. find much this limiting perceived performance, signal amplitude reduced, shown Figure noise contributed will remain constant signal amplitude reduced. When signal amplitude reduced level where noise floor drops below that spectrum analyzer, ACPR will fall same rate that signal level being reduced. Under conditions measured Figure this point occurs Figure dBFS. This shows that data record actually degrading measured ACPR
0100
0101
0001
0000
0110
0111
0011
0010
1110 1111 1011 1010
ACPR
1100
1101
1001
1000
Figure Constellation, Gray Coded (Two 4-Level Signals with Orthogonal Carriers)
Typically, data channels quadrature-modulated digital domain. high data rate AD9751 allows extremely wideband (>10 MHz) quadrature carriers synthesized. Figure shows example MSymbol/S signal, oversampled eight data rate MSPS; modulated onto carrier reconstructed using AD9751. power reconstructed signal measured -12.08 dBm. first adjacent band, power -73.67 dBm, while second adjacent band power -76.91 dBm.
MARKER [T1] -74.49dBm 9.71442886MHz
AMPLITUDE dBFS
Figure ACPR Amplitude Carrier
5kHz 50kHz 12.5 UNIT [T1]
single-channel active mixer such Analog Devices AD8343 then used transmit frequency. Figure shows applications circuit using AD9751 AD8343. AD8343 capable mixing carriers from GHz. Figure shows result mixing signal Figure carrier frequency MHz. ACPR measured output AD8343 shown Figure
-74.49bBM, +9.71442886MHz -73.67dBm -76.91dBm -12.08dBm
-100 -110
-120
-130 START 100kHz 12.49MHz/ STOP 125MHz COMMENT MSYMBOL, QAM, CARRIER 25MHz
Figure Reconstructing Raised Cosine Signal
REV.
-19-
AD9751
DVDD AVDD CLK+ CLK- PLLLOCK
PLL/DIVIDER
PORT DATA INPUT
INPUT LATCHES
LATCHES
IOUTA IOUTB LOIP AD8343 ACTIVE MIXER LOINPUT M/A-COM ETC-1-1-13 WIDEBAND BALUM INPP OUTP INPM LOIM OU
PORT DATA INPUT FSADJ RSET2 1.9k
INPUT LATCHES
AD9751
REFIO ACOM1 ACOM DCOM
Figure Transmitter Architecture Using AD9751 AD8343 Active Mixer
MARKER [T2] -100.59dBm 859.91983968MHz
10kHz 10kHz
UNIT
-100.59bBm, +859.91983968MHz -64.88dBm -62.26dBm -7.38dBm 33.48dB [T2] -49.91983968MHz 33.10dB [T2] -49.91983968MHz [T2]
energy/symbol-to- noise (E/NO) ratio 27.8 loss interferers inherent wireless path, this signal-tonoise ratio must realized receiver achieve given error rate.
-100 -110
Distortion effects much more difficult determine accurately. Most often simulation, energies strongest distortion components root-sum-squared with noise, result treated were noise. That being said, using example above with 1e-6, E/NO ratio much greater than worst-case SFDR, noise will dominate calculation. AD9751 worst-case in-band SFDR upper frequency spectrum (see TPCs When used synthesize high level signals described above, noise, opposed distortion, will dominate performance these applications.
11MHz/
-120 CENTER 860MHz SPAN 110MHz
COMMENT MSYMBOL, CARRIER 825MHz
Figure Signal Figure Mixed Carrier Frequency
Effects Noise Distortion Error Rate (BER)
Textbook analysis Error Rate (BER) performance generally stated terms (energy watts-per-symbol watts-per-bit) (spectral noise density watts/Hz). signals, this performance shown graphically Figure represents number levels each quadrature signal (i.e., QAM, QAM). Figure implies grey coding constellation, well matched filters receiver, which typical. horizontal axis Figure converted units energy/ symbol adding horizontal axis number bits desired curve. instance, achieve 1e-6 with QAM, energy necessary. calculate energy symbol, log(6) Therefore with 1e-6 (assuming source channel coding) theoretically achieved with
SYMBOL ERROR PROBABILITY
1E-1
1E-2 1E-3
1E-4
1E-5
1E-6 SNR/BIT
Figure Probability Symbol Error
-20-
REV.
AD9751
Pseudo Zero Stuffing/IF Mode
excellent dynamic range AD9751 allows applications where synthesis multiple carriers desired. addition, AD9751 used pseudo zero stuffing mode, which improves dynamic range frequencies. this mode, data from input channels interleaved DAC, which running twice speed either input ports. However, data Port held constant midscale. effect this shown Figure signal image, with respect input data rate, fundamental. Normally, sinx/x response attenuates this image. Zero stuffing improves passband flatness that image amplitude closer that fundamental signal. Zero stuffing especially useful technique synthesis signals.
output differentially using transformer, recommended that either Mini-Circuits T1-1T (through-hole) Coilcraft TTWB-1-B (SMT) placed position evaluation board. evaluate output either single-ended direct-coupled, remove transformer bridge either BL2. digital data AD9751 comes from ribbon cables that interface 40-lead connectors Proper termination voltage scaling accomplished installing resistor pack networks RN1-RN12. RN1, RN4, RN7, RN10 resistor packs should installed they help reduce digital edge rates therefore peak current inputs. single-ended clock applied setting DIFF labeled jumpers input clock directed CLK+/CLK- inputs AD9751 either single-ended differential manner. differentially applied clock desired, Mini-Circuits T1-1T transformer should used position Note that with single-ended square wave clock input, must removed. clock also applied ribbon cable Port (P1), inserting EDGE jumper (JP1), this clock will applied CLK+ input AD9751. should position this application bias CLK- half supply voltage. AD9751's clock multiplier enabled inserting position. described Typical Performance Characteristics Functional Description sections, with enabled, clock half output data rate should applied described last paragraph. takes care internal frequency multiplication internal timing requirements. this application, PLLLOCK output indicates when lock achieved PLL. With enabled, DIV0 DIV1 jumpers (JP8 JP9) provide divider ratio described Table disabled when setting. this mode, clock speed output data rate must applied clock inputs. Internally, clock divided data synchronization, clock provided PLLLOCK this application. Care should taken read timing requirements described earlier optimum performance. With disabled, DIV0 DIV1 jumpers define mode (interleaved, noninterleaved) described Table
EFFECT SINX/X ROLL-OFF
AMPLITUDE IMAGE USING ZERO STUFFING
AMPLITUDE IMAGE WITHOUT ZERO STUFFING
FREQUENCY Normalized Input Data Rate
Figure Effects Pseudo Zero Stuffing Spectrum AD9751
EVALUATION BOARD
AD9751-EB evaluation board AD9751 TxDAC. Careful attention layout circuit design, combined with prototyping area, allows user easily effectively evaluate AD9751 different modes operation. Referring Figures AD9751's performance evaluated differentially single-ended either using transformer directly coupling output. evaluate
REV.
-21-
AD9751
VALUE
VALUE
VALUE
1B13 1B12 1B11 1B10 1B09 1B08 1B07 1B06
P1B13 P1B12 P1B11 P1B10 P1B09 P1B08 P1B07 P1B06
1B13 1B12 1B11 1B10 1B09 1B08 1B07 1B06
OUT16 DVDD PLANE
EDGE
DGND: 3,4,5 CLK- P1B13 P1B12 P1B11 P1B10 P1B09 P1B08 P1B07 P1B06 P1B05 P1B04 P1B03 P1B02 P1B01 P1B00 DVDD PLANE CLK+ RESET
RESET
VALUE
VALUE
VALUE
PLLVDD PLANE NOTE: SHIELD AROUND CONNECTED PLLVDD PLANE
1B05 1B04 1B03 1B02 1B01 1B00 1O17 1O15 1O16
P1B05 P1B04 P1B03 P1B02 P1B01 P1B00 OUT15 OUT16
1B05 1B04 1B03 1B02 1B01 1B00 1O15 JP10
CLKVDD
AD9751/53/55
AVDD PLANE 10pF 10pF
1O16
1O17 VALUE
VALUE 2B13 2B12 2B11 2B10 2B09 2B08 2B07 2B06
VALUE
P2B13 P2B12 P2B11 P2B10 P2B09 P2B08 P2B07 P2B06
2B13 2B12 2B11 2B10 2B09 2B08 2B07 2B06
P2B13 P2B12 P2B11 P2B10 P2B09 P2B08 P2B07 P2B06 P2B05 P2B04 P2B03 P2B02 P2B01 P2B00
IOUT
FSADJ
1.91k
RN10 VALUE 2B05 2B04 2B03 2B02 2B01 2B00
RN11 VALUE
RN12 VALUE
P2B05 P2B04 P2B03 P2B02 P2B01 P2B00
2B05 2B04 2B03 2B02 2B01 2B00 2OUT15 2OUT16
NOTES DIGITAL INPUTS FROM RN1-RN12 MUST EQUAL LENGTH. DECOUPLING CAPS LOCATED CLOSE POSSIBLE DUT, PREFERABLY UNDER BOTTOM SIGNAL LAYER. CONNECT GNDS UNDER USING BOTTOM SIGNAL LAYER. CREATE PLANE CAPACITOR WITH 0.007" DIELECTRIC BETWEEN LAYERS
REFIO
DIV1
AVDD_PLANE
DIV0
TP10
TP12
P2OUT15 P2OUT16
Figure Evaluation Board Circuitry
-22-
REV.
AD9751
OUT15
EDGE
CLK+
CKLVDD
PGND:
CLK-
DVDD
FBEAD
TP13
DVDD PLANE
BYPASS CAPS
PINS
PINS
DGND
TP14
DVDD PLANE
AVDD
FBEAD
TP15
AVDD PLANE
PINS
AVDD PLANE
AGND
TP16
CLKVDD
FBEAD
TP17
CLKGND
TP11
CLKVDD
PLLVDD PLANE
PINS
CLKVDD
Figure Evaluation Board Clock Circuitry
REV.
-23-
AD9751
Figure Evaluation Board, Assembly-Top
Figure Evaluation Board, Assembly-Bottom
-24-
REV.
AD9751
Figure Evaluation Board, Layer
Figure Evaluation Board, Layer Ground Plane
REV.
-25-
AD9751
Figure Evaluation Board, Layer Power Plane
Figure Evaluation Board, Bottom Layer
-26-
REV.
AD9751
OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] Thick (ST-48)
Dimensions shown millimeters
1.60 0.75 0.60 0.45
INDICATOR
9.00
1.45 1.40 1.35
0.20 0.09
SEATING PLANE
VIEW
(PINS DOWN)
7.00
0.15 0.05
SEATING PLANE
0.08 COPLANARITY
VIEW
VIEW
ROTATED
0.50
0.27 0.22 0.17
COMPLIANT JEDEC STANDARDS MS-026BBC
REV.
-27-
AD9751 Revision History
Location 1/03-Data Sheet changed from REV. REV. Page
Changes Figure Changes Figure Updated OUTLINE DIMENSIONS
3/02-Data Sheet changed from REV. REV.
C02250-0-1/03(B) PRINTED U.S.A.
Changes PRODUCT DESCRIPTION Changes PRODUCT HIGHLIGHTS Changes DIGITAL SPECIFICATIONS Changes Figure Edits Changes FUNCTIONAL DESCRIPTION Section Changes Figure Figure replaced with Figure Changes Figure Edits Figure Change Figure Change ANALOG OUTPUTS Section Changes DIGITAL INPUTS Section
-28-
REV.
Other recent searches
PSD935G2 - PSD935G2 PSD935G2 Datasheet
MCM69F536C - MCM69F536C MCM69F536C Datasheet
LUGY92M - LUGY92M LUGY92M Datasheet
FQB7N65C - FQB7N65C FQB7N65C Datasheet
DS9072 - DS9072 DS9072 Datasheet
DS9075 - DS9075 DS9075 Datasheet
DS9076 - DS9076 DS9076 Datasheet
BU4S71G2 - BU4S71G2 BU4S71G2 Datasheet
BF994S - BF994S BF994S Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
