12-Bit, MSPS/105 MSPS Converter AD9432 ENCODE ENCODE PIPELINE OUT
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FEATURES On-Chip Reference Track/Hold On-Chip Input Buffer Typical Power Dissipation MSPS Analog Bandwidth MSPS SFDR MSPS Differential Analog Input Range Single Supply Operation CMOS/TTL Outputs Two's Complement Output Format APPLICATIONS Communications Basestations `Zero-IF' Subsystems Wireless Local Loop (WLL) Local Multipoint Distribution Service (LMDS) HDTV Broadcast Cameras Film Scanners
12-Bit, MSPS/105 MSPS Converter AD9432
ENCODE ENCODE PIPELINE OUTPUT STAGING D11-D0
TIMING
AD9432
VREFOUT VREFIN
GENERAL INTRODUCTION
AD9432 12-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuit optimized high-speed conversion ease use. product operates MSPS conversion rate with outstanding dynamic performance over full operating range. requires only single power supply encode clock full-performance operation.
external reference driver components required many applications. digital outputs TTL/CMOS compatible separate output power supply supports interfacing with logic. encode input supports either differential single-ended TTL/CMOS-compatible. Fabricated advanced BiCMOS process, AD9432 available 52-lead plastic quad flatpack package (LQFP) specified over industrial temperature range (-40°C +85°C).
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
AD9432-SPECIFICATIONS
Parameter RESOLUTION ACCURACY Differential Nonlinearity Integral Nonlinearity Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (AIN-AIN) Common-Mode Voltage Input Offset Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power ANALOG REFERENCE Output Voltage Tempco Input Bias Current SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 Output Rise Time (tR)2 Output Fall Time (tF) Out-of-Range Recovery Time Transient Response Time Latency DIGITAL INPUTS Encode Input Common Mode Differential Input (ENC-ENC) Single-Ended Logic Voltage Logic Voltage Input Resistance Input Capacitance DIGITAL OUTPUTS Logic Voltage (VDD Logic Voltage (VDD Output Coding POWER SUPPLY Power Dissipation3 Power Supply Rejection Ratio (PSRR) IVCC IVDD 25°C Full 25°C Full Full 25°C Full Full Full Full Full 25°C 25°C Full Full Full Full Full 25°C 25°C 25°C 25°C Full Full Full Full 25°C 25°C Full Full Full Full Full Full 25°C Full Full Temp
(VDD external reference; differential encode input, unless otherwise noted.)
Test Level AD9432BST/BSQ-80 -0.75 0.25 -1.0 -1.0 -1.5 Guaranteed +0.75 +1.0 +1.0 +1.5 -0.75 -1.0 -1.0 -1.5 AD9432BST/BSQ-105 0.25 Guaranteed +0.75 +1.0 +1.0 +1.5
Unit Bits ppm/°C ppm/°C MSPS MSPS Cycles
0.25
0.25
0.05 0.05 Two's Complement +0.5 1000 12.2
0.05 0.05 Two's Complement +0.5 12.5 1100
Full 25°C Full Full
mV/V
REV.
AD9432
Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) (Without Harmonics) 10.3 Signal-to-Noise Ratio (SINAD) (With Harmonics) 10.3 Effective Number Bits Second Third Harmonic Distortion Worst Harmonic Spur (Excluding Second Third) Two-Tone Intermod Distortion (IMD) fIN1 29.3 MHz; fIN2 30.3 fIN1 70.3 MHz; fIN2 71.3
Temp
Test Level
AD9432BST/BSQ-80
AD9432BST/BSQ-105
Unit
25°C 25°C 25°C 25°C
65.5
67.5 67.2 67.0 66.1
65.5
67.5 67.2 67.0 66.1
25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C
64.5
67.2 66.9 66.7 65.8 11.0 10.9 10.9 10.7
67.2 66.9 66.7 65.8 11.0 10.9 10.9 10.7
Bits Bits Bits Bits
25°C 25°C 25°C 25°C 25°C 25°C
NOTES Gain error gain temperature coefficients based only (with fixed external reference differential analog input). measured from transition points ENCODE input 50%/50% levels digital outputs swing. digital output load during test exceed load current Rise fall times measured from 90%. Power dissipation measured with encode rated speed analog input. (Outputs Static, SNR/harmonics based analog input voltage -0.5 dBFS referenced full-scale input range. Specifications subject change without notice.
REV.
AD9432
ABSOLUTE MAXIMUM RATINGS* THERMAL CHARACTERISTICS
Analog Inputs -0.5 Digital Inputs -0.5 VREFIN -0.5 Digital Output Current Operating Temperature -55°C +125°C Storage Temperature -65°C +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions outside those indicated operation sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
52-Lead Plastic LQFP (ST-52) 50°C/W, Airflow 52-lead PowerQuad® LQFP (SQ-52) 25°C/W, Soldered Exposed Heat Sink, Airflow 33°C/W, Unsoldered Exposed Heat Sink, Airflow 2°C/W, Bottom package (Exposed Heat Sink) Simulated Typical performance 4-layer JEDEC board, horizontal orientation.
ORDERING GUIDE Model AD9432BSQ -80, -105 Temperature Ranges -40°C +85°C Package Descriptions Package Option
EXPLANATION TEST LEVELS Test Level
100% production tested. 100% production tested 25°C sample tested specified temperatures.
AD9432BST -40°C +85°C -80, -105 AD9432/PCB 25°C
52-Lead Thermally SQ-52 Enhanced Plastic Quad Flatpack 52-Lead Plastic Quad ST-52 Flatpack (LQFP) Evaluation Board
Sample tested only. Parameter guaranteed design characterization testing. Parameter typical value only. 100% production tested 25°C; guaranteed design characterization testing industrial temperature range.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9432 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
PowerQuad registered trademark AMkor Technology, Inc.
REV.
AD9432
CONFIGURATION
VREFOUT VREFIN
DGND (LSB)
ENCODE ENCODE DGND
IDENTIFIER
AD9432
VIEW (Not Scale)
(MSB)
DGND
DGND
FUNCTION DESCRIPTIONS Number (AD9432BST) 15-20, 25-30 DEFINITION SPECIFICATIONS Mnemonic ENCODE ENCODE D11-D6, D5-D0 DGND VREFIN VREFOUT Function Analog Ground Analog Supply Encode Clock ADC-Complementary Encode Clock ADC-True (ADC samples rising edge ENCODE) Range Output Digital Output Digital Output Ground Digital Output Power Supply (2.7 Connect Reference Input (2.5 Typical); Bypass with Ground. Internal Reference Output (2.5 Typical) Analog Input-True Analog Input-Complementary Minimum Conversion Rate
Analog Bandwidth (Small Signal) analog input frequency which spectral power fundamental frequency determined analysis) reduced Aperture Delay delay between differential crossing ENCODE ENCODE instant which analog input sampled.
Aperture Uncertainty (Jitter)
encode rate which lowest analog signal frequency drops more than below guaranteed limit.
Maximum Conversion Rate
encode rate which parametric testing performed.
Output Propagation Delay
delay between differential crossing ENCODE ENCODE time when output data bits within valid logic levels.
Power Supply Rejection Ratio
sample-to-sample variation aperture delay.
Differential Nonlinearity
deviation code from ideal step.
Encode Pulsewidth/Duty Cycle
ratio change input offset voltage change power supply voltage.
Signal-to-Noise Plus Distortion (SINAD)
Pulsewidth high minimum amount time that ENCODE pulse should left Logic state achieve rated performance; pulsewidth minimum time ENCODE pulse should left state. given clock rate, these specs define acceptable Encode duty cycle.
Integral Nonlinearity
ratio signal amplitude (set below full scale) value other spectral components, including harmonics excluding
Signal-to-Noise Ratio (SNR)
deviation transfer function from reference line measured fractions using "best straight line" determined least square curve fit. REV.
ratio signal amplitude (set below full scale) value other spectral components, excluding first five harmonics
AD9432
Spurious-Free Dynamic Range (SFDR) Two-Tone SFDR
ratio signal amplitude value peak spurious spectral component. peak spurious component harmonic. reported (i.e., degrades signal level lowered), dBFS (always related back converter full scale).
Two-Tone Intermodulation Distortion Rejection
ratio value either input tone value peak spurious component. peak spurious component product. reported (i.e., degrades signal level lowered), dBFS (always related back converter full scale).
Worst Harmonic
ratio value either input tone value worst third order intermodulation product; reported dBc.
ratio signal amplitude value worst harmonic component, reported dBc.
SAMPLE
SAMPLE
SAMPLE N+10
SAMPLE N+11
ENCODE ENCODE
SAMPLE
SAMPLE
D11-D0 DATA N-11 DATA N-10 DATA DATA
DATA
Figure Timing Diagram
ENCODE
VREFIN
ENCODE
Figure Equivalent Voltage Reference Input Circuit
Figure Equivalent Encode Input Circuit
VREFOUT DIGITAL OUTPUT
VREF OUTPUT
DIGITAL OUTPUT
Figure Equivalent Voltage Reference Output Circuit
Figure Equivalent Digital Output Circuit
ANALOG INPUT
Figure Equivalent Analog Input Circuit
REV.
Typical Performance Characteristics-AD9432
10.3MHz SFDR SINAD
ENCODE MSPS
INPUT FREQUENCY (-0.5dBFS)
SNR/SINAD/SFDR 10.3
Input Frequency, Encode MSPS
10.3MHz
ENCODE 105MSPS
(-6.0dBFS)
-100
(-0.5dBFS) (-3.0dBFS)
ENCODE MSPS
ANALOG INPUT FREQUENCY
Harmonics 10.3
Harmonics fIN: MSPS
ENCODE 105MSPS
ENCODE 105MSPS WORST OTHER (-0.5dBFS)
SINAD (-3.0dBFS)
WORST OTHER (-6.0dBFS) WORST OTHER (-3.0dBFS)
SINAD (-6.0dBFS) SINAD (-0.5dBFS)
ANALOG INPUT FREQUENCY
ANALOG INPUT FREQUENCY
SINAD fIN: MSPS
Worst-Case Spur (Other than Second Third) fIN: MSPS
REV.
AD9432
ENCODE 105MSPS 10.3MHz (-0.53dBFS) 67.32dB SINAD 67.07dB SFDR -85dBc
ENCODE 105MSPS 50.3MHz (-0.46dBFS) 67.0dB SINAD 66.7dB SFDR -80dBc
SAMPLES
-100 -110 -120
-100 -110 -120 SAMPLES
Spectrum: MSPS, 10.3
Spectrum: MSPS, 50.3
ENCODE 105MSPS 27.0MHz (-0.52dBFS) 67.3dB SINAD 67.0dB SFDR -83.1dBc
AIN1 29.3MHz (-7dBFS) AIN2 30.3MHz (-7dBFS) ENCODE 105MSPS
-100 -110 -120 SAMPLES
-100 -110 -120 SAMPLES
Spectrum: MSPS,
Two-Tone Spectrum, Wideband: MSPS, AIN1 29.3 MHz, AIN2 30.3
ENCODE 105MSPS 40.9MHz (-0.56dBFS) 67.2dB SINAD 66.9dB SFDR -80dBc
AIN1 70.3MHz (-7dBFS) AIN2 71.3MHz (-7dBFS) ENCODE 105MSPS
-100 -110 -120 SAMPLES
-100 -110 -120 SAMPLES
Spectrum: MSPS, 40.9
Two-Tone Spectrum, Wideband: MSPS, AIN1 70.3 MHz, AIN2 71.3
REV.
AD9432
WORST-CASE SPURIOUS dBFS
1.00 0.75 0.50
ANALOG INPUT POWER LEVEL dBFS ENCODE 105MSPS 50.3MHz
dBFS
0.25 0.00
-0.25 -0.50 -0.75 -1.00
Single Tone SFDR
Integral Nonlinearity: MSPS
1.00 0.75 0.50
0.00
-0.25 -0.50 -0.75 -1.00
VOLTAGE
CURRENT
0.25
Differential Nonlinearity: MSPS
Voltage Reference Output Current Load
REV.
AD9432
APPLICATION NOTES Theory Operation
PECL GATE
AD9432
ENCODE ENCODE
AD9432 multibit pipeline converter that uses switched capacitor architecture. Optimized high speed, this converter provides flat dynamic performance frequencies near Nyquist. transitional errors calibrated final test typical accuracy 0.25 less.
USING AD9432
Analog Input
Figure Coupling ENCODE Inputs
ENCODE Voltage Level Definition
analog input AD9432 differential buffer. input buffer self-biased on-chip resistor divider that sets common-mode voltage nominal (see Equivalent Circuits section). Rated performance achieved driving input differentially. Minimum input offset voltage obtained when driving from source with differential source impedance such transformer applications. Capacitive coupling inputs will increase input offset voltage much Driving single-endedly will degrade performance. best dynamic performance, impedances should match. Special care taken design analog input section AD9432 prevent damage corruption data when input overdriven. nominal input range p-p. Each analog input will when driven differentially.
voltage level definitions driving ENCODE ENCODE single-ended differential mode shown Figure ENCODE Inputs Differential Signal Amplitude (VID) High Differential Input Voltage (VIHD) Differential Input Voltage (VILD) Common-Mode Input (VICM) 1.25 min, High Single-Ended Voltage (VIHS) Single-Ended Voltage (VILS)
ENCODE ENCODE VIHD VICM VILD
VIHS ENCODE
VILS
Figure Differential Single-Ended Input Levels
Often, cleanest clock source crystal oscillator producing pure sine wave. this configuration, with roughly symmetrical clock input, input ac-coupled biased reference voltage that also provides ENCODE. This ensures that reference voltage centered encode signal.
Digital Outputs
Figure Full-Scale Analog Input Range
ENCODE Input
high speed converter extremely sensitive quality sampling clock provided user. track/hold circuit essentially mixer, noise, distortion, timing jitter clock will combined with desired signal output. that reason, considerable care been taken design ENCODE input AD9432, user advised give commensurate thought clock source. ENCODE input supports either differential single-ended fully TTL/CMOS compatible. Note that ENCODE inputs cannot driven directly from PECL level signals (VIHD max). PECL level signals easily accommodated coupling shown Figure Good performance obtained using MC10EL16 circuit drive encode inputs.
digital outputs (2.7 TTL/CMOScompatible lower power consumption. output data format Two's Complement, illustrated Table range (OR) output (logic normal operation) will HIGH during clock cycle when output data (Dx) reach positive negative full scale (-2048 +2047). internally generated each clock cycle, same pipeline latency propagation delay output data, will remain HIGH until output data reflect in-range condition. output bits (Dx) will roll over, will therefore remain positive negative full scale (+2048 -2047) while output HIGH.
-10-
REV.
AD9432
Table Output Coding (VREF (Two's Complement)
Code +2047 -2048
AIN-AIN 1.000 -0.00049 -1.000
Digital Output 0111 1111 1111 0000 0000 0000 1111 1111 1111 1000 0000 0000
common-mode voltage AD8138 outputs adjusted input VOCM provide common-mode voltage AD9432 inputs require.
10pF
AD9432
22pF VOCM
AD8138
Voltage Reference
stable accurate voltage reference built into AD9432 (VREFOUT). normal operation internal reference used strapping placing decoupling capacitor VREFIN. input range adjusted varying reference voltage applied AD9432. appreciable degradation performance occurs when reference adjusted ±5%. full-scale range tracks reference voltage changes linearly.
10pF
Figure AD8138/AD9432 Schematic
Timing
AD9432 provides latched data outputs, with pipeline delays. Data outputs included available propagation delay after rising edge encode command (see Figure length output data lines loads placed them should minimized reduce transients within AD9432; these transients detract from converter's dynamic performance. minimum guaranteed conversion rate AD9432 MSPS. internal clock rates below MSPS, dynamic performance degrade. Therefore, input clock rates below should avoided. During initial power-up, whenever clock AD9432 interrupted, output data will accurate data clock cycles, whichever longer.
Using AD8138 Drive AD9432
SINAD
Figure Measured SINAD (Encode MSPS)
circuit Figure breadboarded measured performance shown Figures figures shown supplies AD8138-performance dropped about dB-2 with single supply AD8138. Figure shows SINAD dBFS analog input frequency varied from with encode rate MSPS. measurements nominal conditions room temperature. Figure shows second third harmonic distortion performance under same conditions.
differential output from Analog Devices, Inc., AD8138, used drive AD9432 dc-coupled applications. AD8138 specifically designed driver applications. Superior performance maintained analog frequencies MHz. AD8138 provides single-ended-to-differential conversion, providing low-cost option transformer coupling applications well.
-100
Figure Measured Second Third Order Harmonic Distortion (Encode MSPS)
REV.
-11-
AD9432
EVALUATION BOARD
STOP: 5.00GS/s
AD9432 evaluation board offers easy test AD9432. requires analog signal, encode clock, power supplies inputs. clock buffered board provide clocks on-board latches. digital outputs output clock available standard 37-pin connector
Power Connector
ACQS
3.4V 2.5mV
Power supplied board detachable 4-pin power strips P30, P40.
FREQ 49.995MHz SIGNAL AMPLITUDE
VCC2 V/165 V/200
Supply
Analog Supply
500mV 2.00V 500mV 5.00ns 3.00V
Figure Analog Input Levels
Connect Connect /105 Latch, Digital Output Supply
Analog Inputs
evaluation board accepts analog input signal connector This single-ended signal ac-coupled capacitor drives wideband transformer (MiniCircuits ADT1-1WT) that converts single-ended signal differential signal. (The AD9432 should driven differentially provide optimum performance.) evaluation board shipped with termination resistors which provide effective termination impedance; input termination resistor optional. Note: second harmonic distortion that some transformers tend introduce high frequencies reduced coupling transformers series shown Figure (Improvements order dB-4 realized.)
AIN+ AIN-
full-scale analog inputs should signals degrees phase with each other, shown Figure analog inputs biased on-chip resistor dividers that common-mode voltage approximately (0.6 AIN+ AIN- each vary between shown upper traces Figure lower trace input V/div scale).
Encode
encode input board connector p-p) input ac-coupled drives high-speed differential line receivers (MC10EL16). These receivers provide subnanosecond rise times their outputs-a requirement clock inputs optimum performance. EL16 outputs PECL levels must ac-coupled meet common-mode levels required AD9432 encode inputs. PECL/TTL translator (MC100ELT23), provides clocks required output latches, DAC, 37-pin connector. Note: Jitter performance clock source critical this performance level; stable, crystal-controlled signal generator used generate performance plots. Figure shows Encode+ clock ADC. latch clock generated card also shown plot.
STOP: 5.00GS/s ACQS
Figure Improving Second Harmonic Distortion Performance
2.33V 810mV
FREQ 106.3167MHz SIGNAL AMPLITUDE
1.00V
1.00V
5.00ns
1.20V
Figure Encode+ Clock Latch Clock
-12-
REV.
AD9432
DATA OUTPUTS
digital outputs latched board 574s; latch outputs available 37-pin connector Pins 25-36. latch output clock (data ready) available with complement There series termination resistors data clock outputs. These changed required accommodate different loading situations. Figure shows data switching output clock (DR) connector.
STOP: 5.00GS/s ACQS
evaluation board on-board reconstruction (AD9752). This placed only facilitate testing debug board. should used measure performance ADC, will accurately indicate performance. output available will drive load. Provision power down DAC.
LAYOUT
3.06V -390mV FREQ 105.4562MHz
designed four-layer board. Components routing layer with ground flood additional isolation. Test ground points were judiciously placed facilitate high-speed probing. common ground plane exists second layer. third layer three split power planes, support logic. DAC, components, routing located bottom layer.
TROUBLESHOOTING
board does seem working correctly, following: Verify power pins. Check that jumpers correct position desired mode operation. Verify VREF running encode clock analog inputs speeds MSPS/1 MHz) monitor outputs, output, outputs toggling. AD9432 Evaluation Board provided design example customers Analog Devices, Inc. makes warranties, express, statutory, implied, regarding merchantability fitness particular purpose.
1.00V
1.00V
5.00ns
1.20V
Figure Data Clock 37-Pin Connector
REFERENCE
AD9432 on-chip reference available VREFOUT (Pin 46). Most applications will simply this output VREFIN input (Pin 45). This accomplished jumping board. external voltage reference drive VREFIN desired strapping placing AD780 voltage reference board (not supplied).
REV.
-13-
AD9432
Bill Materials
Quantity
REFDES C1-C8, C10-C13, C17, C19-C22, C27-C29, C41, C42, C47, C48, C53, C56, C58, C60, C61, C14, C18, C31, E1-E13, E30, E32, E40, E42, P30, R10, (R1, Optional) R25, R26, R31, RP1-RP4 U12-U13
Device Capacitor
Package
Value 0.01
Capacitor Capacitor Capacitor E-HOLE Connector 37-Pin Connector Power Connector Resistor Resistor Resistor Resistor Transformer Reference (Not Supplied) Inverter Supplied) Latch PECL/TTL Translator Differential Receiver Resistor
CAPTAJD CAPTAJD Test Point Female 1206 1206 1206 1206
747462-2 Mini-Circuits ADT1-1WT AD9752 AD780N NC7SZ04P5 AD9432 74AC574M MC100ELT23 MC10EL16 24.9
SOIC SOIC SC70 52QFP SOIC SOIC SOIC 1206
-14-
REV.
AGND EXTREF (MSB) EXTREF AGND VREFOUT VREFIN FLOAT AGND
AGND AGND AGND AGND MC10EL16 AGND AGND AGND VCC2 AGND
AGND AGND
REV.
AGND (NOT SUPPLIED) RPAK_ AGND AD780N AGND +VIN TEMP 2.5/3V VOUT TRIM
AD9432
ANALOG
AGND 24.9 24.9
SMBPN
AGND
ADT1-1WT
RPAK_ AGND
(OPTIONAL) 0.01
Figure 17a. Schematic
-15-
AGND MC10EL16 MC100ELT23 AGND AGND
ENCODE
AGND AGND
SMBPN
(R1, OPTIONAL) AGND VCC2 AGND AGND NC7SZ04P5 (NOT SUPPLIED) AGND CONNECT AGND
CLOCK
AD9432
BYPASS AGND VCC2
AGND
AGND
(+3V)
AD9432
BYPASS LATCHES AGND
AGND
(+5V)
AGND
AGND
VCC2 (+5V)
AGND
AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND
CLOCK RPAK_742 74AC574M GROUND PLANE CONNECTING E-HOLES AGND AGND 74AC574M
OUT_EN CLOCK
SCOPE TEST POINTS
AGND AGND AGND AGND AGND AGND AGND AGND
Figure 17b. Schematic (Continued)
-16-
CLOCK DVDD DCON AVDD ICOMP IOUTA IOUTB ACON FSADJ REFIO REFLO SLEEP AGND AGND NC7SZ04P5 CLOCK VCC2 AGND VCC2 24.9
CLOCK
OUT_EN CLOCK
RPAK_742
AGND
DACOUT
VCC2 SMBPN
AGND AGND
AD9752
CONNECT
REV.
AGND
VCC2
AGND AGND AGND
AD9432
Figure Silkscreen
Figure Split Power Plane
Figure Level Routing
Figure Bottom Layer Route
Figure Ground Plane
Figure Bottom Silkscreen
REV.
-17-
AD9432
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
52-Lead Plastic Quad Flatpack (LQFP) (ST-52)
0.063 (1.60) 0.030 (0.75) 0.018 (0.45)
0.472 (12.00)
SEATING PLANE VIEW
(PINS DOWN)
0.394 (10.0)
0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
0.026 (0.65)
0.015 (0.38) 0.009 (0.22)
CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
THERMALLY ENHANCED 52-Lead Power Thin Plastic Quad Flatpack (LQFP_ED) (SQ-52)
0.093 (2.35) 0.087 (2.20) PLCS) 0.081 (2.05)
0.472 (12.00) 0.307 (7.80)
0.104 (2.65) 0.098 (2.50) PLCS) 0.093 (2.35)
VIEW
(PINS DOWN)
0.402 (10.20) 0.394 (10.00) 0.386 (9.80)
EXPOSED HEATSINK (CENTERED)
0.236 (6.00) 0.232 (5.90) 0.228 (5.80)
0.026 (0.65)
0.015 (0.38) 0.013 (0.32) 0.009 (0.22)
0.236 (6.00) 0.232 (5.90) 0.228 (5.80) BOTTOM VIEW
(PINS
0.063 (1.60) 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) SEATING PLANE VIEW
0.057 (1.45) 0.055 (1.40) 0.053 (1.35)
0.006 (0.15) 0.002 (0.05) 0.004 (0.10) COPLANARITY
VIEW
NOTES CONTROLLING DIMENSIONS MILLIMETERS; INCH DIMENSIONS ROUNDED-OFF MILLIMETER EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN. ALTHOUGH REQUIRED APPLICATIONS, AD9432 EXPOSED METALLIC PACKAGE BOTTOM WHICH INTENDED ENHANCE HEAT REMOVAL PATH. MAXIMIZE REMOVAL HEAT, LAND PATTERN WITH CLOSELY SPACED THERMAL VIAS GROUND PLANE(S) SHOULD INCORPORATED WITHIN FOOTPRINT PACKAGE CORRESPONDING EXPOSED METAL DIMENSIONS PACKAGE. SOLDERABLE LAND AREA SHOULD SOLDER MASK DEFINED LEAST SAME SIZE SHAPE EXPOSED AREA PACKAGE. LEAST 0.25 CLEARANCE BETWEEN OUTER EDGES LAND PATTERN INNER EDGES PATTERN SHOULD MAINTAINED AVOID SHORTS.
-18-
REV.
AD9432 Revision History
Location Data Sheet changed from REV. REV. Page
Edits SPECIFICATIONS Edits ABSOLUTE MAXIMUM RATINGS Edits ORDERING GUIDE Addition text USING AD9432 section Edits Figure Edits Figure Addition SQ-52 Package Outline
REV.
-19-
-20-
C00587-0-1/02(E)
PRINTED U.S.A.
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