8-Bit MSPS/60 MSPS/80 MSPS Converter AD9057 PWRDN AD9057
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FEATURES 8-Bit, Power ADC: Typical Analog Bandwidth On-Chip Reference Track-and-Hold Analog Input Range Single Supply Operation Logic Interface Power-Down Mode: Performance Grades MSPS, MSPS, MSPS) APPLICATIONS Digital Communications (QAM Demodulators) YC/Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation
8-Bit MSPS/60 MSPS/80 MSPS Converter AD9057
PWRDN
AD9057
BIAS VREF VREF 2.5V D7-D0
ENCODE
PRODUCT DESCRIPTION
AD9057 8-bit monolithic analog-to-digital converter optimized cost, power, small size, ease use. With MSPS, MSPS, MSPS encode rate capability full-power analog bandwidth MHz, component ideal applications requiring excellent dynamic performance. minimize system cost power dissipation, AD9057 includes internal reference track-and-hold (T/H) circuit. user must provide only power supply encode clock. external reference driver components required many applications. AD9057's encode input TTL/CMOS compatible, 8-bit digital outputs operated from supplies.
power-down function exercised bring total consumption power-down mode, digital outputs driven high impedance state. Fabricated advanced BiCMOS process, AD9057 available space-saving 20-lead shrink small outline package (20-lead SSOP) specified over industrial temperature range (-40C +85C). Customers desiring multichannel digitization consider AD9059, dual 8-bit, MSPS monolithic based AD9057 core. AD9059 available 28-lead surface-mount plastic package (28-lead SSOP) specified over industrial temperature range.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 2003 Analog Devices, Inc. rights reserved.
AD9057-SPECIFICATIONS
external reference, unless otherwise noted.)
AD9057BRS-60 0.75 0.75 AD9057BRS-80 0.75 0.75 Unit Bits ppm/C
Parameter RESOLUTION ACCURACY Differential Nonlinearity Integral Nonlinearity Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (Centered Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth BAND REFERENCE Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DYNAMIC PERFORMANCE3 Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SINAD) (With Harmonics) 10.3 Effective Number Bits (ENOB) 10.3 Signal-to-Noise Ratio (SNR) (Without Harmonics) 10.3 Second Harmonic Distortion 10.3 Third Harmonic Distortion 10.3 Tone Intermodulation Distortion (IMD) Differential Phase Differential Gain DIGITAL INPUTS Logic Voltage Logic Voltage Logic Current Logic Current Input Capacitance Encode Pulsewidth High (tEH) Encode Pulsewidth (tEL)
Temp
Test Level
AD9057BRS-40
Full Full Full Full Full
0.75 0.75
Guaranteed -2.5
Guaranteed -2.5
Guaranteed -2.5
Full Full Full Full Full Full Full Full
ppm/C MSPS MSPS
11.5
18.0
14.2
11.3
45.5 44.0
43.5
41.5
43.5
Bits Bits
Full Full Full Full
46.5 45.5
42.5
Degrees
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AD9057
Parameter Temp Test Level AD9057BRS-40 AD9057BRS-60 AD9057BRS-80 Unit
DIGITAL OUTPUTS Logic Voltage (VDD Logic Voltage (VDD Logic Voltage Output Coding POWER SUPPLY Supply Current Supply Current (VDD Power Dissipation5, Power-Down Dissipation Power Supply Rejection Ratio (PSRR)
Full Full Full
2.95 4.95 0.05 Offset Binary Code
2.95 4.95 0.05 Offset Binary Code
2.95 4.95 0.05 Offset Binary Code
Full Full Full Full
mV/V
NOTES Gain error gain temperature coefficient based only (with fixed external reference). measured from level encode 10%/90% levels digital output swing. digital output load during test exceed load current SNR/harmonics based analog input voltage -0.5 dBFS referenced full-scale input range. Digital supply current based output drive with loading under dynamic test conditions. Power dissipation based specified encode 10.3 analog input dynamic test conditions 5%). Typical thermal impedance style (SSOP) 20-lead package 46C/W, 80C/W, 126C/W. Specifications subject change without notice.
EXPLANATION TEST LEVELS
Test Level
Description 100% production tested. 100% production tested sample tested specified temperatures. Sample tested only. Parameter guaranteed design characterization testing. Parameter typical value only. 100% production tested 25C; guaranteed design characterization testing industrial temperature range.
ENCODE
DIGITAL OUTPUTS
APERTURE DELAY PULSEWIDTH HIGH PULSEWIDTH OUTPUT VALID TIME OUTPUT PROP DELAY
Figure Timing Diagram
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AD9057
ABSOLUTE MAXIMUM RATINGS* CONFIGURATION
PWRDN VREF VREF
Analog Inputs -0.5 Digital Inputs -0.5 VREF Input -0.5 Digital Output Current Operating Temperature -55C +125C Storage Temperature -65C +150C Maximum Junction Temperature 150C Maximum Case Temperature 150C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
(LSB)
AD9057
VIEW (Not Scale) BIAS ENCODE (MSB)
ORDERING GUIDE
FUNCTION DESCRIPTIONS Mnemonic PWRDN Function Power-Down Function Select; Logic High Power-Down Mode (Digital Outputs High Impedance State). Internal Reference Output (2.5 typ); Bypass with Ground. Reference Input (2.5 typ, 10%). Ground (Analog/Digital). Analog Power Supply. Bias Coupling IN). Analog Input ADC. Encode Clock (ADC Samples Rising Edge Encode). Digital Outputs ADC. Digital Output Power Supply; Nominally
Model AD9057BRS-40 AD9057BRS-60 AD9057BRS-80 AD9057/PCB
Temperature Range -40C +85C -40C +85C -40C +85C
Package Option* RS-20 RS-20 RS-20 Evaluation Board
VREF
Shrink Small Outline Package (SSOP).
Table Digital Coding (VREF
VREF BIAS ENCODE
Analog Input 2.502 2.498
Voltage Level Positive Full Scale Midscale +1/2 Midscale -1/2 Negative Full Scale
Digital Output 1111 1111 1000 0000 0111 1111 0000 0000
11-14, 17-20
D7-D0
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9057 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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Typical Performance Characteristics-AD9057
SECOND HARMONIC
ENCODE 60MSPS ANALOG 10.3MHz, -0.5dBFS SINAD 46.1dB ENOB 7.36 BITS 46.5dB ENCODE 60MSPS -0.5dBFS
THIRD HARMONIC
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Spectral Plot MSPS, 10.3
Harmonic Distortion Frequency
ENCODE 60MSPS ANALOG 76MHz, -0.5dBFS SINAD 44.9dB ENOB 7.16 BITS 45.2dB FREQUENCY (MHz)
FREQUENCY (MHz) ENCODE 60MSPS 9.5MHz -7.0dBFS 9.9MHz -7.0dBFS -52.0dBc -53.0dBc
Spectral Plot MSPS,
Two-Tone Intermodulation Distortion
SINAD
SINAD
ENCODE 60MSPS -0.5dBFS
10.3MHz, -0.5dBFS
ANALOG INPUT FREQUENCY (MHz)
ENCODE RATE (MSPS)
SINAD/SNR Frequency
SINAD/SNR Encode Rate
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AD9057
12.0 11.0 10.0
(ns)
10.3MHz, -0.5dBFS
ENCODE RATE (MSPS)
TEMPERATURE
Power Dissipation Encode Rate
Temperature/Supply (VDD
46.5 46.0 45.5 45.0 44.5 SINAD
46.5 46.0 45.5 45.0 44.5 44.0 SINAD 43.5 43.0 42.5 ENCODE 60MSPS 10.3MHz, -05dBFS
44.0 43.5 43.0 42.5 42.0 41.5 TEMPERATURE ENCODE 60MSPS 10.3MHz, -0.5dBFS
8.35 10.0 ENCODE HIGH PULSEWIDTH (ns)
10.9
SINAD/SNR Temperature
SINAD/SNR Encode Pulsewidth
-0.2 -0.4
GAIN ERROR
-0.6
GAIN (dB)
-0.8 -1.0 -1.2 -1.4 -1.6 -1.8 TEMPERATURE
ENCODE 60MSPS -0.5dBFS
ANALOG FREQUENCY (MHz)
Gain Temperature (with External Reference)
Frequency Response
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AD9057
THEORY OPERATION
AD9057 combines Analog Devices' proprietary MagAmp gray code conversion circuitry with flash converter technology provide high performance, cost ADC. design architecture ensures power, high speed, 8-bit accuracy. single-ended TTL/CMOS compatible ENCODE input controls timing sampling analog input strobing digital outputs (D7-D0). internal voltage reference (VREF OUT) used control gain offset external reference applied. analog input signal buffered input applied high speed track-and-hold. track-and-hold circuit holds analog input value during conversion process (beginning with rising edge encode command). track-and-hold's output signal passes through gray code flash conversion stages generate coarse fine digital representations held analog input level. Decode logic combines multistage data aligns 8-bit word strobed outputs rising edge encode command. MagAmp/Flash architecture AD9057 results three pipeline delays output data.
USING AD9057 Analog Inputs
VREF
AD9057
AD8041 (-0.5V +0.5V) VREF
Figure DC-Coupled AD9057 (Inverted VIN)
Voltage Reference
stable accurate voltage reference built into AD9057 (VREF OUT). reference output used gain/offset connecting VREF VREF internal reference capable providing drive current (for biasing analog input other user circuitry). Some applications require greater accuracy, improved temperature performance, gain adjustments that cannot obtained using internal reference. external voltage applied VREF with VREF disconnected gain adjustment (the VREF internally tied directly circuitry). gain offset will vary simultaneously with external reference adjustment with ratio adjustment reference varies gain input range center offset mV). Theoretical input voltage range versus reference input voltage calculated from following equations: VRANGE (p-p) VMIDSCALE VTOP-OF-RANGE VREF IN/2.5 VREF VREF VRANGE
AD9057 provides single-ended analog input impedance input requires bias current (typical) centered near 10%). bias provided user derived from ADC's internal voltage reference. Figure shows cost bias implementation allowing user capacitively couple signals directly into without additional active circuitry. best dynamic performance, VREF should decoupled ground with capacitor minimize modulation reference voltage) bias resistor should approximately bias resistor 20%) included within AD9057 used reduce application board size complexity.
VBOTTOM-OF-RANGE VREF VRANGE
Digital Logic Systems)
VREF VREF BIAS p-p)
digital inputs outputs AD9057 easily configured interface directly with logic systems. encode power-down (PWRDN) inputs CMOS stages with thresholds making inputs compatible with TTL, CMOS, CMOS logic families. with high speed data converters, encode signal should clean jitter free prevent degradation dynamic performance. AD9057's digital outputs will also interface directly with CMOS logic systems. voltage supply (VDD) these CMOS stages isolated from analog voltage supply. varying voltage this supply pin, digital output high level will change systems. Optimum obtained running outputs Care should taken isolate supply voltage from analog supply minimize digital noise coupling into ADC.
AD9057
Figure Capacitively Coupled AD9057
Figure shows typical connections high performance biasing using ADC's internal voltage reference. components powered from single supply. example, analog input signals referenced ground.
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AD9057
AD9057 provides high impedance digital output operation when driven into power-down mode (PWRDN, logic high). (minimum) power-down time should provided before high impedance characteristic required outputs. power-up period should provided ensure accurate output data after reactivation (valid output data available three clock cycles after delay).
Timing
full-power analog bandwidth maximum sampling rate, provides sufficient pixel-to-pixel transient settling time ensure accurate MSPS video digitization. Figure shows typical video digitizer implementation AD9057.
AD9057
AD9057 guaranteed operate with conversion rates from MSPS MSPS depending grade. designed operate with encode duty cycle 50%, performance insensitive moderate variations. Pulsewidth variations (allowing encode signal meet minimum/ maximum high/low specifications) will cause degradation performance (see Figure timing diagram).
Power Dissipation
GREEN AD9057
BLUE AD9057
PIXEL CLOCK H-SYNC
Figure Video Encoder
Evaluation Board
power dissipation AD9057 specified reflect typical application setup under following conditions: analog input -0.5 dBFS 10.3 MHz, digital outputs loaded with typical maximum). actual dissipation will vary these conditions modified user applications. shows typical power consumption AD9057 versus encode frequency supply voltage. power-down function allows users reduce power dissipation when data required. TTL/CMOS high signal (PWRDN) shuts down portions brings total power dissipation less than internal band voltage reference remains active during power-down mode minimize reactivation time. power-down function desired, should tied ground.
APPLICATIONS
AD9057/PCB evaluation board provides easy-to-use analog/digital interface 8-bit, MSPS ADC. board includes typical hardware configurations variety high speed digitization evaluations. On-board components include AD9057 20-lead SSOP package), optional analog input buffer amplifier, digital output latch, board timing drivers, analog reconstruction digital-to-analog converter, configurable jumpers coupling, coupling, power-down function testing. board configured shipment coupling using AD9057's internal voltage reference. dc-coupled analog input applications, amplifier configured operate unity gain inverter with adjustable offset analog input signal. full-scale drive, analog input signal should into (R1) referenced ground amplifier offsets analog signal +VREF (2.5 typical) center voltage proper input drive. dc-coupled operation, connect (analog input (amplifier output analog input AD9057) using board jumper connectors. offset analog input signal modified adjusting potentiometer R10. ac-coupled analog input applications, amplifier removed from analog signal path. analog signal coupled into input AD9057 through capacitor pulls analog input bias current from VREF voltage through resistor internal AD9057 (BIAS OUT). analog input signal board should into (R1) full-scale drive. ac-coupled operation, connect (analog input feedthrough capacitor) analog input internal bias resistor) using board jumper connectors. on-board reference voltage used drive external reference applied. internal voltage reference, connect (VREF VREF IN). apply external voltage reference, connect (external reference from banana jack VREF IN). external voltage reference should 10%.
wide analog bandwidth AD9057 makes attractive variety high performance receiver encoder applications. Figure shows ADCs typical cost demodulator implementation cable, satellite, wireless modem receivers. excellent dynamic performance higher analog input frequencies encode rates empowers users employ direct sampling techniques (refer spectral plot). sampling eliminates simplifies analog mixer filter stages reduce total system cost power.
AD9057 AD9057
Figure Digital Receiver
high sampling rate analog bandwidth AD9057 ideal computer video digitizer applications. With
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AD9057
power-down function AD9057 done through board jumper connection. Connect PWRDN) power-down operation. normal operation, connect (ground PWRDN). encode signal source should TTL/CMOS compatible capable driving termination (R7). digital outputs AD9057 buffered through latches evaluation board (U3) available user connector Pins Latch timing derived from encode clock digital clocking signal provided board user connector Pins on-board reconstruction digital-to-analog converter available quick evaluations performance using
oscilloscope spectrum analyzer. converts ADC's digital outputs analog signal examination connector. clocked encode frequency. AD9760 10-bit/100 MSPS single supply DAC. reconstruction signal facilitates quick system troubleshooting confirmation functionality without requiring external digital memory, timing, display interfaces. used limited dynamic testing, customers should note that test results will based combined performance (the best performance will recognized evaluating digital outputs directly).
ENCODE PWRDN
VREF
Digital Inputs
Analog Input
VDD,
D0-D7 VREF BIAS
Digital Outputs
Bias Output
VREF VREF 2.5k
VREF Output
VREF Input
Figure Equivalent Circuits
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AD9057
AD9057 PWRDN (LSB) VREF VREF BIAS (MSB) 74ACQ574 PWRDN
ANALOG
AD8041Q
C37DRPF
ENCODE
74AC00 74AC00 74AC00 74AC00
AD9760AR
CLOCK DVDD (MSB) AVDD COMP2 COMP1
REFIO REFLO SLEEP
ANALOG RECONSTRUCT
(LSB) IOUT
PWRDN
DECOUPLING CAPS
Figure Evaluation Board Schematic
-10-
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AD9057
Figure Evaluation Board Layout
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-11-
AD9057
OUTLINE DIMENSIONS 20-Lead Shrink Small Outline Package [SSOP] (RS-20)
Dimensions shown millimeters
5.60 5.30 8.20 5.00 7.80 7.40
2.00
1.85 1.75 1.65
0.25 0.09 0.95 0.75 0.55
0.05 COPLANARITY 0.10
0.65
0.38 0.22
SEATING PLANE
COMPLIANT JEDEC STANDARDS MO-150AE
Revision History
Location 5/03-Data Sheet changed from REV. REV. Page
Change SPECIFICATIONS Updated OUTLINE DIMENSIONS
9/01-Data Sheet changed from REV. REV.
Edit ABSOLUTE MAXIMUM RATINGS
-12-
REV.
C00561-0-5/03(D)
7.50 7.20 6.90
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