3.6.1 CY7C964 Overview CY7C960 designed with CY7C964 VMEbus Inter

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3.6.1 CY7C964 Overview CY7C960 designed with CY7C964 VMEbus Inter

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CY7C964 Interface
3.6.1 CY7C964 Overview
CY7C960 designed with CY7C964 VMEbus Interface Logic Circuit. This device fully described Section CY7C964 Interface Logic Circuit. CY7C960 provides control timing interface with CY7C964. Interface timing generated CY7C960 designed CY7C964 delay characteristics. CY7C964 contains collection counters, latches, multiplexers used facilitate data handling during many VMEbus data transactions. Three-state high drive buffers allow direct connection local address data busses. Additionally, CY7C964 contains address comparator with mask function allow CY7C964 form part user's slave address decoder. Defined companion VIC068A/VIC64 devices, CY7C964 been designed into many high-performance VME64 boards. concert with CY7C960, performs functions address decoder, data multiplexer, local address counter, facilitate design high-performance slave systems.
3.6.2
CY7C964 Connections
signals that provided CY7C960 CY7C964 are: LADI, LEDI, LEDO, DENO*, ABEN*, DENIN*, DENIN1*, LAEN, STROBE, LDS, using dedicated pins. These signals described description section. LADI (Latch ADdress controls transparent latch which connects VMEbus address local address. default state signal ensures that VMEbus address driven local pins, allowing implementation VMEbus address decoder circuitry local address bus. LAEN (Local Address ENable) input tied High least significant CY7C964 ensure that local address always enabled. least significant CY7C964 LAEN controlled CY7C960 allow CY7C960 source address during block transfers when address increment (dependent transfer type: single, double, quad byte). Note that order take advantage "local holdoff" feature CY7C960, necessary control LAEN upper CY7C964 devices. LAEN must driven during holdoff. LEDI (Latch Enable Data LEDO (Latch Enable Data Out) control VMEbus local data transfer latches CY7C964. Data read from local resources must LEDO burst transfers, while LEDI provides data hold time during burst transfers when data captured from CY7C964. These signals, holding data interface allow "write posting" "read-ahead" performance features.
3-61
CY7C964 Interface
DENO* (VMEbus Data ENable Out) pair signals, DENIN* DENIN1* (local Data ENable normally used local VMEbus data enable. DENIN* DENIN1* also active during address broadcast VMEbus transactions. They used inform external address decoder when data sampled high-order address information. During MD32 data cycles, function DENO* DENIN*/DENIN1* identical LEDO LEDI respectively. two-stage pipelined latch inside CY7C964 controlled data sourcing case LEDO DENO* working concert, data capture case LEDI DENIN*/DENIN1* working concert. Each VMEbus data cycle served local data cycles. second cycle slave read must data falling edge DENO*. slave write, data hold second cycle provided assertion DENIN* (D64) DENIN1* (MD32). used during D64/MD32 slave write transfers control VMEbus address local data demultiplexing, during initialization period control selection address mask compare registers. During multiplexed slave data capture, signal which controls data hold time with respect deassertion CAS* and/or DBE. ABEN* (VME Address ENable) active only during multiplexed data transactions enable VMEbus address pins during MD32 transfers. signal that informs CY7C964s that data phase multiplexed data transfer progress on-chip pipelining should used multiplex demultiplex local data. CY7C964 expressly designed demultiplex MD32 transactions non-multiplexed local data bus. STROBE timing signal used load on-chip address mask compare registers CY7C964. considered latch enable signal which latches local data when High. on-chip counters CY7C964 used local address counting during slave block transfers VMEbus master bursts Kbyte boundaries. Therefore counter chains must enabled connecting appropriate carry-out carry-in pins. VMEbus counters CY7C964 used CY7C960. recommended that following connections made ensure correct operation during Reset period: Pull-up resistors attached ABEN*, DENO*; pull-down resistors attached LAEN LADI. These connections prevent CY7C964 drivers from turning during brief periods three-state operation during reset. CY7C964 several signals which used slave operations: BLT*, FC1, LADO, MWB*. LADO must tied Low. BLT* MWB* must tied High correct operation.
Figure 3-23 shows control signals CY7C964 driven during initialization load Address Compare Mask Registers. significant signals LDS, which selects
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CY7C964 Interface
which register load, STROBE, which actually strobes data local into appropriate register.
SYSRESET*
LDEN* PREN* PDATA PCLK STROBE
COMP.
MASK
Figure 3-23. Example CY7C964 Control Timing
3.6.3
Swap Buffer Control
CY7C960 designed control swap buffering necessary handling VMEbus transactions combination with 32-bit local memory. Figure 3-24 illustrates VMEbus byte lanes relate local memory. Note that CY7C960 coordinates control SWDEN* with DENIN*/DENIN1*. CY7C964 Byte(0) Byte(1) drivers turned during slave write transfers when SWDEN* active. Because DENIN*/DENIN1* used latch control signals during multiplexed data transactions (D64 MD32) DENIN* signaling CY7C964 Byte(0) Byte(1) must modified external logic (and only board handle BOTH A40/MD32 slave write transactions. required circuitry shown figure below.
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CY7C964 Interface
DENIN* Byte(0-1) DENIN1* Byte(0-1)
DENIN1* DENIN*
CY7C964
BYTE(0)
Additional logic only MD32 supported same board
VMEbus BYTE LANES
CY7C964
BYTE(1)
BYTE(1)
DENIN1* DENIN* SWDEN* R/W* DBE[0] DBE[1] DBE[2] DBE[3]
Cross-connect DENIN*s upper bytes!
BYTE(0) BYTE(3) BYTE(2)
'245
CY7C964 BYTE(2) BYTE(0)
'245
Figure 3-24. Swap Buffer Design
CY7C964
BYTE(3) BYTE(1)
3-64
LOCAL MEMORY

3.6.1 CY7C964 Overview CY7C960 designed with CY7C964 VMEbus Inter

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