Dual Channel, Gain-Ranging with RSSI AD6600 input channels, each

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Dual Channel, Gain-Ranging with RSSI AD6600 input channels, each

Datasheet Thumbnail

Top Searches for this datasheet

FEATURES Dual Inputs, MHz-250 Diversity Independent Signals Separate Attenuation Paths Oversample Channels MSPS Single Carrier MSPS/Channel Diversity Mode Total Signal Range from Automatic Gain-Ranging (AGC) from Converter Range >100 After Processing Gain Digital Outputs 11-Bit Word 3-Bit RSSI Word Clock, Indicator Single Power Supply Output DVCC Power Dissipation APPLICATIONS Communications Receivers PCS/Cellular Base Stations GSM, CDMA, TDMA Wireless Local Loop, Fixed Access
Dual Channel, Gain-Ranging with RSSI AD6600
input channels, each with input amplifiers automatic gain-ranging circuitry. Both channels sampled with track-and-hold followed 11-bit, MSPS analog-to-digital converter. Digital RSSI outputs, channel indicator, Clock output, references, control circuitry on-chip. Digital output signals two's complement, CMOS-compatible interface directly digital processing chips. primary dual analog input structure sampling both antennas two-antenna diversity receiver. However, Channels also used sample independent signals. Diversity, dual-channel mode, limited MSPS channel. single-channel mode, full clock rate MSPS applied single carrier. AD6600 used stand-alone sampling chip, combined with AD6620 Digital Receive Signal Processor. AD6620 provides dB-25 additional processing gain before passing data fixed- floating-point DSP. Driving AD6600 simplified using AD6630 differential amplifier. AD6630 easily matched inexpensive filters from MHz. Designed specifically cellular/PCS receivers, AD6600 supports GSM, IS-136, CDMA Wireless LANs, well proprietary interfaces used WLL/fixed-access systems. Units available plastic, surface-mount packages (44-lead LQFP) specified over industrial temperature range (-40°C +85°C).
PRODUCT DESCRIPTION
AD6600 mixed-signal receiver chip directly samples signals analog input frequencies MHz. device includes
FUNCTIONAL BLOCK DIAGRAM
NOISE FILTER
0dB, -12dB, -24dB ATTEN GAIN DETECT PEAK RSSI RSSI GAIN ATTEN 0dB, -12dB, -24dB
RESONANT PORT
AB_OUT
ANALOG
+12, +18dB GAIN
ENCODE CONVERTER TWO'S COMPLEMENT RSSI ENCODE RSSI [2:0] D10-D0
SELECT GAIN
AD6600
TIMING
CLK2
A_SEL
B_SEL
AVCC
DVCC
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
AD6600-SPECIFICATIONS
SPECIFICATIONS (AVCC DVCC
Parameter ANALOG INPUTS (AIN, AIN/BIN, BIN) Differential Analog Input Voltage Range1 Differential Analog Input Resistance2 Differential Analog Input Capacitance PEAK DETECTOR (Internal), RSSI Resolution RSSI Gain Step RSSI Hysteresis3 RESONANT PORT (FLT, FLT) Differential Port Resistance Differential Port Capacitance CONVERTER Resolution ENCODE INPUTS (ENC, ENC) Differential Input Voltage (AC-Coupled)4 Differential Input Resistance Differential Input Capacitance MODE INPUTS (A_SEL, B_SEL)5 Input High Voltage Range Input Voltage Range POWER SUPPLY Supply Voltages AVCC DVCC Supply Current IAVCC (AVCC IDVCC (DVCC POWER CONSUMPTION6 Temp Full Full 25°C
TMAX unless otherwise noted.)
Test Level AD6600AST 1.75 4.75 5.25 Unit Bits Bits
Full Full Full Full Full Full 25°C 25°C Full Full
Full Full Full Full Full
4.75
5.25 5.25
NOTES Analog Input Range function input frequency. specifications MHz-250 inputs. Analog Input Impedance function input frequency. specifications MHz-450 inputs. digital hysteresis used eliminate level uncertainty RSSI threshold points noise amplitude variations. Encode inputs should ac-coupled driven differentially. Encoding AD6600 details. A_SEL B_SEL should tied directly ground AVCC. Maximum power consumption computed maximum current nominal supplies. Specifications subject change without notice.
DIGITAL SPECIFICATIONS (AVCC DVCC
Parameter Temp
TMAX unless otherwise noted.)
AD6600AST CMOS DVCC DVCC 0.35 0.35 Two's Complement DVCC DVCC 0.35 Unit
Test Level
LOGIC OUTPUTS (D10-D0, AB_OUT, RSSI2-0) Logic Compatibility Logic Voltage (DVCC Full Logic Voltage (DVCC Full Logic Voltage (DVCC Full Logic Voltage (DVCC Full Output Coding (D10-D0) OUTPUT1, Logic Voltage (DVCC Logic Voltage (DVCC Logic Voltage (DVCC Logic Voltage (DVCC Full Full Full Full
NOTES Digital output load gate. output voltage levels, high low, tested switching rate MHz. Specifications subject change without notice.
REV.
AD6600 TIMING REQUIREMENTS SWITCHING SPECIFICATIONS
Parameter CONVERTER Conversion Rate Maximum Conversion Rate Minimum Conversion Rate Aperture Uncertainty ENCODE INPUTS (ENC, ENC)2 Period Pulsewidth High3 Pulsewidth Low4 CLOCK OUTPUT Output Frequency Output Period6 Pulsewidth Low6 Output Risetime7 Output Falltime7 OUTPUT RISE/FALL TIMES8 Output Risetime (D10:D0, RSSI2:0) Output Falltime (D10:D0, RSSI2:0) Output Risetime (AB_OUT) Output Falltime (AB_OUT) Name fENC tENC tENCH tENCL Full Full 25°C Full Full Full fENC tENCL tENCH tENCH/2 Temp Test Level
AD6600AST 1/(tENC)
(AVCC DVCC MSPS; TMIN TMAX unless otherwise noted.)
Unit MSPS MSPS MSPS MSPS
Full Full Full Full Full Full Full Full Full
NOTES AD6600 Timing Diagrams. switching specifications tested driving differentially. Several timing specifications function Encode high time, ENCH; these specifications shown data tables timing diagrams. Encode duty cycle should kept close possible. Encode pulse directly affects amount settling time available resonant port. External Analog (Resonant) Filter section details. Clock generated internally, therefore some specifications functions encode period duty cycle. timing measurements from CLK2 referenced crossing. This specification function Encode period duty cycle; reference timing diagrams Figure Output rise time measured from point point total CLK2 voltage swing; output fall time measured from point point total CLK2 voltage swing. Output rise time measured from point point total data voltage swing; output fall time measured from point point total data voltage swing. outputs specified with load. Specifications subject change without notice.
REV.
AD6600-SPECIFICATIONS
TIMING REQUIREMENTS SWITCHING SPECIFICATIONS1,
(AVCC DVCC MSPS, Duty Cycle 50%; TMIN TMAX unless otherwise noted.)
Parameter Encode Rising Falling3 Encode Rising Rising4 Encode MSPS, Duty Cycle Encode MSPS, Duty Cycle (D10:0, RSSI2:0)5 DATA Rising Delay3 DATA Hold Time3 DATA Falling Low3, DATA Setup Time4 Encode MSPS, Duty Cycle Encode MSPS, Duty Cycle6 AB_OUT Rising Delay3 AB_OUT Hold Time3 AB_OUT Falling Delay3, AB_OUT Setup Time4 Encode MSPS, Duty Cycle Encode MSPS, Duty Cycle6 ENCODE/DATA (D10:0, RSSI2:0) ENCODE DATA Rising Delay4 ENCODE DATA Hold Time4 Encode MSPS, Duty Cycle Encode MSPS, Duty Cycle ENCODE DATA Falling Delay4 ENCODE DATA Delay (Setup)4 Encode MSPS, Duty Cycle Encode MSPS, Duty Cycle6 ENCODE/AB_OUT ENCODE AB_OUT Rising Delay4 ENCODE AB_OUT Delay (Hold)4 Encode MSPS, Duty Cycle Encode MSPS, Duty Cycle ENCODE AB_OUT Falling Delay4 ENCODE AB_OUT Delay (Setup)4 Encode MSPS, Duty Cycle Encode MSPS, Duty Cycle6 Name Temp Full Full Full Full Full Full 25°C Full Full Full 25°C Full Full Full 25°C Full Full Full 25°C Full Full Full Full Full Full Full Full 25°C Full Full Full Full Full Full Full Full 25°C Full Test Level 25.7 19.0 10.0 11.0 16.5 12.0 10.7 12.5 -1.0 AD6600AST (tENCH)/2 27.2 20.5 15.0 15.5 tENCH 23.0 10.0 11.0 11.0 18.0 19.0 tENCH 19.5 tEN_DRL 33.7 27.0 tENC tEN_DFL 34.2 14.5 14.0 tEN_ARL 38.2 31.5 tENC tEN_AFL 30.7 11.5 10.5 28.7 22.0 Unit
20.0 22.0
23.0 26.0
tEN_DRL tH_DEN tEN_DFL tS_DEN
28.7 22.0
26.2
tEN_ARL tH_AEN tEN_AFL tS_AEN
32.7 26.0
22.2
NOTES AD6600 Timing Diagrams. switching specifications tested driving differentially. This specification function Encode period duty cycle. This specification function Encode period duty cycle. referenced crossing; digital output levels referenced crossings; outputs with load. these particular specifications, 25°C specification valid from 25°C 85°C. Full temperature specification includes cold temperature extreme covers entire range, -40°C +85°C. Specifications subject change without notice.
REV.
AD6600 SPECIFICATIONS
Parameter ANALOG INPUTS Analog Input Bandwidth2 Differential Analog Input Voltage Range Differential Analog Input Impedance3 Full-Scale Input Power Full-Scale Gain Tolerance4 MHz-250 MHz5 Gain Error dBFS Gain Matching (Input A:B) MHz-250 Range-to-Range Gain Tolerance MHz-250 Range-to-Range Phase Tolerance Channel Isolation6 MHz-250 Noise7 Minimum Attenuation Level Maximum Attenuation Level Attenuator 3OIP8 Signal-to-Noise Ratio (SNR)9, dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
(AVCC DVCC MSPS, Duty Cycle 50%; TMIN TMAX unless otherwise noted.)
Temp Full Full Full Full Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full Full Full Full Full 25°C Test Level AD6600AST 2.45 2.57 2.62 2.86 197-j24 188-j48 175-j57 161-j67 151-j73 140-j80 141-j75 173-j107 Unit
-1.0
+1.0
25°C Full Full Full Full Full Full Full Full Full
-1.5 0.05
+1.5
Degree Degree
-0.5
+0.5
25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C
54.5
REV.
AD6600-SPECIFICATIONS
SPECIFICATIONS (continued)
Parameter ANALOG INPUTS (Continued) Signal-to-Noise Ratio (Continued) dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS SECOND HARMONIC dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS MHz9, dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS THIRD HARMONIC dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS MHz9, dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS MHz-250 dBFS Temp Test Level AD6600AST Unit
25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C
40.5
57.5 53.5 53.5
Full Full Full Full Full Full 25°C Full 25°C Full Full Full Full Full
Full Full Full Full Full Full 25°C Full 25°C Full Full Full Full Full Full
REV.
AD6600 SPECIFICATIONS (continued)
Parameter WORST OTHER SPUR (4th Higher) dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Temp Test Level AD6600AST Unit
Full Full Full Full Full Full 25°C Full 25°C Full Full Full Full
74.5 66.5
NOTES AIN, AIN/BIN, BIN: AD6600 analog inputs unconditionally stable guarantee proper operation over MHz-250 specified operating range. Circuit board layout critical this device, proper layout must employed achieve specified results. Analog Input Bandwidth determined internal track-and-hold. front-end attenuators have bandwidth GHz. Measured real imaginary values using Network Analyzer. Full-scale gain tolerance typical variation gain given input frequency. nominal value full-scale input power function frequency shown previous specification. Full-scale gain tolerance measured analog input referenced nominal full-scale input power. gain measurement test, input signal level dBFS. Tuning port bandwidth MHz. Main channel full-scale input power. Diversity channel swept from dBFS dBFS. Measurement includes thermal quantization noise analog input. Tuning port bandwidth MHz. Test tones 160.05 170.05 MHz. Measurements dFBS, dBFS, dBFS highest attenuation mode, RSSI 101. Each gain-range checked from RSSI trip point (not hysteresis); nominally dBFS (RSSI 100), dBFS (RSSI 011), dBFS (RSSI 010), dBFS (RSSI 001). Measurement dBFS lowest attenuation mode, RSSI 000. Specifications subject change without notice.
REV.
AD6600
ABSOLUTE MAXIMUM RATINGS
Parameter ELECTRICAL AVCC Voltage DVCC Voltage Analog Input Voltage2 Analog Input Current2 Digital Input Voltage3 Output Current4 Resonant Port Voltage5 ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, sec) Storage Temperature Range (Ambient)
AVCC AVCC AVCC
Unit
EXPLANATION TEST LEVELS Test Level
100% Production Tested.
100% Production Tested 25°C guaranteed design characterization temperature extremes. Parameter guaranteed design characterization testing. Parameter typical value only.
ORDERING GUIDE
+150
Model AD6600AST
Temperature Package Range Description -40°C +85°C (Ambient)
Package Option
NOTES Absolute maximum ratings limiting values applied individually, beyond which serviceability circuit impaired. Functional operability necessarily implied. Exposure absolute maximum rating conditions extended period time affect device reliability. Pins AIN, AIN, BIN, BIN. Pins ENC, ENC, A_SEL, B_SEL. Pins D10:0, RSSI2:0, AB_OUT, Pins FLT, FLT. Typical thermal impedance (44-lead LQFP); 16°C/W, 55°C/W.
AD6600ST/PCB
44-Terminal LQFP ST-44 (Low-Profile Quad Plastic Flatpack) Evaluation Board with AD6600AST
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD6600 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD6600
FUNCTION DESCRIPTIONS
Number 35-43
Name DVCC AVCC RSSI[2:0] B_SEL, A_SEL FLT, AB_OUT D1-D9
Function Digital Digital Outputs. Ground. Internal Bias Point. Bypass 0.01 GND. Power Supply. RSSI Digital Output Bits. Mode Select Pins Analog Input Channel Sampling. True Analog Input Channel Complementary Analog Input Channel Resonant Filter Pins External Noise Filter. Complementary Analog Input Channel True Analog Input Channel Complementary Encode Input. True Encode Input. Clock Output Used Clocking Digital Filter Chips. Digital Output Flag Indicating Whether Output Input (High) (Low). Digital Data Output (Least Significant Bit)* Digital Data Output Bits* Digital Data Output (Most Significant Bit)*
*Digital Outputs (D10:D0) Two's Complement Format.
CONFIGURATION
(MSB)
DVCC AVCC RSSI2 RSSI1 RSSI0 B_SEL A_SEL
AVCC AVCC AVCC AVCC
IDENTIFIER
(LSB)
DVCC AVCC
AD6600
VIEW (Not Scale)
AB_OUT CLK2 AVCC
REV.
AD6600
DEFINITIONS SPECIFICATIONS Analog Bandwidth Full-Scale Gain Tolerance
Unit-to-unit variation full-scale input power.
Full-Scale Input Power
analog input frequency which spectral power fundamental frequency determined analysis) reduced bandwidth determined internal track-and-hold when filter node resonated.
Aperture Delay
Expressed dBm. Computed using following equation: 2FULL SCALE INPUT 0.001
delay between point rising edge ENCODE command instant which analog inputis sampled.
Aperture Uncertainty (Jitter)
PowerFULL SCALE
sample-to-sample variation aperture delay.
Attenuator 3OIP
Gain Matching (Input A:B)
Variation full-scale power between inputs.
Harmonic Distortion,
third order intercept point front AD6600. point which third order products would theoretically intercept input signal level input level could increase without bounds. This measured using within AD6600 while input stimulated with dual tones minimum attenuation (i.e., maximum gain) range.
Channel Isolation
ratio signal amplitude value second harmonic component, reported dBc.
Harmonic Distortion,
ratio signal amplitude value third harmonic component, reported dBc.
Integral Nonlinearity
amount signal leakage from channel next when channel driven with full-scale input, other channel swept from dBFS dBFS with frequency offset. leakage measured side with smaller signal.
Differential Analog Input Resistance, Differential Analog Input Capacitance Differential Analog Input Impedance
deviation transfer function from reference line measured fractions using "best straight line" determined least square curve fit.
Minimum Conversion Rate
encode rate which lowest analog signal frequency drops more than below guaranteed limit.
Maximum Conversion Rate
real complex impedances measured each analog input port. resistance measured statically capacitance differential input impedances measured with network analyzer.
Differential Analog Input Voltage Range
encode rate which parametric testing performed.
Noise (For Range Within ADC)
-SNR -Signal dBFS
peak-to-peak differential voltage that must applied converter generate full-scale response. Peak differential voltage computed observing voltage single subtracting voltage from other pin, which degrees phase. Peak-to-peak differential computed rotating inputs phase degrees taking peak measurement again. difference then computed between both peak measurements.
Differential Nonlinearity
VNOISE 0.001
where: Signal
input impedance, full-scale device frequency question, value particular input level, signal level within reported below full scale. This value includes both thermal quantization noise.
deviation code width from ideal step.
Differential Resonant Port Resistance
Range-Range Gain Tolerance
resistance shunted across resonant port (nominally Used determine filter bandwidth gain that stage.
Encode Pulsewidth/Duty Cycle
gain error RSSI attenuator ladder from range next.
Range-Range Phase Tolerance
phase error RSSI attenuator ladder from range next.
Differential Resonant Port Capacitance
Pulsewidth high minimum amount time that ENCODE pulse should left logic state achieve rated performance; pulsewidth minimum time ENCODE pulse should left state. timing implications changing tENCH text. given clock rate, these specifications define acceptable Encode duty cycle.
capacitance between resonant pins. Used determine filter bandwidth resonant frequency.
-10-
REV.
AD6600
RSSI Gain Step AD6600 TRANSFER FUNCTION
input amplitude span between taps RSSI (received signal strength) attenuator ladder. Ideally each stage should span input power.
RSSI Hysteresis
amount movement RSSI switch points, depending direction approach. Hysteresis prevents unnecessary RSSI toggling when input signal power near threshold.
Signal-to-Noise Ratio (Without Harmonics)
-100 LEVEL dBFS
ratio signal amplitude (set below full scale) value other spectral components, excluding first five harmonics
Worst Other Spur
ratio signal amplitude value worst spurious component (excluding second third harmonic) reported dBc.
Figure Input Power
REV.
-11-
AD6600
EQUIVALENT CIRCUITS
AVCC
AVCC VREF GAIN GAIN STAGE
EXTERNAL FILTER
AVCC
AVCC
ATTENUATOR STAGE
EQUIVALENT INPUT SHOWN ONLY
AVCC
FROM GAIN STAGE
Figure Analog Input Stage (Channel Shown; Channel Equivalent)
Figure Resonant Noise Filter) Port
AVCC
AVCC ISEL_A ISEL_B
AVCC
AVCC
AVCC
AVCC
A_SEL BIAS
B_SEL
ENCODE TIMING CIRCUITS
ENCODE
Figure A_SEL, B_SEL Input Mode Pins
Figure Encode Inputs
DVCC
DVCC
CURRENT MIRROR
CURRENT MIRROR
DVCC VREF VREF D10-D0 RSSI [2:0]
DVCC
CLK2 AB_OUT
CURRENT MIRROR
CURRENT MIRROR
Figure Digital Outputs
Figure CLK2 AB_OUT Outputs
-12-
REV.
AD6600
AD6600 TIMING DIAGRAMS
tENCH
ENCODE
tENCL
tENC
tCF1
CLK2 CLK2
tCR1 tCLK2
tCF2
CLK2
tCR2 tCLK2
tCLK2
tCLK2 tCLK2
tCLK2
CLK2
CLK2
CLK2
[10:0] RSSI [2:0]
1_DRL
1_DFL
AB_OUT
1_ARL
1_AFL
Figure Encode CLK2
Delays CLK2
Propagation Delays
tENCH
ENCODE
tENCL
tENC
tCF1
CLK2 CLK2
tCR1 tCLK2
tCF2
CLK2
tCR2 tCLK2
tCLK2
tCLK2 tCLK2
tCLK2
CLK2
CLK2
CLK2
tH_D2
[10:0] RSSI [2:0]
tS_D2
tH_D2
tS_D2
tH_A2
tS_A2
tH_A2
tS_A2
AB_OUT
Figure CLK2
Setup-and-Hold Time Characteristics
tENCH
ENCODE ENCODE
tENCL
ENCODE
tENC
ENCODE
tCF1
CLK2 CLK2
tCR1 tCLK2
tCF2
CLK2
tCR2 tCLK2
tCLK2
tCLK2 tCLK2
tCLK2
CLK2
CLK2
CLK2
tEN_DFL tEN_DRL
[10:0] RSSI [2:0]
tEN_AFL
tEN_ARL
AB_OUT
Figure Encode CLK2
Delays Encode Propagation Delays
REV.
-13-
AD6600
tENCH
ENCODE ENCODE
tENCL
ENCODE
tENC
ENCODE
tCF1
CLK2 CLK2
tCR1 tCLK2
tCF2
CLK2
tCR2 tCLK2
tCLK2
tCLK2 tCLK2
tCLK2
CLK2
CLK2
CLK2
tH_DEN
[10:0] RSSI [2:0]
tS_DEN
tH_DEN
tS_DEN
tH_AEN
AB_OUT
tS_AEN
tH_AEN
tS_AEN
Figure Encode Setup-and-Hold Time Characteristics
CLK2
[10:0] RSSI [2:0] AB_OUT
Figure Typical Output Rise Fall Times
ENCODE
CLK2
Figure Encode MSPS, Duty Cycle
ENCODE CLK2
Figure Encode MSPS, Duty Cycle
-14-
REV.
AD6600
NOISE FILTER 0dB, -12dB, -24dB RESONANT PORT
ATTEN
AB_OUT GAIN
DETECT PEAK RSSI
ANALOG
+12, +18dB GAIN
ENCODE
CONVERTER TWO'S COMPLEMENT
RSSI
GAIN
D10-D0
RSSI
RSSI [2:0]
SELECT GAIN ENCODE
ATTEN
0dB, -12dB, -24dB
AD6600
TIMING
CLK2
A_SEL
B_SEL
AVCC
DVCC
Figure Functional Block Diagram
THEORY OPERATION
AD6600, dual-channel, gain-ranging integrates analog circuitry with high speed data conversion. Each analog input stage GHz, phase-compensated step attenuator; step size each attenuator Both input stages drive analog multiplex function followed gain amplifier. simple noise filter output gain amplifier required resonate desired This resonant filter port precedes wide input bandwidth (450 MHz) track-and-hold followed 11-bit analog-to-digital converter (ADC). high speed synchronous peak detector monitors signal strength both input channels. peak detector drives RSSI circuitry that automatically adjusts attenuation gain clock-by-clock basis. three RSSI indicator bits eleven bits available output providing exponent mantissa data format. Together these integrated components form sampling, high dynamic range system. helpful view this device stand-alone using automatic gain control. gain control referred this data sheet "gain-ranging" works maintain constant over wide range possible.
12dB WINDOW
Figure Gain-Ranging
AD6600 SUBCIRCUITS Input Step Attenuator Gain Stage
stated previously, AD6600 floating-point output: eleven mantissa bits three exponent bits. shown Figure lowest input levels increases increase input power. this range, AD6600 maximum gain. However, when input signal level reaches gain-ranging section (approximately dBFS), contained between about between including effects hysteresis. Although Figure does indicate there slight differences between from gain range next gain switches between Once final RSSI range been exceeded (approximately dBFS), again increases input power increase until converter full scale reached. Again, this performance very much like effects typical analog loop.
REV.
AD6600 identical input attenuators, Channel Channel These dual inputs typically used diversity channels also process independent signals. maximum oversampling device used single channel mode; this case only input channel required. attenuator steps attenuator settings based decisions RSSI stage (see Peak Detector/ RSSI section). outputs attenuators connect analog multiplexer that selects either Channel subsequent processing (see Input Mode). selected signal drives dual-gain amplifier either selected gain also determined RSSI stage. Therefore, based possible combinations attenuation gain, input signal receives voltage gain steps (Table Overall gain-matching typically within With bandwidth GHz, phase delay through front-end ranges from degrees degrees, depending input frequency. Additionally, input impedance does change with attenuator settings there AM-to-PM distortion. -15-
dBFS
AD6600
Table Attenuator Gain Settings Encoder
Attenuator
Gain
Total
RSSI Word
After calibration period complete (one clock cycle), appropriate gain attenuator settings determined set. Once settled, internal track-and-hold freezes input signal that encoder digitize signal. During digitization, peak detector/RSSI circuitry already looking next sample. When AD6600 dual channel mode, process interleaved: while Channel monitored signal strength, Channel digitized. This allows RSSI update clock-by-clock basis.
ENCODE DIGITIZE DATA T-AND-H HOLD T-AND-H TRACK DIGITIZE T-AND-H HOLD
High-Speed Peak Detector RSSI Circuitry
peak detector along with attenuator dual gain amplifier form control loop within AD6600. peak detector designed follow analog input clock cycle before conversion actually made. Therefore, while converter section AD6600 converting sample "n," peak detector already looking sample "n+1." While looking "n+1" sample (the calibration period), peak detector examines envelope input signal. more envelope that tracked, more accurate gain setting. very least, peak detector must presented either positive negative sinusoidal peak, which represents about one-half sine wave cycle. Since peak detector works complete cycle prior conversion, absolute minimum frequency that determined twice sample rate channel. Therefore, MSPS, minimum frequency that sampled would MHz. Note that more cycles input that monitored peak detector, more accurate gain setting will Therefore, actual minimum frequency recommended higher than this. minimum specified frequency MHz. Since RSSI control loop performed sample-by-sample basis, AD6600 very accurately follows signals into deep fade.
Hysteresis
INPUT
INTERNAL CLOCK RSSI CAL.
RSSI CALIBRATION
RSSI
AMPLIFIER CONTROL
NOISE FILTER DISCHARGE
NOISE FILTER SETTLING
INPUT
CLAMPED NOISE FILTER SETTLING
Figure Internal Timing
Figure shows internal timing chip. encode applied device initiates several actions. first most important that track-and-hold placed hold, thus sampling analog input that instant. second action that peak detector RSSI circuitry initialized. During this period, analog input envelope monitored determine signal power. AD6600 calibration mode about onequarter encode period. While AD6600 calibration, external noise filter discharged amplifier driving filter disabled. Since this filter shared between input channels dual channel mode, this greatly reduces feedthrough between channels that would otherwise exist. One-quarter encode period after calibration complete, amplifier re-enabled allowed settle signal conditions sampling wideband next encode signal. final action that signal resonant port sampled track-and-hold. This happens next rising edge encode.
Input Mode Select
AD6600 employs hysteresis prevent gain-ranging from unnecessarily changing when signal envelope near RSSI threshold. hysteresis digital will account exactly shift, depending whether signal increasing decreasing. This effect shown dashed lines overall transfer function, Figure
External Noise Filter, Resonant Port
output attenuator/gain stage drives wide bandwidth track-and-hold (T/H), followed encoder. Because attenuator/gain stage very wide bandwidth GHz), filter "resonant port" provided limit amount wideband noise delivered ADC. simple filter does provide signal selectivity should typically wide. However, because ADC's track-and-hold itself wide bandwidth (~450 MHz), this noise-limiting filter critical meeting overall sensitivity. Specific details selecting components resonant port provided later text (Understanding External Analog Filter).
AD6600 operating modes: single channel dual channel. single channel mode, always samples Channel always samples Channel dual channel mode, converter sampling Channel Channel alternating Encode cycles. control pins provided select desired mode operation. A_SEL B_SEL arbitrate selection these input channels connected output. Table shows truth table selection input.
-16-
REV.
AD6600
Table Selecting AD6600 Operating Mode Table 16-Bit, Fixed-Point Data Format
Mode Dual: Single: Single: Valid
A_SEL
B_SEL
Output Encode Clock
RSSI
11-Bit Word DATA DATA DATA DATA DATA DATA
16-Bit Data Format
Corresponds Shift Right
A_SEL B_SEL logic inputs should tied directly ground analog analog). dual channel mode, AB_OUT signal indicates which input currently available digital output. When AB_OUT digital output digitized version Channel Likewise, when AB_OUT Channel available digital output (Table III).
Table III. AB_OUT Dual Channel Operation
When mated with AD6620, Digital Receive Processor Chip, AD6600 floating point data (mantissa exponent) automatically converted 16-bit two's complement format AD6620.
APPLYING AD6600 Encoding AD6600
A_SEL B_SEL D[10:0], RSSI[2:0] AB_OUT
Data Output Stage
Output Data Encode Clock
output stage provides data form mantissa, D[10:0], exponent, RSSI[2:0], where D[10:0] represents output 11-bit coded two's complement, RSSI[2:0] represents gain-range setting coded offset binary. Table shows nominal gain-ranges nominal differential full-scale input. Keep mind that actual full-scale input voltage power will vary with input frequency.
Table Interpreting RSSI Bits
AD6600 encode signal must high quality, extremely phase noise source prevent degradation performance. Digitizing high frequency signals range MHz-250 MHz) places premium encode clock phase noise. performance easily degrade dB-4 with input signals when using high-jitter clock source. higher MHz), with high-jitter clock sources, higher slew rates input signals reduce performance even further. AN-501, Aperture Uncertainty System Performance complete details. optimum performance, AD6600 must clocked differentially. encode signal usually ac-coupled into pins transformer capacitors. These pins biased internally require additional bias. Figure shows preferred method clocking AD6600. sine source (low jitter) converted from single-ended differential using transformer. back-to-back Schottky diodes across transformer secondary limit clock excursions into AD6600 approximately differential. This helps prevent larger voltage swings clock from feeding through other portions AD6600, limits noise presented encode inputs. crystal clock oscillator also used drive transformer appropriate limiting resistor (typically placed series with primary.
T1-1T SINE SOURCE ENCODE
Differential Analog Input Voltage p-p) 0.25 0.125 0.25 0.0625 0.125 0.03125 0.0625 0.03125
RSSI [2:0] Decimal Binary Equiv.
Attenuation Gain (dB)
digital processing chip which follows AD6600 combine bits two's complement data with RSSI bits form 16-bit equivalent output word. Table explains RSSI data interpreted when using ASIC. Basically, circuit performs right shifts data depending RSSI word. This also performed software using following pseudo code fragment: (rssi); r2-r0; (adc); bits, justified into word) rshift (arithmetic shift extend sign bit) result shifted data 16-bit fixed-point word that used normal 16-bit word.
AD6600
ENCODE 5082-2810 DIODES
Figure Transformer-Coupled Sine Source
REV.
-17-
AD6600
jitter ECL/PECL clock available, another option ac-couple differential ECL/PECL signal encode input pins shown Figure
ENCODE ECL/ PECL
When general purpose gain blocks used, matching easily achieved using transformer. Most gain blocks available with input output ports. Thus matching impedance AD6600 requires only (impedance ratio) transformer shown Figure
FROM MIXER OUTPUT
AD6600
ENCODE
GAIN BLOCK
AD6600
Figure Transformer-Coupled Gain Block
Figure AC-Coupled ECL/PECL Encode
Driving Analog Inputs
with most high-speed, high dynamic range analog-to-digital converters, analog input AD6600 differential. Differential inputs allow much improvement performance on-chip signals processed through attenuation gain stages. Most improvement result differential analog stages having high rejection even-order harmonics. There also benefits level. First, differential inputs have high common-mode rejection stray signals such ground power noise. They also provide good rejection common-mode signals such local oscillator feedthrough. Driving differential analog input introduces some challenges. Most RF/IF amplifiers single-ended obviously interface AD6600. However, using simple techniques, clean interface possible. recommended method drive analog input port shown Figure AD6600 input actually designed match easily filter such SAWTEK 855297. This allows filter used differential mode, which often improves operations filter. Using network analyzer data both filter output AD6600 input ports (see data tables AD6600 data), conjugate match used maximum power transfer. Often adequate match achieved simply using shunt inductor make port look real (Figure 20). more details exactly match networks, Circuit Design Chris Bowick, ISBN: 0-672-21868-2.
FROM MIXER OUTPUT
rare case that better matching required, conjugate match between amplifier selected transformercoupled analog input achieved placing matching network between amplifier transformer (Figure 22). more details matching, reference mentioned previously more details.
FROM MIXER OUTPUT MATCHING NETWORK GAIN BLOCK
AD6600
Figure Gain Block Matching Network
Understanding External Analog Filter
primary trade-offs must made when designing external resonant filter. obvious bandwidth filter. second, obvious, trade-off settling time filter nodes. Resonant Filter Bandwidth determines amount noise that limited center frequency chosen. resonant filter wide, little noise improvement seen. resonant filter narrow, amplitude variation seen tolerance filter components. narrow filter center these tolerances drift), signal will fall transition band filter. optimum starting point this filter approximately MHz. Resonant Filter Settling limits amount capacitance this filter. output amplifier clamped when processing input (encode high time). This prevents output from feeding through (T/H) corrupting results. But, upon falling edge encode, must come clamp present accurate signal T/H. external filter determines settling amp. output does settle, sees attenuated signal. obviously, narrow bandwidth desired improve noise performance; filter narrow, will settle will attenuated signal. Figure shows simplified model amplifier. point note that resistor values collector legs nominal with tolerance 20%. filter performance determined these values conjunction with internal parasitic capacitance, board parasitics external filter components.
AD6630
AD6600
Figure Cascaded Filters with AD6630
Where gain required, AD6630 differential, noise, gain block recommended. This amplifier provides gain provides limiting prevent damage filter AD6600. AD6630 designed reside between filters. This noise device ideally suited many applications AD6600. more information AD6630, reference AD6630 data sheet.
-18-
REV.
AD6600
AVCC RESONANT FILTER PORT FROM GAIN STAGE CLAMP
settling purposes, with MSPS encode duty cycle, maximum allowable capacitance proper settling CTOTAL 13.6 stated above, this CTOTAL includes external capacitors, board parasitics, AD6600 parasitics. parasitics AD6600 (lead, internal bond internal connections) 1.75 0.35 (differential). resistors maximum value (315 20%), maximum allowable capacitance CTOTAL 11.3 duty cycle less than 50%, maximum allowable capacitance further decreased allow settling.
Power Supplies
ENCODE
Figure Amplifier Clamp Circuitry
Figure shows settling important this circuit. does settle (come clamp), amplitude presented will decreased. This results decreased gain when filter capacitance high.
ENCODE HOLD TRACK HOLD
Care should taken when selecting power source. Linear supplies strongly recommended. Switching supplies tend have radiated components that "received" AD6600. Each power supply pins should decoupled closely package possible using chip capacitors. AD6600 separate digital analog power supply pins. analog supplies denoted AVCC digital supply pins denoted DVCC. Although analog digital supplies tied together, best performance achieved when supplies separate. This because fast digital output swings couple switching current back into analog supplies. Note that AVCC must held within Volts; however, DVCC supply varied according output digital logic family. AD6600 specified DVCC this common supply digital ASICS.
Output Loading
RESONANT FILTER
CLAMPED
SETTLING
Figure Amplifier Settling
This explains total capacitance allowed external filter varies depending clock rate (actually encode clock high time). encode MSPS duty cycle 50%, allowable settling time 38.5 (1/2 encode time). assumption that should allowed settle this time period. This been proven with both simulation empirical analysis. settling assumed circuit, then: time; number bits
Care must taken when designing data receivers AD6600. Note from equivalent circuits shown earlier (see Equivalent Circuits) that D[10:0] RSSI[2:0] contain output series resistor. minimize capacitive loading, there should only gate each output pin. Extra capacitive loading will increase output timing invalidate timing specifications. AB_OUT contain output series resistors. Testing digital output timing performed with loads.
Layout Information
schematic evaluation board (Figure represents typical implementation AD6600. multilayer board recommended achieve best results. highly recommended that high quality, ceramic chip capacitors used decouple each supply ground directly device. pinout AD6600 facilitates ease implementation high frequency, high resolution design practices. digital outputs segregated sides chip, with inputs opposite side isolation purposes. Care should taken when routing digital output traces. prevent coupling through digital outputs into analog portion AD6600, minimal capacitive loading should placed these outputs. recommended that fanout only used AD6600 digital outputs. layout analog inputs external resonant filter critical. digital traces must routed near, under, above these portions circuit. transformers used coupling into analog inputs must located close possible analog inputs AD6600. external resonant filter components must physically close filterinput pins, separated from analog inputs. -19-
CTOTAL
(TENCODE 0.5) 38.5 13.6 (8192) (8192)
this case, CTOTAL includes parasitics external capacitance. nominally 8192 2048), which converter bits, 2048).
REV.
AD6600
layout Encode circuit equally critical. noise received this circuitry will result corruption digitization process lower overall performance. Encode clock must isolated from digital outputs analog inputs.
Evaluation Board
evaluation board AD6600 straightforward, containing required circuitry evaluating device. only external connections required power supplies, clock analog inputs. evaluation board includes option on-board, clock oscillator encode. Power analog supply pins AD6600 connected power terminal block (TB1). Power digital interface supplied J201, e-hole located adjacent J201. supply vary between sets level output digital data (J201). J201 connector mates directly with AD6620 (Receive Signal Processor) evaluation board, Part AD6620S/PCB, allowing complete evaluation system performance. analog inputs connected connectors BIN, which transformer-coupled AD6600 inputs. transformers have turns-ratio match input resistance AD6600 (200 connectors.
Encode signal generated using on-board crystal oscillator, U100. on-board crystal used, R104 must removed from board prevent loading oscillator's output. on-board oscillator replaced external encode source connector labeled ENCODE. external source used, must high quality very phase noise source. high range AD6600 -250 MHz) demands that Encode clock sufficiently pure maintain performance. AD6600 output data latched using 74LCX574 (U201, U202) latches. clock these latches determined jumper selection header clock delayed version encode clock (CLKA, CLKB), generated AD6600. clock also distributed with output data (J201) that labeled CLKX (Pin J201). selected with jumpers header CLKA, CLKB, resonant filter components (SEL2, omitted. user must install proper values based chosen. Understanding External Analog Filter section data sheet guidelines selecting these components.
Table AD6600ST/PCB Bill Material
Item
Quantity
Reference AIN, BIN, ENCODE C102-108, C114, C117-118, C120-121, C299 C100-101 C111 C112-C113, C115-116 CR1-2 J201 R1-2 R100-R101 R103 R104 R298-R299 T1-T2, U201-U202 U204
Description Connector Ceramic Chip Capacitor 1206, Tantalum Chip Capacitor, Ceramic Chip Capacitor 0805, Ceramic Chip Capacitor 0508, 1N2810 Schottky Diode AD6600AST 20-Pin Double Male Header 50-Pin Double Male Header, Right Angle Omitted Surface Mount Resistor 1206, Surface Mount Resistor 1206, Surface Mount Resistor 1206, Surface Mount Resistor 1206, Surface Mount Transformer Mini-Circuits T4-1T PCTB2 Terminal Block 74LCX574 Octal Latch 74LVQ00 Input NAND Gate
-20-
REV.
(MSB)
C111 DVCC AVCC RSSI2 RSSI1 RSSI0 B_SEL AVCC AVCC AVCC AVCC AVCC A_SEL CLK_2 AB_OUT AVCC DVCC
C112 0.01
(LSB)
REV.
CLKX CLKA CLK_2X CLKB CLKB CLKA 1N2810 C113 0.01 1N2810 H20DM RSSI0 RSSI1 RSSI2 U201 74LCX574 U202 74LCX574 BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 CLKX BIT2 BIT1 BIT0 RSSIB2 RSSIB1 RSSIB0 H50DM J201 REMOVE
CLKREF
TI-4T
R103
U100
K1115
C114
ENCODE
R104
Figure AD6600ST/PCB Schematic Diagram
AD6600AST
CLK2X RSSI2 RSSI1 RSSI0 T1-4T CLKREF R299 C100 C102 C104 C106 C108 C120 C121 C299 C116 0.01 R298 U204 74LVQ00 SEL2 C118 U204 74LVQ00 PCTB2
-21-
R100
R101
TI-4T
BIT7 BIT8 BIT9 BIT10 RSSIB2 RSSIB1 RSSIB0
C115 0.01
U204 74LVQ00 CLKA U204 74LVQ00
AD6600
C101
C103
C105
C107
C117
AD6600
Figure AD6600ST/PCB Side Silk Screen
Figure AD6600ST/PCB Side Copper
Figure AD6600ST/PCB Power Supply Layer (Negative)
Figure AD6600ST/PCB Bottom Side Copper
Figure AD6600ST/PCB Ground Layer (Negative)
-22-
REV.
AD6600
Connecting AD6600 with AD6620
AD6600 interfaces directly AD6620 Digital Receive Signal Processor shown Figure additional external components required. Note that layout requirements discussed previously apply deviations result degraded performance. digital outputs AD6600 must connect directly AD6620 inputs with additional fanout. Additional loading outputs will compromise timing performance.
(MSB) AD6600 (LSB) IN15 IN14 IN13 IN12 IN11 IN10 EXP2 EXP1 EXP0
Figure shows timing details between AD6600 AD6620. Clock D[10:0], RSSI[2:0], AB_OUT captured AD6620. Since AB_OUT changed state from previous clock, D[10:0] RSSI[2:0] processed AD6620. This clock allows adequate setup hold time AB_OUT, D[10:0], RSSI[2:0] captured AD6620. Clock2, D[10:0], RSSI[2:0], AB_OUT captured AD6620. Since AB_OUT changed from previous clock, D[10:0] RSSI[2:0] ignored AD6620. This clock concerned only with AB_OUT setupand-hold time.
AD6620
RSSI2 RSSI1 RSSI0 AB_OUT CLK2
Figure AD6600/AD6620 Connections
38.5 CLK2
38.5
CLOCK1 [10:0] RSSI [2:0] 16.5
CLOCK2 16.5
12.5 AB_OUT
Figure AD6600 AD6620 Timing MSPS
REV.
-23-
AD6600
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
0.063 (1.60) 0.030 (0.75) 0.018 (0.45)
0.472 (12.00)
SEATING PLANE VIEW
(PINS DOWN)
0.394 (10.0)
0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
0.031 (0.80)
0.018 (0.45) 0.012 (0.30)
-24-
REV.
PRINTED U.S.A.
C00966-2.5-7/00 (rev.
44-Terminal LQFP (Low-Profile Quad Plastic Flatpack) (ST-44)

Dual Channel, Gain-Ranging with RSSI AD6600 input channels, each

Top Searches for this datasheet

Other recent searches