OUT1 -IN1 +IN1 Line Driver with Power-Down AD8019 CONFIGURAT

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OUT1 -IN1 +IN1 Line Driver with Power-Down AD8019 CONFIGURAT

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FEATURES Distortion, High Output Current Amplifiers Operate from Power Supplies, Ideal High-Performance ADSL CPE, xDSL Modems Power Operation mA/Amp (Typ) Supply Current Digital (1-Bit) Power-Down Voltage Feedback Amplifiers Distortion Out-of-Band SFDR into Line High Speed Bandwidth dB), Slew Rate High Dynamic Range VOUT within Power Supply APPLICATIONS ADSL, VDSL, HDSL, Proprietary xDSL USB, PCI, PCMCIA Modems, Customer Premise Equipment (CPE) PRODUCT DESCRIPTION 8-Lead SOIC (R-8)
OUT1 -IN1 +IN1
Line Driver with Power-Down AD8019
CONFIGURATIONS 14-Lead TSSOP (RU-14)
OUT2 -IN2 +IN2 OUT1 -IN1 +IN1 PWDN
AD8019AR
AD8019ARU
OUT2 -IN2 +IN2 DGND
CONNECT
AD8019 cost xDSL line driver optimized drive minimum into load while delivering outstanding distortion performance. AD8019 designed high-speed bipolar process enabling power supplies only. When operating from single supply highly efficient amplifier architecture typically deliver output current into impedance loads through turns ratio transformer. Hybrid designs using supplies enable turns ratio transformer, minimizing attenuation receive signal. AD8019 typically draws amplifier quiescent current. 1-bit digital power down feature reduces quiescent current approximately mA/amplifier. Figure shows typical Band SFDR performance under ADSL (upstream) conditions. SFDR measured while driving ADSL signal into line with back termination. AD8019 comes thermally enhanced 8-lead SOIC 14-lead TSSOP packages. 8-lead SOIC pin-compatible with AD8017 line driver.
10dB/DIV
-80dBc
132.5
137.5 FREQUENCY
142.5
Figure Out-of-Band SFDR; Output Power into Upstream
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2001
AD8019-SPECIFICATIONS otherwise noted.)
Parameter DYNAMIC PERFORMANCE Bandwidth Conditions
TMIN TMAX unless
Unit V/µs
Bandwidth Large Signal Bandwidth Slew Rate Rise Fall Time Settling Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Out-of-Band SFDR MTPR Input Voltage Noise Input Current Noise Crosstalk PERFORMANCE Input Offset Voltage
VOUT p-p, VOUT p-p, VOUT p-p, VOUT p-p, VOUT Noninverting, VOUT Noninverting, VOUT 0.1%, VOUT VOUT (Differential) kHz, RL(DM) kHz, RL(DM) kHz, RL(DM) kHz, RL(DM) kHz-1.1 MHz, Differential kHz-138 kHz, Differential MHz,
-0.5 -0.2 +0.1
nV/Hz pAHz
TMIN-TMAX Input Offset Voltage Match Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance +Input Bias Current TMIN-TMAX -Input Bias Current TMIN-TMAX +Input Bias Current Match TMIN-TMAX -Input Bias Current Match CMRR Input Voltage Range OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short Circuit Current1 POWER SUPPLY Supply Current/Amp TMIN-TMAX TMIN-TMAX VOUT p-p, TMIN-TMAX
-1.5 -1.8 -1.0 -1.5 -0.5 -0.8
+1.5 +1.8 +1.0 +1.5 +0.5 +0.8
SFDR into
-4.8
+4.8 10.5 14.5
Operating Range Power Supply Rejection Ratio LOGIC LEVELS tOFF PWDN Voltage PWDN Voltage PWDN Bias Current PWDN Bias Current
PWDN TMIN-TMAX PWDN Dual Supply +1.0 -1.0 VPWDN MHz,
-100
NOTES This device protected from overheating during short-circuit thermal shutdown circuit. Specifications subject change without notice.
REV.
AD8019
Parameter DYNAMIC PERFORMANCE Bandwidth
TMIN TMAX unless otherwise noted.)
Conditions VOUT VOUT VOUT VOUT Noninverting, VOUT Noninverting, VOUT 0.1%, VOUT VOUT (Differential) kHz, RL(DM) kHz, RL(DM) kHz, RL(DM) kHz, RL(DM) kHz-500 kHz, Differential kHz-138 kHz, Differential MHz, Unit V/µs
Bandwidth Large Signal Bandwidth Slew Rate Rise Fall Time Settling Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Out-of-Band SFDR MTPR Input Voltage Noise Input Current Noise Crosstalk PERFORMANCE Input Offset Voltage
-0.5 -0.2 +0.2 +0.1
nV/Hz pAHz
TMIN-TMAX Input Offset Voltage Match Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance +Input Bias Current TMIN-TMAX -Input Bias Current TMIN-TMAX +Input Bias Current Match TMIN-TMAX -Input Bias Current Match CMRR Input Voltage Range OUTPUT CHARACTERISTICS Output Resistance Output Voltage Swing Output Current Short Circuit Current1 POWER SUPPLY Supply Current/Amp TMIN-TMAX TMIN-TMAX VOUT p-p, TMIN-TMAX
-3.8 -1.5 -1.7 -1.0 -2.4 -1.0 -2.5
+3.8 +1.5 +1.7 +1.0 +2.4 +1.0 +2.5
SFDR into
-10.8
+10.8 11.5 1.75
Operating Range Power Supply Rejection Ratio LOGIC LEVELS tOFF PWDN Voltage PWDN Voltage PWDN Bias Current PWDN Bias Current
PWDN High TMIN-TMAX PWDN Dual Supply +1.0 -1.0 VPWDN MHz,
-100
NOTES This device protected from overheating during short-circuit thermal shutdown circuit. Specifications subject change without notice.
REV.
AD8019
ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION
Supply Voltage 26.4 Internal Power Dissipation TSSOP-14 Package2 SOIC-8 Package3 Input Voltage (Common-Mode) Differential Input Voltage Output Short Circuit Duration Observe Power Derating Curves Storage Temperature Range -65°C +125°C Operating Temperature Range -40°C +85°C Lead Temperature Range (Soldering sec) 300°C
NOTES Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Specification device four-layer board with inches copper 85°C 14-lead TSSOP package: 90°C/W. Specification device four-layer board with inches copper 85°C 8-lead SOIC package: 100°C/W.
maximum power that safely dissipated AD8019 limited associated rise junction temperature. maximum safe junction temperature plastic encapsulated device determined glass transition temperature plastic, approximately 150°C. Temporarily exceeding this limit cause shift parametric performance change stresses exerted package. output stage AD8019 designed maximum load current capability. result, shorting output common cause AD8019 source sink ensure proper operation, necessary observe maximum power derating curves. Direct connection output either power supply rail destroy device.
MAXIMUM POWER DISSIPATION
TSSOP
SOIC
AMBIENT TEMPERATURE
Figure Plot Maximum Power Dissipation Temperature AD8019
ORDERING GUIDE
Model AD8019ARU AD8019ARU-Reel AD8019ARU-EVAL AD8019AR AD8019AR-Reel AD8019AR-EVAL
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Package Description 14-Lead TSSOP 14-Lead TSSOP Evaluation Board 8-Lead SOIC 8-Lead SOIC Evaluation Board
Package Option RU-14 RU-14 Reel ARU-EVAL Reel EVAL
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD8019 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
Typical Performance Characteristics-AD8019
49.9 VOUT +VIN -VIN
Single-Ended Test Circuit;
Differential Test Circuit;
VOUT
VOLTS
-100 -100
TIME
-100 -100
TIME 100ns/DIV
Step Response; Single-Ended
Step Response; Single-Ended
VOUT Volts VOUT Volts
-100
-100
TIME
TIME
Step Response; Single-Ended
Step Response; Single-Ended
REV.
AD8019
DISTORTION
DISTORTION
-100 0.01
FREQUENCY
-100 0.01
FREQUENCY
Distortion Frequency; Differential,
Distortion Frequency; Differential,
HARMONIC HARMONIC
DISTORTION
DISTORTION
-100
-100
PEAK OUTPUT CURRENT
DIFFERENTIAL OUTPUT VOLTAGE
Distortion Peak Output Current; kHz; Single-Ended; Second Harmonic
Distortion Output Voltage; kHz, +10, Differential
DISTORTION
DISTORTION
HARMONIC HARMONIC
-100 -110
-100
PEAK OUTPUT CURRENT
DIFFERENTIAL OUTPUT VOLTAGE
Distortion Peak Output Current; kHz; Single-Ended; Second Harmonic
Distortion Output Voltage; kHz, +10, Differential
REV.
AD8019
OUTPUT VOLTAGE
DISTORTION
-100 DIFFERENTIAL OUTPUT VOLTAGE
1000
FREQUENCY
Distortion Output Voltage; kHz, +10, Differential
Output Voltage Frequency;
DISTORTION
CMRR
0.01 VOUT
-100 -110 DIFFERENTIAL OUTPUT VOLTAGE
FREQUENCY
1000
Distortion Output Voltage; kHz, +10, Differential
CMRR Frequency;
OUTPUT SATURATION VOLTAGE Volts
OUTPUT VOLTAGE 1000
FREQUENCY 1000
LOAD CURRENT
Output Saturation Voltage Load;
Output Voltage Frequency;
REV.
AD8019
0.01 +PSRR -PSRR
CROSSTALK
PSRR
FREQUENCY
1000
-100 0.01
FREQUENCY
1000
PSRR Frequency;
Crosstalk Frequency,
PHASE Degrees
VNOISE +INOISE
GAIN PHASE
VNOISE
INOISE
-INOISE
1000
0.01
FREQUENCY
1000
0.001
0.01
FREQUENCY
Noise Frequency
Open-Loop Gain Phase Frequency
0.1%
2mV/DIV
2mV/DIV
0.1%
VOUT
VOUT
6.8pF 1.1k 1.1k VOUT
6.8pF 1.1k 1.1k VOUT
20ns/DIV
20ns/DIV
Settling Time 0.1%; VOUT
Settling Time 0.1%; VOUT
REV.
AD8019
1000
VOUT
1V/DIV VOUT 2V/DIV
OUTPUT IMPEDANCE
0.01
0.001 0.01 FREQUENCY
-200
TIME
1200
1600
Output Impedance Frequency;
Overload Recovery;
VOUT
2V/DIV VOUT 5V/DIV
VOUT
1V/DIV VOUT 2V/DIV
-100 TIME
-200
TIME
1200
1600
Overload Recovery; =100
Overload Recovery;
VOUT
2V/DIV VOUT 5V/DIV
-100
TIME
Overload Recovery;
REV.
AD8019
13dBm
MTPR
SFDR
11dBm 12dBm
13dBm
11dBm 12dBm
10dBm
10dBm TURNS RATIO
TURNS RATIO
MTPR Turns Ratio; Line
SFDR Turns Ratio; Line
18dBm
18dBm
17dBm
MTPR
17dBm 16dBm 13dBm
SFDR
16dBm 13dBm
TURNS RATIO
TURNS RATIO
MTPR Turns Ratio; Line
SFDR Turns Ratio; Line
-10-
REV.
AD8019
GENERAL INFORMATION
AD8019 voltage feedback amplifier with high output current capability. voltage feedback amplifier, AD8019 features lower current noise more applications flexibility than current feedback designs. fabricated Analog Devices' proprietary High Voltage eXtra Fast Complementary Bipolar Process (XFCB-HV), which enables construction transistors with similar region. process dielectrically isolated eliminate parasitic latch-up problems caused junction isolation. These features enable construction high-frequency, low-distortion amplifiers.
POWER-DOWN FEATURE
Figure Simplified Differential Driver
digitally programmable logic (PWDN) available TSSOP-14 package. allows user select between operating conditions, full shutdown. DGND logic reference. threshold PWDN typically above DGND. power-down feature being used, better DGND lowest potential that AD8019 tied place PWDN potential least higher than that DGND pin, lower than positive supply voltage.
POWER SUPPLY DECOUPLING
Remembering that each output device only dissipates half time gives simple integral that computes power each device: total supply power then computed PTOT
POUT
AD8019 powered with good quality (i.e., low-noise) supply anywhere range from order optimize ADSL upstream drive capability maintain best Spurious Free Dynamic Range (SFDR), AD8019 circuit should powered with well-regulated supply. Careful attention must paid decoupling power supply. High quality capacitors with equivalent series resistance (ESR) such multilayer ceramic capacitors (MLCCs) should used minimize supply voltage ripple power dissipation. addition, MLCC decoupling capacitors should located more than inch away from each power supply pins. large, usually tantalum, capacitor required provide good decoupling lower frequency signals supply current fast, large signal changes AD8019 outputs.
POWER DISSIPATION
this differential driver, voltage output amplifier, voltage across total impedance seen differential driver, including back termination. Now, with observations integrals easily evaluated. First, integral simply square value Second, integral equal average rectified value sometimes called mean average deviation, MAD. shown that signal, value equal times value.
PTOT (0.8 rms2 POUT
AD8019 operating single supply delivering total line matching network) into 17.3 (100 reflected back through 1:1.7 transformer plus back termination), dissipated power Using these calculations 90°C/W TSSOP package 100°C/W SOIC, Tables I-IV show junction temperature versus power delivered line several supply voltages while operating with ambient temperature 85°C. shaded areas indicate operation junction temperature over absolute maximum rating 150°C, should avoided.
Table Junction Temperature Line Power Operating Voltage TSSOP
important consider total power dissipation AD8019 order properly size heat sink area application. Figure simple representation differential driver. With some simplifying assumptions estimate total power dissipated this circuit. output current large compared quiescent current, computing dissipation output devices adding quiescent power dissipation will give close approximation total power dissipation package. factor (~0.6-1) corrects slight error Class operation output stage. estimated subtracting quiescent current output stage from total quiescent current ratioing that total quiescent current. AD8019, 0.833.
PLINE,
VSUPPLY 12.5
REV.
-11-
AD8019
Table Junction Temperature Line Power Operating Voltage SOIC
VSUPPLY PLINE, 12.5
energy make circuit less susceptible interference. Adherence stripline design techniques long signal traces (greater than about inch) recommended.
Evaluation Board
AD8019 available installed evaluation board both package styles. Figures show schematics TSSOP evaluation board. receiver circuit these boards typically unpopulated. Requesting samples AD8022AR, along with either AD8019 evaluation boards, will provide capability evaluate AD8019 along with other Analog Devices products typical transceiver circuit. evaluation circuits have been designed replicate side analog transceiver hybrid circuits. circuit mentioned above designed using 1-transformer transceiver topology including line receiver, line driver, line matching network, RJ11 jack interfacing line simulators, differential inputs. AC-coupling capacitors C10, combination with resistors R25, will form order highpass pole
Transformer Selection
Table III. Junction Temperature Line Power Operating Voltage TSSOP
VSUPPLY PLINE,
Table Junction Temperature Line Power Operating Voltage SOIC
VSUPPLY PLINE,
Thermal stitching, which connects outer layers internal ground plane(s), help utilize thermal mass draw heat away from line driver other active components.
LAYOUT CONSIDERATIONS
Customer premise ADSL requires transmission signal. signal crest factor 5.3, requiring line driver provide peak line power peak line power translates into peak voltage telephone line. Assuming that maximum distortion output swing available from AD8019 line driver supply taking into account power lost termination resistance, step-up transformer with turns ratio adequate most applications. modem designer desires transmit more than down twisted pair, higher turns ratio used transformer. This trade-off comes expense higher power dissipation line driver well increased attenuation downstream signal that received transceiver. simplified differential drive circuit shown Figure AD8019 coupled phone line through step-up transformer with turns ratio. back termination line matching resistors, each (100 12)) where approximate phone line impedance. transformer reflects impedance from line side side value inversely proportional square turns ratio. total differential load AD8019, including termination resistors, Even under these conditions AD8019 provides distortion signals within power supply rails. must take care minimize capacitance present outputs line driver. sources such capacitance include, limited suppression capacitors, overvoltage protection devices transformers used hybrid. Transformers have kinds parasitic capacitances, distributed, bulk capacitance, interwinding capacitance. Distributed capacitance result capacitance created between each adjacent winding transformer. Interwinding capacitance capacitance that exists between windings primary secondary sides transformer. existence these capacitances unavoidable, specifying
case with high-speed applications, careful attention printed circuit board layout details will prevent associated board parasitics from becoming problematic. Proper design technique mandatory. should have ground plane covering unused portions component side board provide low-impedance return path. Removing ground plane layers from areas near input output pins will reduce stray capacitance, particularly area inverting inputs. signal routing should short direct order minimize parasitic inductance capacitance associated with these traces. Termination resistors loads should located close possible their respective inputs outputs. Input output traces should kept apart possible minimize coupling (crosstalk) though board. Wherever there complementary signals, symmetrical layout should provided extent possible maximize balanced performance. When running differential signals over long distance, traces should close together differential wiring should twisted together minimize area loop that formed. This will reduce radiated
-12-
REV.
AD8019
transformer, should minimize them order avoid operating line driver potentially unstable environment. Limiting both distributed interwinding capacitance less than each should sufficient most applications.
Stability Enhancements
from other subbands, regardless whether corruption comes from adjacent subband harmonics other subbands. Conventional methods expressing output signal integrity line drivers such single tone harmonic distortion THD, two-tone Intermodulation Distortion (IMD) third order intercept (IP3) become significantly less meaningful when amplifiers required process other heavily modulated waveforms. typical ADSL upstream signal contain many carriers (subbands tones) signals. Multi-Tone Power Ratio (MTPR) relative difference between measured power typical subband tone carrier) versus power another subband specifically selected contain data. other words, selected subband tone) remains open void intentional power (without signal) yielding empty frequency bin. MTPR, sometimes referred `empty test,' typically expressed dBc, similar expressing relative difference between single tone fundamentals second third harmonic distortion components. Measurements MTPR typically made line side secondary side transformer.
Voltage feedback amplifiers exhibit sensitivity capacitance present inverting input. Parasitic capacitance, small several picofarads, combination with high-impedance input create pole that dramatically decrease phase margin amplifier. case AD8019, compensation capacitor pF-20 parallel with feedback resistor will form zero that serve cancel effects parasitic capacitance. Placing series with each noninverting inputs serves isolate inputs from each other from high frequency signals that coupled into amplifier midsupply bias. also necessary configure line driver separate, noninverting amplifiers rather than single differential driver. When doing this, gain resistors share coupling capacitor minimize errors. Adhering previously mentioned layout techniques will also assistance keeping amplifier stable.
Receive Channel Considerations
transformer used output differential line driver step differential output voltage line inverse effect signals received from line. voltage reduction attenuation equal inverse turns ratio realized receive channel typical bridge hybrid. turns ratio transformer also dictated ability receive circuitry resolve low-level signals noisy twisted pair telephone plant. While higher turns ratio transformers boost transmit signals appropriate level, they also effectively reduce received signal noise ratio reduction received signal strength. Using transformer with turns ratio possible will limit degradation received signal. AD8022, dual amplifier with typical voltage noise only nV/Hz supply current mA/amplifier recommended receive channel.
Modulation, Multi-Tone Power Ratio (MTPR) Out-of-Band SFDR
POWER
FREQUENCY
Figure Waveform Frequency Domain
ADSL systems rely Discrete Multi-Tone DMT) modulation carry digital data over phone lines. modulation appears frequency domain power contained several individual frequency subbands, sometimes referred tones bins, each which uniformly separated frequency. uniquely encoded, Quadrature Amplitude Modulation (QAM)like signal occurs center frequency each subband tone. Figure example waveform frequency domain, Figure time domain waveform. Difficulties will exist when decoding these subbands signal from subband corrupted signal(s)
MTPR versus transformer turns ratio depicted TPCs covers variety line power ranging from dBm. turns ratio increases, driver hybrid deliver more undistorted power load high output current capability AD8019. Significant degradation MTPR will occur output driver swings rails, causing clipping voltage peaks. Driving signals such extremes only compromises band" MTPR, will also produce spurs that exist outside frequency spectrum containing transmitted signal. "Outof-band" spurious free dynamic range (SFDR) defined relative difference amplitude between these spurs tone upstream bins. Compromising out-of-band SFDR equivalent increasing near-end cross talk (NEXT). Regardless terminology, maintaining out-of-band SFDR while reducing NEXT will improve overall performance modems connected either twisted pair.
REV.
-13-
AD8019
Generating Signals
this time, DMT-modulated waveforms typically menu-selectable items contained within arbitrary waveform generators. Even using (AWG) software generate signals, AWGs that available today deliver signals sufficient performance with regard MTPR limitations converters output drivers used manufacturers. Similar evaluating single-tone distortion performance amplifier, MTPR evaluation requires signal generator capable delivering MTPR performance better than that driver under evaluation. Generating signals accomplished using Tektronics 2021 equipped with Option (12-/24-bit, Digital Data Out), digitally coupled Analog Devices' AD9754, 14-bit TxDAC®, buffered AD8002 amplifier configured differential driver. Note that waveforms, available Analog Devices website, www.analog.com, similar. files needed produce necessary digital data required drive TxDAC from optional Digital Data output AWG2021.
+12V
VOLTS
-0.25 -0.20 -0.15 -0.10 -0.05 TIME
0.05
0.10
0.15
0.20
Figure Signal Time Domain
POUT 16dBm
17.3
LINE POWER 13dBm
17.3 1:1.7 TRANSFORMER
Figure Recommended Application Circuit Single Supply
+12V
-12V POUT 16dBm
12.4
LINE POWER 13dBm
12.4 TRANSFORMER
Figure Recommended Application Circuit Supply
TxDAC registered trademark Analog Devices, Inc.
-14-
REV.
REV.
TP10 AD8019 TP23 TP24 *DNI INSTALL VCC-2 BEAD VCCIN BEAD TP19 TP25 TP26 VCC;8 VEE;4 TP17 AD8022 AD8019 1WATT VCC-2 TP11
Figure TSSOP Noninverting Evaluation Board Schematic
-15-
TP18 AD8022 VCC;8 VEE;4
0.01 DECOUPLING TP12
DECOUPLING
VCC-2
DECOUPLING DECOUPLING
AD8019
AD8019
PWDN DGND
AD8019
Figure Driver Input Control Circuit
Figure TSSOP Evaluation Board Silkscreen Bottom
AGND AGND
Figure TSSOP Evaluation Board Silkscreen
Figure TSSOP Evaluation Board Power Plane
-16-
REV.
AD8019
Figure Solder Mask
Figure Ground Plane Bottom
Figure Solder Mask Bottom
Figure Assembly
REV.
-17-
AD8019
Figure Ground Plane
Figure Assembly Bottom
-18-
REV.
AD8019
Figure Board Fabrication
REV.
-19-
AD8019
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
14-Lead TSSOP (RU-14)
C02551-1.5-4/01(0)
0.028 (0.70) 0.020 (0.50) 0.201 (5.10) 0.193 (4.90)
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10)
SEATING PLANE
0.0256 (0.65)
0.0118 (0.30) 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8-Lead SOIC (R-8)
0.1968 (5.00) 0.1890 (4.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.102 (2.59) 0.094 (2.39) 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
0.0500 (1.27) 0.0160 (0.41)
-20-
REV.
PRINTED U.S.A.

OUT1 -IN1 +IN1 Line Driver with Power-Down AD8019 CONFIGURAT

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