Highest-Performance Floating-Point Digital Signal Processor (DSP)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Highest-Performance Floating-Point Digital
Signal Processor (DSP): TMS320C6713 Eight 32-Bit Instructions/Cycle 32/64-Bit Data Word 225-, 150-MHz Clock Rate 4.4-, 6.7-ns Instruction Cycle Time 1800 MIPS/1350 MFLOPS, 1200 MIPS /900 MFLOPS Rich Peripheral Set, Optimized Audio VelociTI Advanced Very Long Instruction Word (VLIW) TMS320C67x Core Eight Independent Functional Units: ALUs (Fixed-Point) Four ALUs (Floating- Fixed-Point) Multipliers (Floating- Fixed-Point) Load-Store Architecture With 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Instruction Features Native Instructions IEEE Single- Double-Precision Byte-Addressable (8-, 16-, 32-Bit Data) 8-Bit Overflow Protection Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization L1/L2 Memory Architecture 4K-Byte Program Cache (Direct-Mapped) 4K-Byte Data Cache (2-Way) 256K-Byte Memory, With 64K-Byte Unified Cache/Mapped 192K-Byte Additional Mapped Device Configuration Boot Mode: HPI, 16-, 32-Bit Boot Endianness: Little Endian, Endian 32-Bit External Memory Interface (EMIF) Glueless Interface SRAM, EPROM, Flash, SBSRAM, SDRAM 512M-Byte Total Addressable External Memory Space Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels)
16-Bit Host-Port Interface (HPI) Multichannel Audio Serial Ports
(McASPs) Independent Clock Zones Each Eight Serial Data Pins Port: Individually Assignable Clock Zones Each Clock Zone Includes: Programmable Clock Generator Programmable Frame Sync Generator Streams From 2-32 Time Slots Support Slot Size: Bits Data Formatter Manipulation Wide Variety Similar Stream Formats Integrated Digital Audio Interface Transmitter (DIT) Supports: S/PDIF, IEC60958-1, AES-3 Formats transmit pins Enhanced Channel Status/User Data Extensive Error Checking Recovery Inter-Integrated Circuit (I2C) Buses Multi-Master Slave Interfaces Multichannel Buffered Serial Ports (McBSPs): Serial-Peripheral-Interface (SPI) High-Speed Interface AC97 Interface 32-Bit General-Purpose Timers Dedicated General-Purpose Input/Output Module With pins Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module IEEE-1149.1 (JTAG) Boundary-Scan-Compatible Package Options: 208-Pin PowerPAD Plastic (Low-Profile) Quad Flatpack (PYP) 256-Pin Ball Grid Array Package (GFN) 0.13-µm/6-Level Metal Process CMOS Technology 3.3-V I/Os, 1.2-V Internal
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. TMS320C67x, VelociTI, PowerPAD trademarks Texas Instruments. trademarks property their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port Boundary Scan Architecture.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Copyright 2001, Texas Instruments Incorporated
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Table Contents
PowerPAD package (top view) package (bottom view) description device characteristics functional block (DSP core) diagram (DSP core) description memory summary peripheral register descriptions PWRD bits register description interrupts interrupt selector EDMA module EDMA selector signal groups description device configurations configuration examples terminal functions development support documentation support clock generator, oscillator, absolute maximum ratings over operating case temperature range recommended operating conditions electrical characteristics over recommended ranges supply voltage operating case temperature parameter measurement information signal transition levels timing parameters board routing analysis input output clocks asynchronous memory timing synchronous-burst memory timing synchronous DRAM timing HOLD/HOLDA timing BUSREQ timing reset timing external interrupt timing multichannel audio serial port (McASP) timing inter-integrated circuits (I2C) timing host-port interface timing multichannel buffered serial port timing timer timing general-purpose input/output (GPIO) port timing JTAG test-port timing mechanical data
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
PowerPAD package (top view)
208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP) VIEW
package (bottom view)
256-PIN BALL GRID ARRAY (BGA) PACKAGE BOTTOM VIEW
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
description
TMS320C67xt DSPs (including TMS320C6713 device) compose floating-point generation TMS320C6000t platform. TMS320C6713 (C6713) device based high-performance, advanced VelociTIt very-long-instruction-word (VLIW) architecture developed Texas Instruments (TI), making this excellent choice multichannel multifunction applications. Operating MHz, C6713 delivers 1350 million floating-point operations second (MFLOPS), 1800 million instructions second (MIPS), with dual fixed-/floating-point multipliers million multiply-accumulate operations second (MMACS). C6713 uses two-level cache-based architecture powerful diverse peripherals. Level program cache (L1P) 4K-Byte direct-mapped cache Level data cache (L1D) 4K-Byte 2-way set-associative cache. Level memory/cache (L2) consists 256K-Byte memory space that shared between program data space. Bytes 256K Bytes memory configured mapped memory, cache, combinations two. remaining 192K Bytes serves mapped SRAM. C6713 rich peripheral that includes Multichannel Audio Serial Ports (McASPs), Multichannel Buffered Serial Ports (McBSPs), Inter-Integrated Circuit (I2C) buses, dedicated General-Purpose Input/Output (GPIO) module, general-purpose timers, host-port interface (HPI), glueless external memory interface (EMIF) capable interfacing SDRAM, SBSRAM, asynchronous peripherals. McASP interface modules each support transmit receive clock zone. Each McASP eight serial data pins which individually allocated zones. serial port supports time-division multiplexing each from time slots. C6713 sufficient bandwidth support serial data pins transmitting stereo signal. Serial data each zone transmitted received multiple serial data pins simultaneously formatted multitude variations Philips Inter-IC Sound (I2S) format. addition, McASP transmitter programmed output multiple S/PDIF, IEC60958, AES-3 encoded data channels simultaneously, with single containing full implementation user data channel status fields. McASP also provides extensive error-checking recovery features, such clock detection circuit each high-frequency master clock which verifies that master clock within programmed frequency range. ports TMS320C6713 allow easily control peripheral devices, boot from serial EEPROM, communicate with host processor. TMS320C67x generation supported eXpressDSPt industry benchmark development tools, including highly optimizing C/C++ Compiler, Code Composer Studiot Integrated Development Environment (IDE), JTAG-based emulation real-time debugging, DSP/BIOSt kernel.
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TMS320C6000, eXpressDSP, Code Composer Studio, DSP/BIOS trademarks Texas Instruments.
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device characteristics
Table provides overview C6713 DSP. table shows significant features C6713 device, including capacity on-chip RAM, peripherals, execution time, package type with count. more details C67x device part numbers part numbering, Table Figure Table Characteristics C6713 Processor
HARDWARE FEATURES EMIF EDMA Channels) bit) McASPs Peripherals I2Cs McBSPs 32-Bit Timers GPIO Modules Size (Bytes) On-Chip Memory bit) 264K 4K-Byte (4KB) Program (L1P) Cache Data (L1D) Cache 64KB Unified Cache/Mapped 192KB Mapped 0x0203 225, (C6713GFN-225), (C6713GFN-150) 256-Pin (GFN) 0.13 208-Pin PowerPAD PQFP (PYP) (C6713PYP-150) C6713 (FLOATING-POINT DSP) bit)
Organization
ID+CPU Frequency Cycle Time Voltage
Control Status Register (CSR.[31:16]) Core Prescaler Multiplier Postscaler
Clock Generator Options
Packages Process Technology Product Status Product Preview (PP) Advance Information (AI) Production Data (PD)
C67x trademark Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
functional block (DSP core) diagram
C6713 Digital Signal Processor
EMIF Cache Direct Mapped Bytes Total
McASP1
Cache/ Memory Banks Bytes Total 4-Way)
C67x Instruction Fetch Instruction Dispatch Control Registers Control Logic Test In-Circuit Emulation Interrupt Control
McASP0
McBSP1
Instruction Decode Data Path Data Path Register File
Multiplexing
McBSP0
Register File
I2C1
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Enhanced Controller channel) Memory 192K Bytes
I2C0
Timer
Cache 2-Way Associative Bytes
Timer
Clock Generator, Oscillator, through Multipliers
Power-Down Logic
GPIO
addition fixed-point instructions, these functional units execute floating-point instructions. EMIF interfaces -SDRAM -SBSRAM -SRAM, -ROM/Flash, -I/O devices McBSPs interface -SPI Control Port -High-Speed Codecs -AC97 Codecs -Serial EEPROM McASPs interface -I2S Multichannel ADC, DAC, Codec, -DIT: Multiple Outputs
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
(DSP core) description
TMS320C6713 floating-point digital signal processor based C67x CPU. fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) supply eight 32-bit instructions eight functional units during every clock cycle. VelociTI VLIW architecture features controls which eight units have supplied with instructions they ready execute. first every 32-bit instruction determines next instruction belongs same execute packet previous instruction, whether should executed following clock part next execute packet. Fetch packets always bits wide; however, execute packets vary size. variable-length execute packets memory-saving feature, distinguishing C67x from other VLIW architectures. features sets functional units. Each contains four units register file. contains functional units .L1, .S1, .M1, .D1; other contains units .D2, .M2, .S2, .L2. register files each contain 32-bit registers total general-purpose registers. sets functional units, along with register files, compose sides (see functional block diagram Figure four functional units each side freely share registers belonging that side. Additionally, each side features single data connected registers other side, which sets functional units access data from register files opposite side. While register access functional units same side register file service units single clock cycle, register access using register file across supports read write cycle. C67x executes C62x instructions. addition C62x fixed-point instructions, eight functional units (.L1, .S1, .M1, .M2, .S2, .L2) also execute floating-point instructions. remaining functional units (.D1 .D2) also execute LDDW instruction which loads bits side total bits cycle. Another feature C67x load/store architecture, where instructions operate registers opposed data memory). sets data-addressing units (.D1 .D2) responsible data transfers between register files memory. data address driven units allows data addresses generated from register file used load store data from other register file. C67x supports variety indirect addressing modes using either linear- circular-addressing modes with 15-bit offsets. instructions conditional, most access registers. Some registers, however, singled support specific addressing hold condition conditional instructions condition automatically "true"). functional units dedicated multiplies. functional units perform general arithmetic, logical, branch functions with results available every clock cycle. processing flow begins when 256-bit-wide instruction fetch packet fetched from program memory. 32-bit instructions destined individual functional units "linked" together bits least significant (LSB) position instructions. instructions that "chained" together simultaneous execution eight total) compose execute packet. instruction breaks chain, effectively placing instructions that follow next execute packet. execute packet crosses fetch-packet boundary (256 bits wide), assembler places next fetch packet, while remainder current fetch packet padded with instructions. number execute packets within fetch packet vary from eight. Execute packets dispatched their respective functional units rate clock cycle next 256-bit fetch packet fetched until execute packets from current fetch packet have been dispatched. After decoding, instructions simultaneously drive active functional units maximum execution rate eight instructions every clock cycle. While most results stored 32-bit registers, they subsequently moved memory bytes half-words well. load store instructions byte-, half-word, word-addressable.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
(DSP core) description (continued)
src1
src2
long long
Data Path
long long src1 src2
src1 src2
src1 src2
src2 src1
src2
src1 src2
Data Path
src1 long long
addition fixed-point instructions, these functional units execute floating-point instructions.
Figure TMS320C67x (DSP Core) Data Paths
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long long src2
src1
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Register File (A0-A15) Register File (B0-B15) Control Register File
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
memory summary
Table shows memory address ranges C6713 device. Table TMS320C6713 Memory Summary
MEMORY BLOCK DESCRIPTION Internal (L2) Internal RAM/Cache Reserved External Memory Interface (EMIF) Registers Registers Reserved Registers McBSP Registers McBSP Registers Timer Registers Timer Registers Interrupt Selector Registers Device Configuration Registers Reserved EDMA EDMA Registers Reserved GPIO Registers Reserved I2C0 Registers I2C1 Registers Reserved McASP0 Registers McASP1 Registers Reserved Registers Reserved QDMA Registers Reserved Reserved McBSP0 Data McBSP1 Data Reserved McASP0 Data McASP1 Data Reserved EMIF EMIF EMIF EMIF Reserved BLOCK SIZE (BYTES) 192K 256K 256K 128K 128K 256K 256K 256K 256K 256K 256K 256K 768K 240K 160K 520K 720M 256M 256M 256M 256M ADDRESS RANGE 0000 0000 0002 FFFF 0003 0000 0003 FFFF 0004 0000 017F FFFF 0180 0000 0183 FFFF 0184 0000 0185 FFFF 0186 0000 0187 FFFF 0188 0000 018B FFFF 018C 0000 018F FFFF 0190 0000 0193 FFFF 0194 0000 0197 FFFF 0198 0000 019B FFFF 019C 0000 019C 01FF 019C 0200 019C 0203 01A0 0000 01A3 FFFF 01A4 0000 01AF FFFF 01B0 0000 01B0 3FFF 01B0 4000 01B3 FFFF 01B4 0000 01B4 3FFF 01B4 4000 01B4 7FFF 01B4 8000 01B4 BFFF 01B4 C000 01B4 FFFF 01B5 0000 01B5 3FFF 01B5 4000 01B7 BFFF 01B7 C000 01B7 DFFF 01B7 E000 01FF FFFF 0200 0000 0200 0033 0200 0034 02FF FFFF 0300 0000 2FFF FFFF 3000 0000 33FF FFFF 3400 0000 37FF FFFF 3800 0000 3BFF FFFF 3C00 0000 3C0F FFFF 3C10 0000 3C1F FFFF 3C20 0000 7FFF FFFF 8000 0000 8FFF FFFF 9000 0000 9FFF FFFF A000 0000 AFFF FFFF B000 0000 BFFF FFFF C000 0000 FFFF FFFF 019C 0204 019F FFFF
number EMIF address pins (EA[21:2]) limits maximum addressable memory (SDRAM) 128MB space.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
memory structure expanded Figure shows detail memory structure.
Mode 0x0000 0000 Memory Block Base Address
208K SRAM
192K SRAM
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256K SRAM (All)
240KSRAM
224K SRAM
Bytes
0x0003 0000
4-Way Cache
3-Way Cache
2-Way Cache
1-Way Cache
Figure Memory Configuration
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Bytes Bytes Bytes Bytes
0x0003 4000 0x0003 8000 0x0003 C000 0x0003 FFFF
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions
Table through Table identify peripheral registers C6713 device their register names, acronyms, address address range. more detailed information register contents, names, their descriptions, TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table EMIF Registers
ADDRESS RANGE 0180 0000 0180 0004 0180 0008 0180 000C 0180 0010 0180 0014 0180 0018 0180 001C 0180 0020 0180 0024 0183 FFFF ACRONYM GBLCTL CECTL1 CECTL0 CECTL2 CECTL3 SDCTL SDTIM SDEXT EMIF global control EMIF space control EMIF space control Reserved EMIF space control EMIF space control EMIF SDRAM control EMIF SDRAM refresh control EMIF SDRAM extension Reserved REGISTER NAME
Table Cache Registers
ADDRESS RANGE 0184 0000 0184 4000 0184 4004 0184 4010 0184 4014 0184 4020 0184 4024 0184 4030 0184 4034 0184 5000 0184 5004 0184 8200 0184 8204 0184 8208 0184 820C 0184 8240 0184 8244 0184 8248 0184 824C 0184 8280 0184 8284 0184 8288 0184 828C 0184 82C0 0184 82C4 0184 82C8 0184 82CC 0184 82D0 0185 FFFF ACRONYM CCFG L2FBAR L2FWC L2CBAR L2CWC L1PFBAR L1PFWC L1DFBAR L1DFWC L2FLUSH L2CLEAN MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7 MAR8 MAR9 MAR10 MAR11 MAR12 MAR13 MAR14 MAR15 Cache configuration register flush base address register flush word count register clean base address register clean word count register flush base address register flush word count register flush base address register flush word count register flush register clean register Controls range 8000 0000 80FF FFFF Controls range 8100 0000 81FF FFFF Controls range 8200 0000 82FF FFFF Controls range 8300 0000 83FF FFFF Controls range 9000 0000 90FF FFFF Controls range 9100 0000 91FF FFFF Controls range 9200 0000 92FF FFFF Controls range 9300 0000 93FF FFFF Controls range A000 0000 A0FF FFFF Controls range A100 0000 A1FF FFFF Controls range A200 0000 A2FF FFFF Controls range A300 0000 A3FF FFFF Controls range B000 0000 B0FF FFFF Controls range B100 0000 B1FF FFFF Controls range B200 0000 B2FF FFFF Controls range B300 0000 B3FF FFFF Reserved REGISTER NAME
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions (continued)
Table Interrupt Selector Registers
ADDRESS RANGE 019C 0000 019C 0004 019C 0008 019C 000C 019F FFFF ACRONYM MUXH MUXL EXTPOL REGISTER NAME Interrupt multiplexer high Interrupt multiplexer External interrupt polarity Reserved COMMENTS Selects which interrupts drive interrupts 10-15 (INT10-INT15) Selects which interrupts drive interrupts (INT04-INT09) Sets polarity external interrupts (EXT_INT4-EXT_INT7)
Table EDMA Parameter
ADDRESS RANGE 01A0 0000 01A0 0017 01A0 0018 01A0 002F 01A0 0030 01A0 0047 ACRONYM Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Parameters Event words) Reload/link parameters Event words) Reload/link parameters Event words) Reload/link parameters Event words) REGISTER NAME
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01A0 0048 01A0 005F 01A0 0060 01A0 0077 01A0 0078 01A0 008F 01A0 0090 01A0 00A7 01A0 00A8 01A0 00BF 01A0 00C0 01A0 00D7 01A0 00D8 01A0 00EF 01A0 00F0 01A0 00107 01A0 0108 01A0 011F 01A0 0120 01A0 0137 01A0 0138 01A0 014F 01A0 0150 01A0 0167 01A0 0168 01A0 017F 01A0 0180 01A0 0197 01A0 0198 01A0 01AF 01A0 07E0 01A0 07F7 01A0 07F8 01A0 07FF
Scratch area words) C6211/C6211B device sixty-nine parameter sets [six words each] that used reload/link EDMA transfers.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions (continued)
Table EDMA Registers
ADDRESS RANGE 01A0 0800 01A0 FEFC 01A0 FF00 01A0 FF04 01A0 FF08 01A0 FF0C 01A0 FF1F 01A0 FFDC 01A0 FFE0 01A0 FFE4 01A0 FFE8 01A0 FFEC 01A0 FFF0 01A0 FFF4 01A0 FFF8 01A0 FFFC 01A1 0000 01A3 FFFF ACRONYM ESEL0 ESEL1 ESEL3 PQSR CIPR CIER CCER Reserved EDMA event selector EDMA event selector Reserved EDMA event selector Reserved Priority queue status register Channel interrupt pending register Channel interrupt enable register Channel chain enable register Event register Event enable register Event clear register Event register Reserved REGISTER NAME
Table Quick (QDMA) Pseudo Registers
ADDRESS RANGE 0200 0000 0200 0004 0200 0008 0200 000C 0200 0010 0200 0014 0200 001C 0200 0020 0200 0024 0200 0028 0200 002C 0200 0030 ACRONYM QOPT QSRC QCNT QDST QIDX QSOPT QSSRC QSCNT QSDST QSIDX QDMA options parameter register QDMA source address register QDMA frame count register QDMA destination address register QDMA index register Reserved QDMA pseudo options register QDMA pseudo source address register QDMA pseudo frame count register QDMA pseudo destination address register REGISTER NAME
QDMA pseudo index register QDMA Pseudo registers write-accessible only
Table Wrapper Registers
ADDRESS RANGE 01B7 C000 01B7 C0FF 01B7 C100 01B7 C104 01B7 C10F 01B7 C110 01B7 C114 01B7 C118 01B7 C11C 01B7 C120 01B7 C124 01B7 C128 01B7 DFFF ACRONYM PLLCSR PLLM PLLDIV0 PLLDIV1 PLLDIV2 PLLDIV3 OSCDIV1 Reserved control/status register Reserved multiplier control register wrapper divider register wrapper divider register wrapper divider register wrapper divider register Oscillator divider register Reserved REGISTER NAME
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions (continued)
Table McASP0 McASP1 Registers
ADDRESS RANGE McASP0 01B4 C000 01B4 C004 01B4 C008 01B4 C00C 01B4 C010 01B4 C014 01B4 C018 01B4 C01C 01B4 C020 01B4 C024 01B4 C040 01B4 C044 01B4 C048 01B4 C04C 01B4 C050 01B4 C054 01B4 C05C 01B4 C060 01B4 C064 01B4 C068 01B4 C06C 01B4 C070 01B4 C074 01B4 C078 01B4 C07C 01B4 C080 01B4 C084 01B4 C088 01B4 C08C 01B4 C09C 01B4 C0A0 01B4 C0A4 01B4 C0A8 01B4 C0AC 01B4 C0B0 01B4 C0B4 01B4 C0B8 01B4 C0BC 01B4 C0C0 01B4 C0C4 McASP1 01B5 0000 01B5 0004 01B5 0008 01B5 000C 01B5 0010 01B5 0014 01B5 0018 01B5 001C 01B5 0020 01B5 0024 01B5 0040 01B5 0044 01B5 0048 01B5 004C 01B5 0050 01B5 0054 01B5 005C 01B5 0060 01B5 0064 01B5 0068 01B5 006C 01B5 0070 01B5 0074 01B5 0078 01B5 007C 01B5 0080 01B5 0084 01B5 0088 01B5 008C 01B5 009C 01B5 00A0 01B5 00A4 01B5 00A8 01B5 00AC 01B5 00B0 01B5 00B4 01B5 00B8 01B5 00BC 01B5 00C0 01B5 00C4 ACRONYM PWRDEMU PFUNC PDIR PDOUT PDIN/PDSET PDCLR GBLCTL AMUTE DLBCTL DITCTL RGBLCTL RMASK RFMT AFSRCTL ACLKRCTL AHCLKRCTL RTDM RINTCTL RSTAT RSLOT RCLKCHK XGBLCT XMASK XFMT AFSXCTL ACLKXCTL AHCLKXCTL XTDM XINTCTL XSTAT XSLOT Reserved Power down emulation management register Reserved Reserved function register direction register data register data data register Read returns: PDIN Writes affect: PDSET data clear register Reserved Global control register Mute control register Digital Loop-back control register mode control register Reserved Alias GBLCTL containing only Receiver Reset bits, allows transmit reset independently from receive. Receiver format unit mask register Receive stream format register Receive frame sync control register Receive clock control register High-frequency receive clock control register Receive slot 0-31 register Receiver interrupt control register Status register Receiver Current receive slot register Receiver clock check control register Reserved Alias GBLCTL containing only Transmitter Reset bits, allows transmit reset independently from receive. Transmit format unit mask register Transmit stream format register Transmit frame sync control register Transmit clock control register High-frequency Transmit clock control register Transmit slot 0-31 register Transmit interrupt control register Status register Transmitter Current transmit slot REGISTER NAME
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peripheral register descriptions (continued)
Table McASP0 McASP1 Registers (Continued)
ADDRESS RANGE McASP0 01B4 C0C8 01B4 C0CC 01B4 C0FC 01B4 C100 01B4 C104 01B4 C108 01B4 C10C 01B4 C110 01B4 C114 01B4 C118 01B4 C11C 01B4 C120 01B4 C124 01B4 C128 01B4 C12C 01B4 C130 01B4 C134 01B4 C138 01B4 C13C 01B4 C140 01B4 C144 01B4 C148 01B4 C14C 01B4 C150 01B4 C154 01B4 C158 01B4 C15C 01B4 C160 01B4 C17C 01B4 C180 01B4 C184 01B4 C188 01B4 C18C 01B4 C190 01B4 C194 01B4 C198 01B4 C19C 01B4 C1A0 01B4 C1FC 01B4 C200 01B4 C204 01B4 C208 01B4 C20C 01B4 C210 McASP1 01B5 00C8 01B5 00CC 01B5 00FC 01B5 0100 01B5 0104 01B5 0108 01B5 010C 01B5 0110 01B5 0114 01B5 0118 01B5 011C 01B5 0120 01B5 0124 01B5 0128 01B5 012C 01B5 0130 01B5 0134 01B5 0138 01B5 013C 01B5 0140 01B5 0144 01B5 0148 01B5 014C 01B5 0150 01B5 0154 01B5 0158 01B5 015C 01B5 0160 01B5 017C 01B5 0180 01B5 0184 01B5 0188 01B5 018C 01B5 0190 01B5 0194 01B5 0198 01B5 019C 01B5 C1A0 01B5 01FC 01B5 0200 01B5 0204 01B5 0208 01B5 020C 01B50C210 ACRONYM XCLKCHK DITCSRA0 DITCSRA1 DITCSRA2 DITCSRA3 DITCSRA4 DITCSRA5 DITCSRB0 DITCSRB1 DITCSRB2 DITCSRB3 DITCSRB4 DITCSRB5 DITUDRA0 DITUDRA1 DITUDRA2 DITUDRA3 DITUDRA4 DITUDRA5 DITUDRB0 DITUDRB1 DITUDRB2 DITUDRB3 DITUDRB4 DITUDRB5 SRCTL0 SRCTL1 SRCTL2 SRCTL3 SRCTL4 SRCTL5 SRCTL6 SRCTL7 XBUF0 XBUF1 XBUF2 XBUF3 XBUF4 REGISTER NAME Transmit clock check control register Reserved Left (even slot) channel status register file Left (even slot) channel status register file Left (even slot) channel status register file Left (even slot) channel status register file Left (even slot) channel status register file Left (even slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Right (odd slot) channel status register file Left (even slot) user data register file Left (even slot) user data register file Left (even slot) user data register file Left (even slot) user data register file Left (even slot) user data register file Left (even slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Right (odd slot) user data register file Reserved Serializer control register Serializer control register Serializer control register Serializer control register Serializer control register Serializer control register Serializer control register Serializer control register Reserved Transmit Buffer Serializer Transmit Buffer Serializer Transmit Buffer Serializer Transmit Buffer Serializer Transmit Buffer Serializer Right (odd slot) channel status register file
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
peripheral register descriptions (continued)
Table McASP0 McASP1 Registers (Continued)
ADDRESS RANGE McASP0 01B4 C214 01B4 C218 01B4 C21C 01B4 C220 01B4 C27C 01B4 C280 01B4 C284 01B4 C288 01B4 C28C 01B4 C290 01B4 C294 01B4 C298 01B4 C29C 01B4 C2A0 01B4 FFFF McASP1 01B5 0214 01B5 0218 01B5 021C 01B5 C220 01B5 027C 01B5 0280 01B5 0284 01B5 0288 01B5 028C 01B5 0290 01B5 0294 01B5 0298 01B5 029C 01B5 02A0 01B5 3FFF ACRONYM XBUF5 XBUF6 XBUF7 RBUF0 RBUF1 RBUF2 RBUF3 RBUF4 RBUF5 RBUF6 RBUF7 REGISTER NAME Transmit Buffer Serializer Transmit Buffer Serializer Transmit Buffer Serializer Reserved Receive Buffer Serializer Receive Buffer Serializer Receive Buffer Serializer Receive Buffer Serializer Receive Buffer Serializer Receive Buffer Serializer Receive Buffer Serializer Receive Buffer Serializer Reserved
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Table I2C0 Registers
ADDRESS RANGE 01B4 0000 01B4 0004 01B4 0008 01B4 000C 01B4 0010 01B4 0014 01B4 0018 01B4 001C 01B4 0020 01B4 0024 01B4 0028 01B4 002C 01B4 0030 01B4 0034 01B4 3FFF ACRONYM I2COAR0 I2CIER0 I2CSTR0 I2CCLKL0 I2CCLKH0 I2CCNT0 I2CDRR0 I2CSAR0 I2CDXR0 I2CMDR0 I2CISRC0 I2CPSC0 REGISTER NAME I2C0 address register I2C0 interrupt enable register I2C0 interrupt status register I2C0 clock low-time divider register I2C0 clock high-time divider register I2C0 data count register I2C0 data receive register I2C0 slave address register I2C0 data transmit register I2C0 mode register I2C0 interrupt source register Reserved I2C0 prescaler register Reserved
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peripheral register descriptions (continued)
Table I2C1 Registers
ADDRESS RANGE 01B4 4000 01B4 4004 01B4 4008 01B4 400C 01B4 4010 01B4 4014 01B4 4018 01B4 401C 01B4 4020 01B4 4024 01B4 4028 01B4 402C 01B4 4030 01B4 4034 01B4 7FFF ACRONYM I2COAR1 I2CIER1 I2CSTR1 I2CCLKL1 I2CCLKH1 I2CCNT1 I2CDRR1 I2CSAR1 I2CDXR1 I2CMDR1 I2CISRC1 I2CPSC1 REGISTER NAME I2C1 address register I2C1 interrupt enable register I2C1 interrupt status register I2C1 clock low-time divider register I2C1 clock high-time divider register I2C1 data count register I2C1 data receive register I2C1 slave address register I2C1 data transmit register I2C1 mode register I2C1 interrupt source register Reserved I2C1 prescaler register Reserved
Table Registers
ADDRESS RANGE 0188 0000 0188 0001 018B FFFF ACRONYM HPID HPIA HPIC REGISTER NAME data register address register control register Reserved COMMENTS Host read/write access only Host read/write access only Both Host/CPU read/write access
Table McBSP Registers
ADDRESS RANGE 018C 0000 0x3000 0000 0x33FF FFFF 018C 0004 0x3000 0000 0x33FF FFFF 018C 0008 018C 000C 018C 0010 018C 0014 018C 0018 018C 001C 018C 0020 018C 0024 018C 0028 018F FFFF ACRONYM DRR0 DRR0 DXR0 DXR0 SPCR0 RCR0 XCR0 SRGR0 MCR0 RCER0 XCER0 PCR0 REGISTER NAME McBSP0 data receive register Peripheral McBSP0 data receive register EDMA McBSP0 data transmit register Peripheral McBSP0 data transmit register EDMA McBSP0 serial port control register McBSP0 receive control register McBSP0 transmit control register McBSP0 sample rate generator register McBSP0 multichannel control register McBSP0 receive channel enable register McBSP0 transmit channel enable register McBSP0 control register Reserved COMMENTS DMA/EDMA controller only read this register; they cannot write
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peripheral register descriptions (continued)
Table McBSP Registers
ADDRESS RANGE 0190 0000 0x3400 0000 0x37FF FFFF 0190 0004 0x3400 0000 0x37FF FFFF 0190 0008 0190 000C 0190 0010 0190 0014 0190 0018 0190 001C 0190 0020 ACRONYM DRR1 DRR1 DXR1 DXR1 SPCR1 RCR1 XCR1 SRGR1 MCR1 RCER1 XCER1 PCR1 REGISTER NAME Data receive register Peripheral McBSP1 data receive register EDMA McBSP1 data transmit register Peripheral McBSP1 data transmit register EDMA McBSP1 serial port control register McBSP1 receive control register McBSP1 transmit control register McBSP1 sample rate generator register McBSP1 multichannel control register McBSP1 receive channel enable register McBSP1 transmit channel enable register McBSP1 control register Reserved COMMENTS DMA/EDMA controller only read this register; they cannot write
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0190 0024 0190 0028 0193 FFFF
Table Timer Registers
ADDRESS RANGE 0194 0000 ACRONYM CTL0 REGISTER NAME Timer control register COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
0194 0004 0194 0008 0194 000C 0197 FFFF
PRD0 CNT0
Timer period register Timer counter register Reserved
Table Timer Registers
ADDRESS RANGE 0198 0000 ACRONYM CTL1 REGISTER NAME Timer control register COMMENTS Determines operating mode timer, monitors timer status, controls function TOUT pin. Contains number timer input clock cycles count. This number controls TSTAT signal frequency. Contains current value incrementing counter.
0198 0004 0198 0008 0198 000C 019B FFFF
PRD1 CNT1
Timer period register Timer counter register Reserved
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peripheral register descriptions (continued)
Table GPIO Registers
ADDRESS RANGE 01B0 0000 01B0 0004 01B0 0008 01B0 000C 01B0 0010 01B0 0014 01B0 0018 01B0 001C 01B0 0020 01B0 0024 01B0 0028 01B0 3FFF ACRONYM GPEN GPDIR GPVAL GPDH GPHM GPDL GPLM GPGC GPPOL REGISTER NAME GPIO enable register GPIO direction register GPIO value register Reserved GPIO delta high register GPIO high mask register GPIO delta register GPIO mask register GPIO global control register GPIO interrupt polarity register Reserved
PWRD bits register description
Table identifies PWRD field (bits 15-10) register. These bits control device power-down modes. more detailed information PWRD field register, TMS320C6000 Peripherals Reference Guide (literature number SPRU190). Table PWRD field bits Register
ADDRESS RANGE ACRONYM REGISTER NAME Control status register COMMENTS PWRD field (bits 15-10 CSR) controls device power-down modes. Accessible writing value register.
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interrupts interrupt selector
C67x core supports prioritized interrupts, which listed Table highest priority interrupt INT_00 (dedicated RESET) while lowest priority INT_15. first four interrupts non-maskable fixed. remaining interrupts (4-15) maskable default interrupt source listed Table However, their interrupt source reprogrammed sources listed Table (Interrupt Selector). Table lists selector value corresponding each alternate interrupt sources. selector choice interrupts 4-15 made programming corresponding fields (listed Table MUXH (address 0x019C0000) MUXL (address 0x019C0004) registers. Table Interrupts
INTERRUPT NUMBER INT_00 INT_01 INT_02 INT_03 INT_04 INT_05 INT_06 INT_07 INT_08 INT_09 INT_10 INT_11 INT_12 INT_13 INT_14 INT_15 INTERRUPT SELECTOR CONTROL REGISTER MUXL[4:0] MUXL[9:5] MUXL[14:10] MUXL[20:16] MUXL[25:21] MUXL[30:26] MUXH[4:0] MUXH[9:5] MUXH[14:10] MUXH[20:16] MUXH[25:21] MUXH[30:26] DEFAULT SELECTOR VALUE (BINARY) 00100 00101 00110 00111 01000 01001 00011 01010 01011 00000 00001 00010 DEFAULT INTERRUPT EVENT RESET Reserved Reserved EXTINT4 EXTINT5 EXTINT6 EXTINT7 EDMAINT EMUDTDMA SDINT EMURTDXRX EMURTDXTX DSPINT TINT0 TINT1
Table Interrupt Selector
INTERRUPT SELECTOR VALUE (BINARY) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 INTERRUPT EVENT DSPINT TINT0 TINT1 SDINT EXTINT4 EXTINT5 EXTINT6 EXTINT7 EDMAINT EMUDTDMA EMURTDXRX EMURTDXTX XINT0 RINT0 XINT1 RINT1 GPINT0 Reserved Reserved Reserved Reserved Reserved I2CINT0 I2CINT1 Reserved Reserved Reserved Reserved AXINT0 ARINT0 AXINT1 ARINT1 MODULE
Timer Timer EMIF GPIO GPIO GPIO GPIO EDMA Emulation Emulation Emulation McBSP0 McBSP0 McBSP1 McBSP1 GPIO I2C0 I2C1 McASP0 McASP0 McASP1 McASP1
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EDMA module EDMA selector
C67x EDMA supports EDMA channels. Four sixteen channels (channels 8-11) reserved EDMA chaining, leaving EDMA channels available service peripheral devices. EDMA selector registers that control EDMA channels servicing peripheral devices located addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), 0x01A0FF0C (ESEL3). These EDMA selector registers control mapping EDMA events EDMA channels. Each EDMA event assigned EDMA selector code (see Table 23). loading each EVTSELx register field with EDMA selector code, users desired EDMA event specified EDMA channel. Table lists default EDMA selector value each EDMA channel. Table Table EDMA Event Selector registers their assoicated descriptions.
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EDMA module EDMA selector (continued)
Table EDMA Channels
EDMA CHANNEL EDMA SELECTOR CONTROL REGISTER ESEL0[5:0] ESEL0[13:8] ESEL0[21:16] ESEL0[29:24] ESEL1[5:0] ESEL1[13:8] ESEL1[21:16] ESEL1[29:24] ESEL3[5:0] ESEL3[13:8] ESEL3[21:16] ESEL3[29:24] DEFAULT SELECTOR VALUE (BINARY) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 DEFAULT EDMA EVENT DSPINT TINT0 TINT1 SDINT EXTINT4 EXTINT5 EXTINT6 EXTINT7 TCC8 (Chaining) TCC9 (Chaining) TCC10 (Chaining) TCC11 (Chaining) XEVT0 REVT0 XEVT1 REVT1
Table EDMA Selector
EDMA SELECTOR CODE (BINARY) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000-011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000-111111 EDMA EVENT DSPINT TINT0 TINT1 SDINT EXTINT4 EXTINT5 EXTINT6 EXTINT7 GPINT0 GPINT1 GPINT2 GPINT3 XEVT0 REVT0 XEVT1 REVT1 Reserved AXEVTE0 AXEVTO0 AXEVT0 AREVTE0 AREVTO0 AREVT0 AXEVTE1 AXEVTO1 AXEVT1 AREVTE1 AREVTO1 AREVT1 I2CREVT0 I2CXEVT0 I2CREVT1 I2CXEVT1 GPINT8 GPINT9 GPINT10 GPINT11 GPINT12 GPINT13 GPINT14 GPINT15 Reserved McASP0 McASP0 McASP0 McASP0 McASP0 McASP0 McASP1 McASP1 McASP1 McASP1 McASP1 McASP1 I2C0 I2C0 I2C1 I2C1 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO MODULE
TIMER0 TIMER1 EMIF GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO McBSP0 McBSP0 McBSP1 McBSP1
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EDMA module EDMA selector (continued)
Table EDMA Event Selector Registers (ESEL0, ESEL1, ESEL3) ESEL0 Register (0x01A0 FF00)
Reserved
EVTSEL3 R/W-00 0011b
Reserved
EVTSEL2 R/W-00 0010b
EVTSEL0
Reserved
EVTSEL1 R/W-00 0001b
Reserved
R/W-00 0000b
Legend: Read only, Read/Write; value after reset
ESEL1 Register (0x01A0 FF04)
R/W-00 0111b
Reserved
R/W-00 0110b
EVTSEL4
Reserved
EVTSEL5 R/W-00 0101b
R/W-00 0100b
Legend: Read only, Read/Write; value after reset
ESEL3 Register (0x01A0 FF0C)
Reserved
EVTSEL15 R/W-00 1011b
Reserved
EVTSEL14 R/W-00 1010b
Reserved
EVTSEL13 R/W-00 1001b
Reserved
EVTSEL12 R/W-00 1000b
Legend: Read only, Read/Write; value after reset
Table EDMA Event Selection Registers (ESEL0, ESEL1, ESEL3) Description
31:30 23:22 15:14 NAME DESCRIPTION
Reserved
Reserved. Read-only, writes have effect.
EDMA event selection bits channel Allows mapping EDMA events EDMA channels. 29:24 21:16 13:8 EVTSEL0 through EVTSEL15 bits correspond channels respectively. These EVTSELx fileds user-selectable. configuring EVTSELx fields EDMA selector value desired EDMA sync event number (see Table 23), users EDMA event EDMA channel. example, EVTSEL15 programmed 0001b (the EDMA selector code TINT0), then channel triggered Timer0 TINT0 events.
EVTSELx
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Reserved
EVTSEL7
Reserved
EVTSEL6
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
signal groups description
CLKIN CLKOUT2/GP[2] CLKOUT3 CLKMODE0 PLLV PLLG OSCIN OSCOUT Clock/PLL Oscillator
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TRST EMU0 EMU1 EMU2 EMU3 EMU4 EMU5
Reset Interrupts
RESET GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1
IEEE Standard 1149.1 (JTAG) Emulation
Control/Status
HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7] HD0/AXR1[4]
(Host-Port Interface) HAS/ACLKX1 HR/W/AXR1[0] HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HINT/GP[1]
Control
Data
Register Select
HCNTL0/AXR1[3] HCNTL1/AXR1[1]
Half-Word Select
HHWIL/AFSR1
These external pins applicable package only. NOTE multiplexed pins, bolded text denotes active function that particular peripheral module.
Figure (DSP Core) Peripheral Signals
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
signal groups description (continued)
HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8]
GPIO
GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0]
General-Purpose Input/Output (GPIO) Port
TOUT1/AXR0[4] TINP1/AHCLKX0
Timer
Timer
TOUT0/AXR0[2] TINP0/AXR0[3]
Timers
CLKS1/SCL1 DR1/SDA1
I2C1 I2Cs
I2C0
SCL0 SDA0
NOTE multiplexed pins, bolded text denotes active function that particular peripheral module.
Figure Peripheral Signals
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
signal groups description (continued)
ED[31:16] ED[15:0]
Data Memory Control
ECLKIN ECLKOUT ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARDY
EA[21:2]
Memory Space Select Arbitration HOLD HOLDA BUSREQ
Address
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Byte Enables EMIF (External Memory Interface)
McBSP1
McBSP0
CLKX1/AMUTE0 FSX1 DX1/AXR0[5]
Transmit
Transmit
CLKX0/ACLKX0 FSX0/AFSX0 DX0/AXR0[1]
CLKR1/AXR0[6] FSR1/AXR0[7] DR1/SDA1
Receive
Receive
CLKR0/ACLKR0 FSR0/AFSR0 DR0/AXR0[0]
CLKS1/SCL1
Clock
Clock
CLKS0/AHCLKR0
McBSPs (Multichannel Buffered Serial Ports)
These external pins applicable package only. NOTE multiplexed pins, bolded text denotes active function that particular peripheral module.
Figure Peripheral Signals (Continued)
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signal groups description (continued)
(Transmit/Receive Data Pins) FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0]
8-Serial Ports Flexible Partitioning
(Receive Clock) CLKR0/ACLKR0 TINP1/AHCLKX0 (Receive Master Clock) Transmit Clock Check Circuit Receive Clock Generator Transmit Clock Generator
(Transmit Clock) CLKX0/ACLKX0 CLKS0/AHCLKR0 (Transmit Master Clock)
Receive Clock Check Circuit
FSR0/AFSR0 (Receive Frame Sync Left/Right Clock)
Receive Frame Sync
Transmit Frame Sync
FSX0/AFSX0 (Transmit Frame Sync Left/Right Clock) CLKX1/AMUTE0 GP[5](EXT_INT5)/AMUTEIN0
Error Detect (see Note
Auto Mute Logic
McASP0 (Multichannel Audio Serial Port
NOTES: McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, errors, external mute input. multiplexed pins, bolded text denotes active function that particular peripheral module. Bolded italicized text within parentheses denotes function pins audio system.
Figure Peripheral Signals (Continued)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
signal groups description (continued)
(Transmit/Receive Data Pins) HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0]
8-Serial Ports Flexible Partitioning
(Receive Clock) HRDY/ACLKR1 HD6/AHCLKR1 (Receive Master Clock) Receive Clock Generator Transmit Clock Generator
(Transmit Clock) HAS/ACLKX1 HD5/AHCLKX1 (Transmit Master Clock) Transmit Clock Check Circuit
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Receive Clock Check Circuit
HHWIL/AFSR1 (Receive Frame Sync Left/Right Clock)
Receive Frame Sync
Transmit Frame Sync
HD2/AFSX1 (Transmit Frame Sync Left/Right Clock) HD3/AMUTE1 GP[4](EXT_INT4)/AMUTEIN1
Error Detect (see Note
Auto Mute Logic
McASP1 (Multichannel Audio Serial Port
NOTES: McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, errors, external mute input. multiplexed pins, bolded text denotes active function that particular peripheral module. Bolded italicized text within parentheses denotes function pins audio system.
Figure Peripheral Signals (Continued)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS
C6713 device, bootmode certain device configurations/peripheral selections determined device reset, while other device configurations/peripheral selections software-configurable device configurations register (DEVCFG) [address location 0x019C0200] after device reset.
device configurations device reset
Table describes C6713 device configuration pins, which external pullup/pulldown resistors through data pins (HD[4:3], HD8, HD12) CLKMODE0 pin. more details these device configuration pins, Terminal Functions table Debugging Considerations section. Table Device Configurations Pins Device Reset (HD[4:3], HD8, HD12, CLKMODE0)
CONFIGURATION FUNCTIONAL DESCRIPTION Device Endian mode (LEND) System operates Endian mode System operates Little Endian mode (default) Bootmode Configuration Pins (BOOTMODE) width 32-bit, boot width 8-bit, Asynchronous external boot with default timings (default mode) width 16-bit, Asynchronous external boot width 32-bit, Asynchronous external boot Pulldown. proper device operation, this must externally pulled down with resistor. Clock generator input clock source select Oscillator pads (OSCIN, OSCOUT directly from crystal oscillator) CLKIN square wave [default]
HD[4:3] (BOOTMODE)
A15, C19,
HD12
CLKMODE0
This must pulled correct level even after reset. Other pins [15, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). proper device operation, oppose these pins with external IPUs/IPDs reset.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) peripheral selection device reset
Some C6713 peripherals share same pins mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:8, McASP0, I2C0).
versus McASP1, I2C0, peripherals
HPI_EN (HD14 pin) latched reset. This selects whether peripheral McASP1, I2C0 peripherals, GP[15:8, pins functionally enabled (see Table 27). Table HPI_EN (HD14 Pin) Peripheral Selection (HPI McASP1, I2C0, Select Pins)
PERIPHERAL SELECTION HPI_EN (HD14 Pin) PERIPHERALS SELECTED McASP1, I2C0, [15:8,3,1,0] DESCRIPTION
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HPI_EN disabled; McASP1 I2C0 peripherals [15:8, 1,0] pins enabled. multiplexed HPI/McASP1 HPI/GP pins function McASP1 pins, respectively. pins, appropriate bits GPEN GPDIR registers need configured. IPUs I2C0 pins disabled, allowing I2C0 use. When I2C0 peripheral used, avoid floating inputs, these I2C0 pins must externally pulled with resistor. HPI_EN enabled; McASP1 I2C0 peripherals [15:8, 1,0] pins disabled [default]. multiplexed HPI/McASP1 HPI/GP pins function pins. addition, since I2C0 peripheral disabled, IPUs I2C0 pins enabled avoid floating inputs.
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DEVICE CONFIGURATIONS (CONTINUED) peripheral selection/device configurations DEVCFG control register
device configuration register (DEVCFG) allows user control peripheral selection McBSP0, McBSP1, McASP0, I2C1 peripherals. DEVCFG register also offers user control EMIF input clock source timer output functions TOUT1/AXR0[4] TOUT0/AXR0[2] multiplexed pins. more detailed information DEVCFG register control bits, Table Table Table Device Configuration Register (DEVCFG) [Address location: 0x019C0200]
Reserved RW-0 Reserved RW-0 Legend: Read/Write; value after reset write non-zero values these locations. EKSRC R/W-0 TOUT1SEL R/W-0 TOUT0SEL R/W-0 McASP0EN R/W-0 I2C1EN R/W-0
Table Device Configuration (DEVCFG) Register Selection Descriptions
31:5 NAME Reserved DESCRIPTION Reserved. write non-zero values these locations. EMIF input clock source bit. Determines which clock signal used EMIF input clock. SYSCLK3 (from clock generator) EMIF input clock source (default) ECLKIN external EMIF input clock source Timer output (TOUT1) function select bit. Selects function TOUT1/AXR0[4] external independent rest peripheral selection bits DEVCFG register. functions Timer output (TOUT1) (default) functions McASP0 AXR0[4] pin. Timer output (TOUT0) function select bit. Selects function TOUT0/AXR0[2] external independent rest peripheral selection bits DEVCFG register. functions Timer output (TOUT0) (default) functions McASP0 AXR0[2] pin. Multichannel Audio Serial Port (McASP0) enable bit. Selects whether McASP0 McBSP0 peripheral enabled. McASP0 disabled (functional mode only), McBSP0 enabled (default). McASP0 enabled, McBSP0 disabled. Inter-integrated circuit (I2C1) enable bit. Selects whether I2C1 McBSP1 peripheral enabled. I2C1 disabled, McBSP1 enabled (default) internal IPU/IPDs CLKS1/SCL1 DR1/SDA1 pins enabled McBSP1's use. I2C1 enabled, McBSP1 disabled internal IPU/IPDs CLKS1/SCL1 DR1/SDA1 pins disabled I2C1's
EKSRC
TOUT1SEL
TOUT0SEL
MCASP0EN
I2C1EN
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) multiplexed pins
Multiplexed pins pins that shared more than peripheral internally multiplexed. Most these pins configured software device configuration register (DEVCFG), others (specifically, pins) configured external pullup/pulldown resistor HD14 (HPI_EN) reset. muxed pins that configured software intended programmed once during software initialization. muxed pins that configured external pullup/pulldown resistors mutually exclusive; only peripheral primary control function these pins after reset. Table summarizes peripheral pins affected HPI_EN (HD14 pin) DEVCFG register. Table identifies multiplexed pins C6713 device; shows default (primary) function default settings after reset; describes pins, registers, etc. necessary configure specific multiplexed functions.
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DEVICE CONFIGURATIONS (CONTINUED)
Table Peripheral Selection Matrix
SELECTION BITS PERIPHERAL PINS AVAILABILITY GP[0:1], GP[3], GP[8:15] None Plus: ctrl'd GP2EN GP[0:1], GP[3], GP[8:15]
HPI_EN (boot config pin)
None
None
None ACLKK0 ACLKR0 AFSX0 AFSR0 AHCLKR0 AXR0[0] AXR0[1] AMUTE0 AXR0[5] AXR0[6] AXR0[7] AMUTE0 AXR0[5] AXR0[6] AXR0[7] AXR0[2] AXR0[2] AXR0[4] AXR0[4]
McASP0EN (DEVCFG bit)
None
IIC1EN (DEVCFG bit)
None
None
TOUT0SEL (DEVCFG bit) TOUT1SEL (DEVCFG bit)
TOUT0 TOUT0 TOUT1 TOUT1
Gray blocks indicate that peripheral affected selection bit. McASP0 pins AXR0[3] AHCLKX0 shared with timer input pins TINP0 TINP1, respectively. Table more detailed information.
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AHCLKX1 AHCLKR1 ACLKX1 ACLKR1 AFSX1 AFSR1 AMUTE1 AXR1[0] AXR1[7]
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED)
Table C6713 Device Multiplexed/Shared Pins
MULTIPLEXED PINS NAME DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION When CLKOUT2 enabled CLK2EN EMIF global control register (GBLCTL) controls CLKOUT2 pin. CLK2EN CLKOUT2 held high CLK2EN CLKOUT2 enabled clock these GPIO pins, GPxEN bits GPIO Enable Register GPxDIR bits GPIO Direction Register must properly configured. GPxEN enabled GPxDIR input GPxDIR output AMUTEIN0/1 function, GP[5]/GP[4] pins must configured input, INSTAT associated McASP AMUTE register.
CLKOUT2/GP[2]
CLKOUT2
GP2EN (GPEN reigster bit) GP[2] function disabled, CLKOUT2 enabled
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GP[5](EXT_INT5)/AMUTEIN0 GP[4](EXT_INT4)/AMUTEIN1
GP[5](EXT_INT5) GP[4](EXT_INT4)
Function GP5EN (disabled) GP4EN (disabled) GPxDIR (input)
CLKS0/AHCLKR0 DR0/AXR0[0] DX0/AXR0[1] FSR0/AFSR0 FSX0/AFSX0 CLKR0/ACLKR0 CLKX0/ACLKX0 CLKS1/SCL1 DR1/SDA1 DX1/AXR0[5] FSR1/AXR0[7] CLKR1/AXR0[6] CLKX1/AMUTE0
McBSP1 function McBSP1 function I2C1EN (DEVCFG register bit) I2C1 disabled, McBSP0 pins enabled I2C1EN (DEVCFG register bit) I2C1 disabled disabled, McBSP1 pins enabled enable I2C1 peripheral, I2C1EN DEVCFG register must disabling McBSP1 peripheral pins. enable McASP0 peripheral pins I2C1EN DEVCFG register must McBSP0 function MCASP0EN (DEVCFG register bit) McASP0 pins disabled disabled, McBSP0 pins enabled enable McASP0 peripheral, McASP0EN ASP0EN DEVCFG register must (disabling McBSP0 peripheral pins). heral ins).
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED)
Table C6713 Device Multiplexed/Shared Pins
MULTIPLEXED PINS NAME HINT/GP[1] HD15/GP[15] HD14/GP[14] HD13/GP[13] HD12/GP[12] HD11/GP[11] HD10/GP[10] HD9/GP[9] HD8/GP[8] HD7/GP[3] HD4/GP[0] HD1/AXR1[7] HD0/AXR1[4] HCNTL1/AXR1[1] HCNTL0/AXR1[3] HR/W/AXR1[0] HDS1/AXR1[6] HDS2/AXR1[5] HCS/AXR1[2] HD6/AHCLKR1 HD5/AHCLKX1 HD3/AMUTE1 HD2/AFSX1 HHWIL/AFSR1 HRDY/ACLKR1 HAS/ACLKX1 AXR3 McASP0 PDIR register (input) default, this functions TINP0 AXR0[3] input. Setting AXR3 McASP0 PDIR register enables AXR0[3] output disables TINP0 function. default, this functions TINP1 AHCLKX0 input. Setting AHCLKX McASP0 PDIR register enables AHCLKX0 output disables TINP1 function. function HPI_EN (HD14 pin) (HPI enabled) McASP1, I2C0, eleven pins disabled disabled. enable McASP1 I2C0 peripherals eleven pins, herals ins, external pulldown resistor must provided HD14 setting HPI_EN reset. DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION
TINP0/AXR0[3]
Both TINP0 AXR0[3] input function
TINP1/AHCLKX0
Both TINP1 AHCLKX0 input function
AHCLKX McASP0 PDIR register (input)
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these GPIO pins, GPxEN bits GPIO Enable Register GPxDIR bits GPIO Direction Register must properly configured. GPxEN enabled GPxDIR input GPxDIR output
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED)
Table C6713 Device Multiplexed/Shared Pins
MULTIPLEXED PINS NAME DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION enable McASP0 AXR0[2] pin, following must properly configured: TOUT0SEL (DEVCFG register bit) TOUT0 enabled McASP0 AXR0[2] disabled TOUT0SEL (TOUT0 disabled, AXR0[2] enabled. AXR2 McASP0 PDIR register then AXR0[2] input pin. AXR2 McASP0 PDIR register then AXR0[2] output pin. enable McASP0 AXR0[4] pin, following must properly configured: TOUT1SEL (DEVCFG register bit) TOUT1 enabled McASP0 AXR0[4] disabled TOUT1SEL (TOUT1 disabled, AXR0[4] enabled. AXR4 McASP0 PDIR register then AXR0[4] input pin. AXR4 McASP0 PDIR register then AXR0[4] output pin.
TOUT0/AXR0[2]
Timer output function
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TOUT1/AXR0[4]
Timer output function
configuration examples
Figure through Figure illustrate examples peripheral selections that configurable this device.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET,
EMIF
GP[15:8, 3:1] GPIO EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
I2C0
SCL0, SDA0
SCL1, SDA1
I2C1
McASP1
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] AXR0[7:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
McBSP1
McASP0
TIMER0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000F McASP0EN I2C1EN TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (GPEN Register)
Figure Configuration Example McASP)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET,
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY
GP[15:8, 3:1] GPIO EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
PRODUCT PREVIEW
I2C0
SCL0, SDA0
I2C1
McASP1
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0]
AXR0[4:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1
McBSP1
McASP0
TIMER0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000E McASP0EN I2C1EN TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (GPEN Register)
Figure Configuration Example McBSP McASP)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET,
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY
GP[15:8, 3:1] GPIO EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
I2C0
SCL0, SDA0
SCL1, SDA1
I2C1
McASP1
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0]
McBSP1
McASP0 (DIT Mode)
AXR0[7:2] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0
TIMER0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000D McASP0EN I2C1EN TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (GPEN Register)
Figure Configuration Example McBSP McASP McASP (DIT)]
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET,
CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY
GP[15:8, 3:1] GPIO EXT_INT GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
PRODUCT PREVIEW
I2C0
SCL0, SDA0
I2C1
McASP1
AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0]
McASP0 (DIT Mode) AXR0[4:2] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0
DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1
McBSP1
TIMER0 DR0, CLKS0, CLKR0, CLKX0, FSR0, DX0, FSX0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000C McASP0EN I2C1EN TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (GPEN Register)
Figure Configuration Example McBSP McASP McASP (DIT)]
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, CLKOUT2
GPIO EXT_INT
GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
HD[15:0] HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, SCL1, SDA1 I2C1 McASP1 I2C0
AXR0[7:0], TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
McBSP1
McASP0
TIMER0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000F McASP0EN I2C1EN TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (GPEN Register)
Figure Configuration Example McASP)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) configuration examples (continued)
[31:16], ED[15:0] EA[21:2] CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, ARDY EMIF Clock, System, EMU, Reset CLKIN, CLKOUT3, CLKMODE0, PLLV, PLLG, OSCIN, OSCOUT, TMS, TDO, TDI, TCK, TRST, EMU[5:0], RESET, CLKOUT2
GPIO EXT_INT
GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7)
PRODUCT PREVIEW
HD[15:0] HINT, HHWIL, HRDY, HR/W, HCNTRL1, HCNTRL0, HCS, HDS2, HDS1, I2C1 McASP1 I2C0
AXR0[4:0] TINP0/AXR0[3], TOUT0/AXR0[2], TOUT1/AXR0[4] TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0
DR1, CLKS1, CLKR1, CLKX1, FSR1, DX1, FSX1
McBSP1
McASP0
TIMER0 McBSP0 TIMER1
Shading denotes peripheral module available this configuration. DEVCFG Register Value: 0x0000 000E McASP0EN I2C1EN TOUT0SEL TOUT1SEL EKSRC HPI_EN(HD14) GP2EN (GPEN Register)
Figure Configuration Example McBSP McASP)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
DEVICE CONFIGURATIONS (CONTINUED) debugging considerations
recommended that external connections provided peripheral selection/device configuration pins, including HD[14:12, CLKMODE0. Although internal pullup resistors exist these pins, providing external connectivity adds convenience user debugging flexibility switching operating modes. Internal pullup/pulldown resistors also exist non-configuration pins data (HD[15, 11:9, 7:5, 2:0]). proper device operation, oppose internal pullup/pulldown resistors these non-configuration pins with external pullup/pulldown resistors. external controller provides signals these non-configuration pins, these signals must driven default state pins reset, driven all. internal pullup/pulldown resistors device pins, terminal functions table.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
TERMINAL FUNCTIONS
terminal functions table identifies external signal names, associated (ball) numbers along with mechanical package designator, type O/Z, I/O/Z), whether internal pullup/pulldown resistors functional description. more detailed information device configuration, peripheral selection, multiplexed/shared pins, debugging considerations, Device Configurations section this data sheet.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions
SIGNAL NAME TYPE IPD/ CLOCK/PLL CONFIGURATION CLKIN CLKOUT2/GP[2] CLKOUT3 CLKMODE0 PLLV PLLG OSCIN OSCOUT TRST EMU5 EMU4 EMU3 EMU2 EMU1 EMU0 RESET GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/ AMUTEIN0 GP[4](EXT_INT4)/ AMUTEIN1 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Clock Input Clock output half device speed (O/Z) [default] (SYSCLK2 internal signal from clock generator) this programmed GP[2] (I/O/Z) Programmable clock output (OSC Divider internal signal from clock generator) Clock generator input clock source select Oscillator pads (OSCIN, OSCOUT directly from crystal oscillator) CLKIN square wave [default] Analog power (1.2 Analog ground Crystal oscillator Input (XI) Crystal oscillator output (XO) JTAG EMULATION JTAG test-port mode select JTAG test-port data JTAG test-port clock JTAG test-port reset Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Reserved future use, leave unconnected. Emulation Emulation Device reset Nonmaskable interrupt Edge-driven (rising edge) General-purpose input/output pins (I/O/Z) which also function external interrupts [default] Edge-driven Polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[4] GP[5] pins also function AMUTEIN1 ASP1 mute McASP1 input AMUTEIN0 McASP0 mute input, respectively, enabled INSTAT McASP AMUTE register. JTAG test-port data DESCRIPTION
RESETS INTERRUPTS
Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) Analog signal (PLL Filter) EMU0 EMU1 pins internally pulled with 30-k resistors; therefore, emulation normal operation, external pullup/pulldown resistors necessary. However, boundary scan operation, pull down EMU1 EMU0 pins with dedicated resistor.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME TYPE IPD/ HOST-PORT INTERFACE (HPI) HINT/GP[1] HCNTL1/AXR1[1] HCNTL0/AXR1[3] Host interrupt (from host) [default] this programmed GP[1] (I/O/Z). Host control selects between control, address, data registers [default] McASP1 data (I/O/Z). Host control selects between control, address, data registers [default] McASP1 data (I/O/Z). Host half-word select first second half-word (not necessarily high order) [default] McASP1 receive frame sync left/right clock (LRCLK) (I/O/Z). Host read write select [default] McASP1 data (I/O/Z). Host-port data pins (I/O/Z) [default] general-purpose input/output pins (I/O/Z) Used transfer data, address, control data address Also controls initialization modes reset pullup/pulldown resistors Device Endian mode (HD8) Endian Little Endian Boot mode (HD[4:3]) width 32-bit, boot width 8-bit, Asynchronous external boot with default timings (default mode) width 16-bit, Asynchronous external boot width 32-bit, Asynchronous external boot HPI_EN (HD14) disabled, McASP1 I2C0 enabled enabled, McASP1 I2C0 disabled (default) proper device operation, HD12 must externally pulled down with resistor. Other pins 11:9, 7:5, 2:0] have pullups/pulldowns [15, (IPUs/IPDs). proper device operation, oppose these pins with external IPUs/IPDs reset. more details, Device Configurations section this data sheet. Host-port data (I/O/Z) default] McASP1 receive high-frequency master clock (I/O/Z). Host-port data (I/O/Z) default] McASP1 transmit high-frequency master clock (I/O/Z). Host-port data (I/O/Z) default] this programmed (I/O/Z). Host-port data (I/O/Z) default] McASP1 mute output (I/O/Z). Host-port data (I/O/Z) default] McASP1 transmit frame sync left/right clock (LRCLK) (I/O/Z). Host-port data (I/O/Z) default] McASP1 data (I/O/Z). DESCRIPTION
HHWIL/AFSR1 HR/W/AXR1[0] HD15/GP[15]
HD14/GP[14]
PRODUCT PREVIEW
HD13/GP[13]
HD12/GP[12]
HD11/GP[11]
HD10/GP[10]
HD9/GP[9]
I/O/Z
HD8/GP[8]
HD7/GP[3] HD6/AHCLKR1 HD5/AHCLKX1 HD4/GP[0] HD3/AMUTE1 HD2/AFSX1 HD1/AXR1[7]
HD0/AXR1[4] Host-port data (I/O/Z) default] McASP1 data (I/O/Z). Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME HAS/ACLKX1 HCS/AXR1[2] HDS1/AXR1[6] HDS2/AXR1[5] HRDY/ACLKR1 HOLDA HOLD BUSREQ ECLKIN TYPE IPD/ DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED) Byte-enable control Decoded from lowest bits internal address Byte-write enables most types memory connected SDRAM read write mask signal (SDQM) directly Memory space enables Enabled bits through word address Only asserted during external data access Host address strobe [default] McASP1 transmit clock (I/O/Z). Host chip select [default] McASP1 data (I/O/Z). Host data strobe [default] McASP1 data (I/O/Z). Host data strobe [default] McASP1 data (I/O/Z) Host ready (from host) [default] McASP1 receive clock (I/O/Z).
EMIF COMMON SIGNALS TYPES MEMORY
EMIF ARBITRATION Hold-request-acknowledge host Hold request from host request output External EMIF input clock source EMIF output clock depends EKSRC (DEVCFG.[16]). EKSRC EMIF output clock source internal SYSCLK3 signal from clock generator (default). EKSRC ECLKOUT based external EMIF input clock source (ECLKIN). Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable Asynchronous memory ready input EMIF ADDRESS EA21 EA20 EA19 EA18 EA17 External address (word address)
EMIF ASYNCHRONOUS/SYNCHROUS MEMORY CONTROL
ECLKOUT
ARE/SDCAS/ SSADS AOE/SDRAS/ SSOE AWE/SDWE/ SSWE ARDY
EA16 Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME EA15 EA14 EA13 EA12 EA11 EA10 ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 EMIF DATA I/O/Z External data pins (ED[31:16] pins applicable package only) External address (word address) TYPE IPD/ EMIF ADDRESS (CONTINUED) DESCRIPTION
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Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME GP[4](EXT_INT4)/ AMUTEIN1 HD3/AMUTE1 HRDY/ACLKR1 HD6/AHCLKR1 HAS/ACLKX1 HD5/AHCLKX1 MULTICHANNEL AUDIO SERIAL PORT (McASP1) I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z General-purpose input/output external interrupt (I/O/Z) [default] McASP1 mute input (I/O/Z). Host-port data (I/O/Z) default] McASP1 mute output (I/O/Z). Host ready (from host) [default] McASP1 receive clock (I/O/Z). Host-port data (I/O/Z) default] McASP1 receive high-frequency master clock (I/O/Z). Host address strobe [default] McASP transmit clock (I/O/Z). Host-port data (I/O/Z) default] McASP1 transmit high-frequency master clock (I/O/Z). Host half-word select first second half-word (not necessarily high order) [default] McASP1 receive frame sync left/right clock (LRCLK) (I/O/Z). Host-port data (I/O/Z) default] McASP1 transmit frame sync left/right clock (LRCLK) (I/O/Z). Host-port data (I/O/Z) default] McASP1 data (I/O/Z). Host data strobe [default] McASP1 data (I/O/Z). Host data strobe [default] McASP1 data (I/O/Z). Host-port data (I/O/Z) default] McASP1 data (I/O/Z). Host control selects between control, address, data registers [default] McASP1 data (I/O/Z). Host chip select [default] McASP1 data (I/O/Z). Host control selects between control, address, data registers [default] McASP1 data (I/O/Z). I/O/Z External data pins (ED[31:16] pins applicable package only) TYPE IPD/ EMIF DATA (CONTINUED) DESCRIPTION
HHWIL/AFSR1
I/O/Z
HD2/AFSX1 HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1]
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
HR/W/AXR1[0] I/O/Z Host read write select [default] McASP1 data (I/O/Z). Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME GP[5](EXT_INT5)/ AMUTEIN0 CLKX1/AMUTE0 CLKR0/ACLKR0 TINP1/AHCLKX0 CLKX0/ACLKX0 CLKS0/AHCLKR0 FSR0/AFSR0 FSX0/AFSX0 TYPE IPD/ DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT (McASP0) I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z General-purpose input/output external interrupt (I/O/Z) [default] McASP0 mute input (I/O/Z). McBSP1 transmit clock (I/O/Z) [default] McASP0 mute output (I/O/Z). McBSP0 receive clock (I/O/Z) [default] McASP0 receive clock (I/O/Z). Timer input [default] McBSP0 transmit high-frequency master clock (I/O/Z). McBSP0 transmit clock (I/O/Z) [default] McASP0 transmit clock (I/O/Z). McBSP0 external clock source opposed internal) [default] McASP0 receive high-frequency master clock (I/O/Z). McBSP0 receive frame sync (I/O/Z) [default] McASP0 receive frame sync left/right clock (LRCLK) (I/O/Z). McBSP0 transmit frame sync (I/O/Z) [default] McASP0 transmit frame sync left/right clock (LRCLK) (I/O/Z). McBSP1 receive frame sync (I/O/Z) [default] McASP0 data (I/O/Z). McBSP1 receive clock (I/O/Z) [default] McASP0 data (I/O/Z). McBSP1 rransmit data (O/Z) [default] McASP0 data (I/O/Z). Timer output [default] McASP0 data (I/O/Z). Timer input [default] McASP0 data (I/O/Z). Timer output [default] McASP0 data (I/O/Z). McBSP0 transmit data (O/Z) [default] McASP0 data (I/O/Z). McBSP0 receive data [default] McASP0 data (I/O/Z). TIMER TOUT1/AXR0[4] TINP1/AHCLKX0 Timer output [default] McASP0 data (I/O/Z). Timer input [default] McBSP0 transmit high-frequency master clock (I/O/Z). TIMER0 TOUT0/AXR0[2] Timer output [default] McASP0 data (I/O/Z). TINP0/AXR0[3] Timer input [default] McASP0 data (I/O/Z). Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.)
PRODUCT PREVIEW
FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0]
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Terminal Functions (Continued)
SIGNAL NAME TYPE IPD/ DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT (McBSP1) CLKS1/SCL1 CLKR1/AXR0[6] CLKX1/AMUTE0 DR1/SDA1 DX1/AXR0[5] FSR1/AXR0[7] FSX1 I/O/Z I/O/Z I/O/Z I/O/Z McBSP1 external clock source opposed internal) [default] I2C1 clock (I/O/Z). McBSP1 receive clock (I/O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP1 transmit clock (I/O/Z) [default] McASP0 mute output (I/O/Z). McBSP1 receive data [default] I2C1 data (I/O/Z). McBSP1 transmit data (O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP1 receive frame sync (I/O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP1 transmit frame sync McBSP0 external clock source opposed internal) [default] McASP0 receive high-frequency master clock (I/O/Z). McBSP0 receive clock (I/O/Z) [default] McASP0 receive clock (I/O/Z). McBSP0 transmit clock (I/O/Z) [default] McASP0 transmit clock (I/O/Z). McBSP0 receive data [default] McASP0 TX/RX data (I/O/Z). McBSP0 transmit data (O/Z) [default] McASP0 TX/RX data (I/O/Z). McBSP0 receive frame sync (I/O/Z) [default] McASP0 receive frame sync left/right clock (LRCLK) (I/O/Z). McBSP0 transmit frame sync (I/O/Z) [default] McASP0 transmit frame sync left/right clock (LRCLK) (I/O/Z).
MULTICHANNEL BUFFERED SERIAL PORT (McBSP0) CLKS0/AHCLKR0 CLKR0/ACLKR0 CLKX0/ACLKX0 DR0/AXR0[0] DX0/AXR0[1] FSR0/AFSR0 FSX0/AFSX0 I/O/Z I/O/Z I/O/Z I/O/Z
INTER-INTEGRATED CIRCUIT (I2C1) CLKS1/SCL1 DR1/SDA1 SCL0 I/O/Z I/O/Z I/O/Z McBSP1 external clock source opposed internal) [default] I2C1 clock (I/O/Z). McBSP1 receive data [default] I2C1 data (I/O/Z). I2C0 clock.
INTER-INTEGRATED CIRCUIT (I2C0) SDA0 I/O/Z I2C0 data. Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.)
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME TYPE IPD/ DESCRIPTION
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) HD15/GP[15] Host-port data pins (I/O/Z) [default] general-purpose input/output pins (I/O/Z) Used transfer data, address, control Also controls initialization modes reset pullup/pulldown resistors Device Endian mode (HD8) Endian Little Endian Boot mode (HD[4:3]) width 32-bit, boot width 8-bit, Asynchronous external boot with default timings (default mode) width Asynchronous external boot 16-bit, width 32-bit, Asynchronous external boot HPI_EN (HD14) disabled, McASP1 I2C0 enabled enabled, McASP1 I2C0 disabled (default) device proper operation, HD12 must externally pulled down with resistor. Other pins [15, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). ullu ulldowns proper device operation, oppose these pins with external IPUs/IPDs reset. more details, Device Configurations section this data sheet. General-purpose input/output pins (I/O/Z) which also function external interrupts [default] Edge-driven Polarity independently selected External Interrupt Polarity Register bits (EXTPOL.[3:0]) GP[4] GP[5] pins also function AMUTEIN1 ASP1 mute input McASP1 AMUTEIN0 McASP0 mute input, respectively, enabled INSTAT McASP AMUTE register. I/O/Z I/O/Z I/O/Z Host-port data (I/O/Z) [default] general-purpose input/output (I/O/Z) Clock output half device speed (O/Z) [default] this programmed GP[2] pin. Host interrupt (from host) [default] this programmed GP[1] (I/O/Z). Host-port data (I/O/Z) default] this programmed GP[0] (I/O/Z).
HD14/GP[14]
HD13/GP[13]
HD12/GP[12]
I/O/Z
HD11/GP[11]
PRODUCT PREVIEW
HD10/GP[10]
HD9/GP[9]
HD8/GP[8] GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5)/ AMUTEIN0 GP[4](EXT_INT4)/ AMUTEIN1 HD7/GP[3] CLKOUT2/GP[2] HINT/GP[1] HD4/GP[0]
I/O/Z
RESERVED TEST RSV0 RSV1 Reserved. (Leave unconnected, connect power ground) Reserved. (Leave unconnected, connect power ground)
RSV2 Reserved. (Leave unconnected, connect power ground) Input, Output, High impedance, Supply voltage, Ground Internal pulldown, Internal pullup. (These IPD/IPU signal pins feature 30-k resistor. pull signal opposite supply rail, resistor should used.) Analog signal
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Terminal Functions (Continued)
SIGNAL NAME DVDD CVDD Input, Output, High impedance, Supply voltage, Ground supply voltage 1.2-V supply voltage 3.3-V TYPE SUPPLY VOLTAGE PINS DESCRIPTION
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME CVDD GROUND PINS Input, Output, High impedance, Supply voltage, Ground Ground pins 1.2-V supply voltage TYPE DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED)
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Terminal Functions (Continued)
SIGNAL NAME Input, Output, High impedance, Supply voltage, Ground Ground pins TYPE GROUND PINS (CONTINUED) DESCRIPTION
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Terminal Functions (Continued)
SIGNAL NAME Input, Output, High impedance, Supply voltage, Ground Ground pins TYPE GROUND PINS (CONTINUED) DESCRIPTION
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
development support
offers extensive line development tools TMS320C6000 platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. following products support development C6000 DSP-based applications: Software Development Tools: Code Composer Studio Integrated Development Environment (IDE): including Editor C/C++/Assembly Code Generation, Debug plus additional development tools Scalable, Real-Time Foundation Software (DSP/BIOS), which provides basic run-time target software needed support application. Hardware Development Tools: Extended Development System (XDS) Emulator (supports C6000 multiprocessor system debug) (Evaluation Module) TMS320 Development Support Reference Guide (SPRU011) contains information about development-support products TMS320 family member devices, including documentation. this document further information TMS320 documentation TMS320 support products from Texas Instruments. additional document, TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320 DSP-related products from other companies industry. receive TMS320 literature, contact Literature Response Center 800/477-8924. complete listing development-support tools TMS320C6000 platform, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL) select "Find Development Tools". device-specific tools, under "Semiconductor Products", select "Digital Signal Processors", choose product family, select particular device. information pricing availability, contact nearest field sales office authorized distributor. offers extensive line development tools TMS320C6000 platform, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules.
Code Composer Studio, DSP/BIOS, XDS, TMS320 trademarks Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
device development-support tool nomenclature designate stages product development cycle, assigns prefixes part numbers TMS320 devices support tools. Each TMS320 commercial family member three prefixes: TMX, TMP, TMS. Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX TMDX) through fully qualified production devices/tools (TMS TMDS). Device development evolutionary flow: Experimental device that necessarily representative final device's electrical specifications Final silicon that conforms device's electrical specifications completed quality reliability verification Fully qualified production device
Support tool development evolutionary flow:
PRODUCT PREVIEW
TMDX
Development-support product that completed Texas Instruments internal qualification testing. Fully qualified development-support product
TMDS
devices TMDX development-support tools shipped against following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, GFN), temperature range (for example, blank default commercial temperature range), device speed range megahertz (for example, -225 MHz). Figure provides legend reading complete device name TMS320C6000 family member.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
device development-support tool nomenclature (continued) Table TMS320C6713 Device Part Numbers (P/Ns) Ordering Information
CORE VOLTAGE DEVICE ORDERABLE C6713 TMS320C6713GFN225 TMS320C6713GFN150 TMS320C6713PYP150 MHz/1350 MFLOPS MHz/900 MFLOPS MHz/900 MFLOPS 90_C 90_C 90_C DEVICE SPEED CVDD (CORE) DVDD (I/O) OPERATING CASE TEMPERATURE RANGE
PREFIX Experimental device Prototype device Qualified device MIL-PRF-38535, High (non-38535)
6713
DEVICE SPEED RANGE
DEVICE FAMILY TMS320 family
TEMPERATURE RANGE (DEFAULT: 90°C) Blank 90°C, commercial temperature -40°C 105°C, extended temperature PACKAGE TYPE 256-pin plastic 352-pin plastic 352-pin plastic 352-pin plastic 384-pin plastic 340-pin plastic 384-pin plastic 352-pin plastic 288-pin plastic MicroStar BGAt 208-pin PowerPADt plastic DEVICE C6000 DSP: 6201 6202 6202B 6203B 6203C
TECHNOLOGY CMOS
6204 6205 6211 6211B
6414 6415 6416 6701
6711 6711B 6712 6713
Ball Grid Array Quad Flatpack
Figure TMS320C6000 Device Nomenclature (Including TMS320C6713 Device)
MicroStar PowerPAD trademarks Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
documentation support
Extensive documentation supports TMS320 family generations devices from product announcement through applications development. types documentation available include: data sheets, such this document, with design specifications; complete user's reference guides devices tools; technical briefs; development-support tools; on-line help; hardware software applications. following brief, descriptive list support documentation specific C6000 devices: TMS320C6000 Instruction Reference Guide (literature number SPRU189) describes C6000 (DSP core) architecture, instruction set, pipeline, associated interrupts. TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes functionality peripherals available C6000 platform devices, such external memory interface (EMIF), host-port interface (HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access (EDMA) controller, expansion (XB), clocking phase-locked loop (PLL); power-down modes. This guide also includes information internal data program memories. PowerPAD Thermally Enhanced Package Technical brief (literature number SLMA002) focuses specifics integrating PowerPAD package into printed circuit board design make optimum thermal efficiencies designed into PowerPAD package.
PRODUCT PREVIEW
TMS320C6000 Technical Brief (literature number SPRU197) gives introduction C62x/C67x devices, associated development tools, third-party support. tools support documentation electronically available within Code Composer Studio Integrated Development Environment (IDE). complete listing C6000 latest documentation, visit Texas Instruments site Worldwide http://www.ti.com uniform resource locator (URL). Worldwide application report Begin Development Today with TMS320C6713 Floating-Point (literature number SPRA809), which describes more detail similarities/differences between C6713 C6711 C6000 devices.
C62x trademark Texas Instruments.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
clock generator, oscillator,
TMS320C6713 includes flexible clock generator module consisting oscillator, with several dividers that different clocks generated different parts system (i.e., core, Internal Peripheral Control, External Memory Interface EMIF, Audio Peripheral Serial Clocks). Figure illustrates clock generator logic.
+1.2 CLKMODE0 CLKIN CVDD OSCIN OSCOUT
OSCDIV1
PLLV 0.01 PLLG
PLLOUT
PLLREF
DIVIDER
PLLEN
DIVIDER
Osc.
DIVIDER
DIVIDER
CLKOUT3 System ECLKIN
AUXCLK (Internal Clock Source McASP0 McASP1)
SYSCLK2 (Peripherals CLKOUT2) SYSCLK3
(EMIF Clock Input)
EKSRC (DEVCFG.[4])
C6713 Exact values these components depend choice crystal
EMIF
ECLKOUT
Figure Clock Generator Logic clock sourced either from externally generated 3.3-V clock input CLKIN pin, from on-chip oscillator external crystal circuit attached device. oscillator supports fundamental mode crystals MHz. This reference clock (AUXCLK) also directly available McASP modules internal serial port clock; divided down programmable divider (/1, /32) output CLKOUT3 other system. input clock source then either divided down /32) then multiplied factor x16. Either input clock output PLLEN selected) then serves high-frequency reference clock rest system. core clock, peripheral control clock, EMIF clock divided down from this high-frequency clock (each with unique divider) example, with input output configured MHz, core operated (/2) while EMIF configured operate rate (/6).
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SYSCLK1 (DSP Core Clock)
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
clock generator, oscillator, (continued)
EMIF itself clocked from totally unrelated (asynchronous) reference clock input ECLKIN specific EMIF frequency needed, from on-chip clock generation logic. settings multiplier each dividers clock generation block reconfigured software time. either input changed multiplier changed, then software must enter bypass first stay bypass until enough time lock (see electrical specifications). clock generator dedicated power supply pins, recommended that these pins filtered with pair ferrite beads series with each supply line, bypassed with pair capacitors (0.1 0.01 close device pins (PLLV, PLLG) possible shown Figure 12). Similarly, lowest jitter oscillator circuit, recommended that pair 470-pF capacitors connected between isolated (not directly connected board supply) CVDD either side oscillator. This helps cancel switching noise from other circuits device. Note that there specific minimum maximum input clock block labeled Figure well core, peripheral control, EMIF. addition, there maximum output frequency PLL. clock generator must configured exceed these constraints (certain combinations external clock input, internal dividers, multiply ratios might supported). SYSCLK2 internal clock source peripheral control. SYSCLK2 (Divider must programmed half SYSCLK1 rate. example, configured divide-by-2 mode (/2), then must programmed divide-by-4 mode (/4). SYSCLK2 also tied directly CLKOUT2 (see Figure 12). detailed information clock generator (PLL oscillator registers) their associated software descriptions, Table through Table
PRODUCT PREVIEW
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
clock generator, oscillator, (continued)
PLLCSR Register (0x01B7 C100)
Reserved STABLE RW-0 Reserved PLLRST RW-1 PLLPWRDN R/W-0b PLLEN RW-0
Reserved
Legend: Read only, Read/Write; value after reset
Table Control/Status Register (PLLCSR)
31:7 NAME Reserved STABLE Reserved PLLRST Reserved PLLPWRDN DESCRIPTION Reserved. Read-only, writes have effect. Oscillator Input Stable. This indicates OSCIN/CLKIN input stabilized. OSCIN/CLKIN input stable. Oscillator counter finished counting (default). OSCIN/CLKIN input stable. Reserved. Read-only, writes have effect. Asserts RESET Reset Released. Reset Asserted (default). Reserved. Read-only, writes have effect. Select Power Down Operational (default). Placed Power-Down State. Mode Enable Bypass Mode (default). disabled. Divider bypassed. SYSCLK1/SYSCLK2/SYSCLK3 divided down directly from input reference clock. Enabled. Divider bypassed. SYSCLK1/SYSCLK2/SYSCLK3 divided down from output.
PLLEN
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
clock generator, oscillator, (continued)
PLLM Register (0x01B7 C110)
Reserved Reserved Legend: Read only, Read/Write; value after reset PLLM R/W-0 0111
Table Multiplier Control Register (PLLM)
31:5 NAME Reserved DESCRIPTION Reserved. Read-only, writes have effect. multiply mode [default 0111)]. 00000 01000 00001 01001 00010 01010 00011 01011 00100 01100 00101 01101 00110 01110 00111 01111 PLLM select values 10000 through 11111 supported.
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PLLM
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
clock generator, oscillator, (continued)
PLLDIV0, PLLDIV1, PLLDIV2, PLLDIV3 Registers (0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, 0x01B7 C120, respectively)
Reserved Reserved PLLDIVx R/W-x xxxx
DxEN
R/W-1
Legend: Read only, Read/Write; value after reset Default values PLLDIV0, PLLDIV1, PLLDIV2, PLLDIV3 bits 0000), 0000), 0001), 0001), respectively.
Table Wrapper Divider Registers (Prescaler Dividers
31:16 14:5 NAME Reserved DxEN Reserved DESCRIPTION Reserved. Read-only, writes have effect. Divider Enable (where denotes through Divider Disabled. clock output. Divider Enabled (default). Reserved. Read-only, writes have effect. Divider Ratio [Default values PLLDIV0, PLLDIV1, PLLDIV2, PLLDIV3 bits respectively]. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
PLLDIVx
Note that SYSCLK2 must half rate SYSCLK1. Therefore, divider ratio must times slower than example, then must
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
clock generator, oscillator, (continued)
OSCDIV1 Register (0x01B7 C124)
Reserved Reserved OSCDIV1 R/W-0 0111
OD1EN
R/W-1
Legend: Read only, Read/Write; value after reset
OSCDIV1 register controls oscillator divider CLKOUT3. CLKOUT3 signal does through path. Table Oscillator Divider Register (OSCDIV1)
NAME Reserved OD1EN Reserved DESCRIPTION Reserved. Read-only, writes have effect. Oscillator Divider Enable. Oscillator Divider Disabled. Oscillator Divider Enabled (default). Reserved. Read-only, writes have effect. Oscillator Divider Ratio [default 0111)]. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
PRODUCT PREVIEW
31:16 14:5
OSCDIV1
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, CVDD (see Note -0.3 1.35 Supply voltage range, DVDD (see Note -0.3 Input voltage range -0.3 DVDD Output voltage range -0.3 DVDD Operating case temperature ranges, 90_C Storage temperature range, Tstg -65_C 150_C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect VSS.
recommended operating conditions
CVDD DVDD Supply voltage, Core referenced Supply voltage, referenced Maximum supply voltage difference CVDD DVDD Maximum supply voltage difference DVDD CVDD High-level input voltage Low-level input voltage signals except TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3, SCL1, SDA1, SCL0, SDA0 TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3 signals except TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3, SCL1, SDA1, SCL0, SDA0 Low-level output current TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3 SCL1, SDA1, SCL0, SDA0 0.7*DVDD 0.3*DVDD 1.14 3.13 1.26 3.47 1.32 2.75 UNIT
High-level current output
Operating case temperature core supply should powered same time prior (and powered down after), supply. Systems should designed ensure that neither supply powered extended period time other supply below proper operating voltage.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
electrical characteristics over recommended ranges supply voltage operating case temperature (unless otherwise noted)
PARAMETER signals except TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3, SCL1, SDA1, SCL0, SDA0 TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3 signals except TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3, SCL1, SDA1, SCL0, SDA0 Low-level output voltage TDO, EMU[5:0], ECLKOUT, CLKOUT2, CLKOUT3 TEST CONDITIONS 0.8*DVDD UNIT
High-level output voltage
DVDD MIN,
DVDD MIN,
0.22*DVDD
SCL1 SDA1 SCL0 SDA0 SCL1, SDA1, SCL0,
DVDD MIN, DVDD MIN, DVDD DVDD C6713, CVDD NOM, clock C6713, CVDD NOM, clock C6713, DVDD NOM, clock
±150
Input current Off-state output current Supply current, memory access Supply current, peripherals Supply current, pins Input capacitance
PRODUCT PREVIEW
IDD2V
IDD2V IDD3V
Output capacitance test conditions shown MIN, MAX, NOM, appropriate value specified recommended operating conditions table. Measured with average activity (50% high/50% power). more details CPU, peripheral, activity, refer TMS320C6000 Power Consumption Summary application report (literature number SPRA486).
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION
Tester Electronics Output Under Test
Vcomm
Where: Vcomm 10-15-pF typical load-circuit capacitance
Figure Test Load Circuit Timing Measurements
signal transition levels
input output timing parameters referenced both logic levels.
Vref
Figure Input Output Voltage Reference Levels Timing Measurements rise fall transition timing parameters referenced input clocks, output clocks.
Vref MIN)
Vref MAX)
Figure Rise Fall Transition Time Voltage Reference Levels
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters board routing analysis
timing parameter values specified this data sheet include delays board routings. good board design practice, such delays must always taken into account. Timing values adjusted increasing/decreasing such delays. recommends utilizing available buffer information specification (IBIS) models analyze timing characteristics correctly. needed, external logic hardware such buffers used compensate timing differences. inputs, timing most impacted round-trip propagation delay from external device from external device DSP. This round-trip delay tends negatively impact input setup time margin, also tends improve input hold time margins (see Table Figure 16). Figure represents general transfer between external device. figure also represents board route delays they perceived external device.
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
Table IBIS Timing Parameters Example (see Figure
DESCRIPTION Clock route delay Minimum hold time Minimum setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time hold time requirement setup time requirement Data route delay
ECLKOUT (Output from DSP) ECLKOUT (Input External Device) Control Signals (Output from DSP) Control Signals (Input External Device) Data Signals (Output from External Device) Data Signals (Input DSP) Control signals include data Writes. Data signals generated during Reads from external device.
Figure IBIS Input/Output Timings
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
INPUT OUTPUT CLOCKS timing requirements CLKIN (see Figure
tc(CLKIN) tw(CLKINH) tw(CLKINL) tt(CLKIN) Cycle time, CLKIN Pulse duration, CLKIN high Pulse duration, CLKIN -150 -225 UNIT
Transition time, CLKIN reference points rise fall transitions measured MIN. CLKIN cycle time example, when CLKIN frequency MHz,
CLKIN
PRODUCT PREVIEW
Figure CLKIN Timings
switching characteristics over recommended operating conditions CLKOUT2 (see Figure
tc(CKO2) tw(CKO2H) tw(CKO2L) tt(CKO2) Cycle time, CLKOUT2 Pulse duration, CLKOUT2 high Pulse duration, CLKOUT2 PARAMETER -150 -225 UNIT
Transition time, CLKOUT2 reference points rise fall transitions measured MIN. 1/CPU clock frequency CLKOUT2
Figure CLKOUT2 Timings
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TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
INPUT OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions CLKOUT3 (see Figure
tc(CKO3) tw(CKO3H) tw(CKO3L) tt(CKO3) Cycle time, CLKOUT3 Pulse duration, CLKOUT3 high Pulse duration, CLKOUT3 PARAMETER -150 -225 UNIT
Transition time, CLKOUT3 reference points rise fall transitions measured MIN. 1/CPU clock frequency CLKOUT3
Figure CLKOUT3 Timings
timing requirements ECLKIN (see Figure
tc(EKI) tw(EKIH) tw(EKIL) tt(EKI) Cycle time, ECLKIN Pulse duration, ECLKIN high Pulse duration, ECLKIN -150 -225 UNIT
Transition time, ECLKIN reference points rise fall transitions measured MIN. ECLKIN
Figure ECLKIN Timings
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
PRODUCT PREVIEW
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
INPUT OUTPUT CLOCKS (CONTINUED) switching characteristics over recommended operating conditions (see Figure
tc(EKO) tw(EKOH) tw(EKOL) tt(EKO) td(EKIH-EKOH) td(EKIL-EKOL) PARAMETER Cycle time, ECLKOUT Pulse duration, ECLKOUT high Pulse duration, ECLKOUT Transition time, ECLKOUT Delay time, ECLKIN high ECLKOUT high -150 -225 UNIT
Delay time, ECLKIN ECLKOUT reference points rise fall transitions measured MIN. ECLKIN period high period ECLKIN period ECLKIN
PRODUCT PREVIEW
ECLKIN ECLKOUT
Figure ECLKOUT Timings
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
ASYNCHRONOUS MEMORY TIMING timing requirements asynchronous memory (see Figure 22-Figure
tsu(EDV-AREH) th(AREH-EDV) tsu(ARDY-EKOH) th(EKOH-ARDY) Setup time, valid before high Hold time, valid after high Setup time, ARDY valid before ECLKOUT high Hold time, ARDY valid after ECLKOUT high -150 -225 UNIT
ensure data setup time, simply program strobe width wide enough. ARDY internally synchronized. ARDY signal recognized cycle which setup hold time met. ARDY asynchronous input, pulse width ARDY signal should wide enough (e.g., pulse width ensure setup hold time met. Read setup, Read strobe, Read hold, Write setup, Write strobe, Write hold. These parameters programmed EMIF space control registers. ECLKOUT period
switching characteristics over recommended operating conditions asynchronous memory (see Figure 22-Figure
tosu(SELV-AREL) toh(AREH-SELIV) td(EKOH-AREV) tosu(SELV-AWEL) toh(AWEH-SELIV) td(EKOH-AWEV) PARAMETER Output setup time, select signals valid Output hold time, high select signals invalid Delay time, ECLKOUT high vaild Output setup time, select signals valid Output hold time, high select signals invalid -150 -225 UNIT
Delay time, ECLKOUT high vaild Read setup, Read strobe, Read hold, Write setup, Write strobe, Write hold. These parameters programmed EMIF space control registers. ECLKOUT period Select signals include: CEx, BE[3:0], EA[21:2], AOE; writes, include ED[31:0].
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
PRODUCT PREVIEW
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup ECLKOUT BE[3:0] EA[21:2] Address ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, AWE/SDWE/SSWE operate (identified under select signals), ARE, AWE, respectively, during asynchronous memory accesses. Read Data Strobe Ready Hold
PRODUCT PREVIEW
Figure Asynchronous Memory Read Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup ECLKOUT BE[3:0] EA[21:2] ED[31:0] AOE/SDRAS/SSOE ARE/SDCAS/SSADS AWE/SDWE/SSWE ARDY AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, AWE/SDWE/SSWE operate (identified under select signals), ARE, AWE, respectively, during asynchronous memory accesses. Write Data Address Strobe Ready Hold
Figure Asynchronous Memory Write Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
PRODUCT PREVIEW
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS-BURST MEMORY TIMING timing requirements synchronous-burst SRAM cycles (see Figure
tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read valid before ECLKOUT high -150 -225 UNIT
Hold time, read valid after ECLKOUT high C6713 SBSRAM interface takes advantage internal burst counter SBSRAM. Accesses default incrementing 4-word bursts, random bursts decrementing bursts done interrupting bursts progress. burst types sustain continuous data flow.
switching characteristics over recommended operating conditions synchronous-burst SRAM cycles (see Figure Figure
td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-ADSV) td(EKOH-OEV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) PARAMETER Delay time, ECLKOUT high valid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLKOUT high ARE/SDCAS/SSADS valid Delay time, ECLKOUT high AOE/SDRAS/SSOE valid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid -150 -225 UNIT
PRODUCT PREVIEW
Delay time, ECLKOUT high AWE/SDWE/SSWE valid C6713 SBSRAM interface takes advantage internal burst counter SBSRAM. Accesses default incrementing 4-word bursts, random bursts decrementing bursts done interrupting bursts progress. burst types sustain continuous data flow. ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, AWE/SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT BE[3:0] EA[21:2] ED[31:0] ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, AWE/SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses.
Figure SBSRAM Read Timing
ECLKOUT EA[21:2] ARE/SDCAS/SSADS AOE/SDRAS/SSOE AWE/SDWE/SSWE
BE[3:0]
ED[31:0]
ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, AWE/SDWE/SSWE operate SSADS, SSOE, SSWE, respectively, during SBSRAM accesses.
Figure SBSRAM Write Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
PRODUCT PREVIEW
TMS320C6713 FLOATING-POINT DIGITAL SIGNAL PROCESSOR
SYNCHRONOUS DRAM TIMING timing requirements synchronous DRAM cycles (see Figure
tsu(EDV-EKOH) th(EKOH-EDV) Setup time, read valid before ECLKOUT high -150 -225 UNIT
Hold time, read valid after ECLKOUT high C6713 SDRAM interface takes advantage internal burst counter SDRAM. Accesses default incrementing 4-word bursts, random bursts decrementing bursts done interrupting bursts progress. burst types sustain continuous data flow.
switching characteristics over recommended operating conditions synchronous DRAM cycles (see Figure 26-Figure
td(EKOH-CEV) td(EKOH-BEV) td(EKOH-BEIV) td(EKOH-EAV) td(EKOH-EAIV) td(EKOH-CASV) td(EKOH-EDV) td(EKOH-EDIV) td(EKOH-WEV) td(EKOH-RAS) PARAMETER Delay time, ECLKOUT high valid Delay time, ECLKOUT high valid Delay time, ECLKOUT high invalid Delay time, ECLK
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