File Number 4602.2 Radiation Hardened CMOS Dual SPDT Analog

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File Number 4602.2 Radiation Hardened CMOS Dual SPDT Analog

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HS-303RH-T
File Number
4602.2
Radiation Hardened CMOS Dual SPDT Analog Switch
Intersil's Satellite Applications Flow(SAF) devices fully tested guaranteed 100kRAD total dose. These Class devices processed standard flow intended meet cost shorter lead-time needs large volume satellite manufacturers, while maintaining high level reliability. HS-303RH-T analog switch monolithic device fabricated using Radiation Hardened CMOS technology Intersil dielectric isolation process latch-up free operation. Improved total dose hardness obtained layout (thin oxide tabs extending channel stop) processing (hardened gate oxide). This switch offers lowresistance switching performance analog voltages supply rails. "ON" resistance stays reasonably constant over full range operating voltage current. "ON" resistance also stays reasonably constant when exposed radiation, being typically pre-rad post 100kRAD(Si). Break-before-make switching controlled digital inputs.
Features
Class MIL-PRF-38535 Radiation Performance Gamma Dose RAD(Si) Latch-Up, Dielectrically Isolated Device Islands Compatible with Intersil HI-303 Series Analog Switches Analog Signal Range Leakage 100nA (Max, Post Rad) (Max, Post Rad) Operating Power 100µA (Max, Post Rad)
Pinouts
HS1-303RH-T (SBDIP), CDIP2-T14 VIEW
Specifications
Specifications Hard devices controlled Defense Supply Center Columbus (DSCC). numbers listed below must used when ordering. Detailed electrical specifications HS-303RH-T contained 5962-95813. "hot-link" provided from website downloading. Intersil's Quality Management Plan Plan), listing Class screening operations, available website.
HS9-303RH-T (FLATPACK) CDFP3-F14 VIEW
Ordering Information
ORDERING NUMBER 5962R9581301TCC 5962R9581301TXC PART NUMBER HS1-303RH-T HS9-303RH-T TEMP. RANGE (oC)
NOTE: Minimum order quantity units through distribution, units direct.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2001. Rights Reserved Satellite Applications Flow(SAF) trademark Intersil Americas Inc.
Functional Diagram
SBDIP TRUTH TABLE
LOGIC
SW1AND
Characteristics
DIMENSIONS: (2130µm 1930µm 279µm ±25.4µm) 11mils ±1mil METALLIZATION: Type: Thickness: SUBSTRATE POTENTIAL: Unbiased (DI) BACKSIDE FINISH: Gold PASSIVATION: Type: Silox (SiO2) Thickness: WORST CASE CURRENT DENSITY: 2.0e5 A/cm2 TRANSISTOR COUNT: PROCESS: Metal Gate CMOS, Dielectric Isolation
Metallization Mask Layout
HS-303RH-T
Intersil products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com

File Number 4602.2 Radiation Hardened CMOS Dual SPDT Analog

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