Tools Information FAQs Application Note HA0075E Reset Oscillator Circu
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HT56R64 TinyPowerA/D Type with 8-Bit
Tools Information FAQs Application Note HA0075E Reset Oscillator Circuits Application Note
Operating voltage: Dual Serial Interfaces: driver: operating modes: normal, slow, idle sleep 8-level subroutine nesting 8-channel 12-bit resolution converter 4-channel 12-bit output shared with lines voltage reset function 2.1V, 3.15V, 4.2V voltage detect function 2.2V, 3.3V, 4.4V manipulation instruction 15-Bit table read instructions powerful instructions 0.33ms instruction cycle with 12MHz system
fSYS=32768Hz: 2.2V~5.5V fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V fSYS=12MHz: 4.5V~5.5V
Program Memory: Data Memory: bidirectional lines TinyPower technology power operation Three pin-shared external interrupts lines
segment
Single 8-bit programmable Timer/Event Counter
with overflow interrupt 7-stage prescaler
Single 16-bit programmable Timer/Event Counter
clock VDD=5V
instructions executed machine
with overflow interrupt
External Crystal, oscillator Fully integrated 32KHz oscillator Externally supplied system clock option Watchdog Timer function PFD/Buzzer audio frequency generation
cycles
Power down wake-up functions reduce power
consumption
52/100-pin QFP, 64-pin LQFP packages
General Description
HT56R64 TinyPowerA/D Type with 8-bit high performance RISC architecture microcontroller, designed especially applications that interface directly analog signals which require interface. device includes integrated multi-channel Analog Digital Converter, four Pulse Width Modulation outputs driver. With fully integrated functions, designers provided with means easy communication with external peripheral hardware. benefits integrated A/D, LCD, functions, addition power consumption, high performance, flexibility low-cost, provides device with versatility wide range products home appliance industrial application areas. Some these products could include electronic metering, environmental monitoring, handheld instruments, electronically controlled tools, motor driving addition many others. unique Holtek TinyPower technology also gives device extremely current consumption characteristics, extremely important consideration present trend power battery powered applications. usual Holtek features such power down wake-up functions, oscillator options, programmable frequency divider, etc. combine ensure user applications require minimum external components.
Rev. 1.20
March 2009
HT56R64
Block Diagram
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Assignment
Rev. 1.20
March 2009
HT56R64
Description
Name Configuration Option Description Bidirectional 8-bit input/output port. Each individual this port configured wake-up input using PAWU register. Software instructions determine CMOS output Schmitt trigger input. pull-high resistor connected each using PAPU register. Pins PA0, shared with respectively, function which chosen configuration option. Pins PA0~PA3 also setup open drain pins using MISC register. Bidirectional 8-bit input/output port. Software instructions determine CMOS output Schmitt trigger input. pull-high resistor connected each using PBPU register. pin-shared with input pins. inputs selected software instructions. Once selected input, function pull-high resistor selections disabled automatically. Bidirectional 8-bit input/output port. Software instructions determine CMOS output Schmitt trigger input. pull-high resistor connected each using PDPU register. outputs, PWM0~PWM3, shared with pins PD0~PD3, function which chosen using registers. Pins PD4~PD7 pin-shared with INT0, INT1, TMR0 TMR1 respectively. COM2~COM0 common outputs. Control Register determines COM3/SEG32 configured segment driver common output driver.
PA0/BZ PA1/BZ PA3/PFD PA4~PA7
BZ/BZ
PB0/AN0~ PB7/AN7
PD0/PWM0~ PD3/PWM3 PD4/INT0 PD5/INT1 PD6/TMR0 PD7/TMR1 COM0~COM2 COM3/SEG32
Rev. 1.20
March 2009
HT56R64
Configuration Option
Name SEG31~SEG24 SEG23~SEG16
Description driver outputs panel segments. Control Register determines pins used segment drivers CMOS outputs. SEG8 SEG9 driver outputs. SEG10 pin-shared with Serial Interface Output line, SDO. SEG11 pin-shared with data line, data line SDA. SEG12, pin-shared with clock line, SCK, clock line SCL. SEG13 pin-shared with Serial Interface Select line, SCS. SEG14 pin-shared with Peripheral Clock line, PCLK. SEG15 pin-shared with Peripheral Interrupt line, PINT. SEG8~SEG15 lines chosen either segment drivers logical outputs using control bits. driver outputs panel segments. SEG0~SEG7 chosen either segment drivers logical outputs using control bits. OSC1, OSC2 connected external network external crystal, determined configuration option, internal system clock. system clock option selected, OSC2 used measure system clock frequency. OSC3 OSC4 connected 32768Hz crystal oscillator form real time clock timing purposes fSUB fSL. Schmitt Trigger reset input. Active low. power supply Reference voltage input pin. maximum voltage, connect VDD, VLCD voltage pump Positive power supply Analog positive power supply. Negative power supply, ground Analog negative power supply, ground
SEG8~SEG9 SEG10/SDO SEG11/SDI/SDA SEG12/SCK/SCL SEG13/SCS SEG14/PCLK SEG15/PINT
PCLK PINT
SEG0~SEG7
OSC1 OSC2 OSC3 OSC4 VLCD1 VREF VMAX VLCD2, AVDD AVSS Note:
Crystal
Description table represents largest package available, therefore some pins functions available smaller package types.
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Total .150mA Total Power Dissipation .500mW Storage Temperature .-50°C 125°C Operating Temperature.-40°C 85°C Total.-100mA
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
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March 2009
HT56R64
D.C. Characteristics
Symbol Parameter Test Conditions Conditions fSYS=4MHz Operating Voltage fSYS=8MHz fSYS=12MHz IDD1 Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current Mode, Filter Operating Current Mode, Filter Off) Operating Current (Crystal OSC, OSC) Operating Current (Crystal OSC, OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, OSC) Operating Current (Slow Mode, fM=4MHz) (Crystal OSC, OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, OSC) Operating Current (Slow Mode, fM=8MHz) (Crystal OSC, OSC) Operating Current (fSYS=32768Hz (note 32K_INT internal OSC) Operating Current (fSYS=32768Hz (note 32K_INT internal OSC) Operating Current (fSYS=32768Hz (note 32K_INT internal OSC) load, fSYS=fM=1MHz load, fSYS=fM=2MHz load, fSYS=fM=4MHz load, fSYS=fM=4MHz load, fSYS=fM=4MHz load, fSYS=fM=8MHz load, fSYS=fM=12MHz load, fSYS=fSLOW=500kHz load, fSYS=fSLOW=1MHz load, fSYS=fSLOW=2MHz load, fSYS=fSLOW=1MHz load, fSYS=fSLOW=2MHz load, fSYS=fSLOW=4MHz load, off, off, (note type, VLCD=VDD, bias (RBIAS=400kW) load, off, off, (note type, VLCD=VDD, bias (RBIAS=600kW) load, off, off, (note type bias, VLCD=3V Min. Typ. Max. 1200 1380 Ta=25°C Unit
IDD2
IDD3
IDD4
IDD5 IDD6 IDD7
IDD8
IDD9
IDD10
IDD11
IDD12
IDD13
IDD14
IDD15
IDD16
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March 2009
HT56R64
Test Conditions VLVR Voltage Reset Voltage VLVD Voltage Detector Voltage IOL1 Port Sink Current Port Source Current Conditions load, off, off, load, system HALT,
Symbol
Parameter Operating Current (fSYS=32768Hz (note 32K_INT internal OSC) Standby Current Sleep) (fSYS, fSUB, fLCD, fWDT=off) Standby Current Sleep) (fSYS, fLCD=off; fLCD, fWDT=fSUB=32768Hz (note 32K_INT OSC) Standby Current Idle) (fSYS, fWDT=off; (note fSUB=32768Hz (note 32K_INT OSC) Standby Current Idle) (fSYS, fWDT=off; (note fSUB=32768Hz (note 32K_INT OSC) Standby Current Idle) (fSYS, fWDT=off; (note fSUB=32768Hz (note 32K_INT OSC) Standby Current Idle) (fSYS, fWDT=off; (note fSUB=32768Hz (note 32K_INT OSC) Standby Current Idle) (fSYS=on, fSYS=fM=4MHz, fWDT, fLCD=off, (note 3)=fSUB=32768Hz (note 32K_INT OSC) Input Voltage Ports, Input High Voltage Ports, Input Voltage (RES) Input High Voltage (RES)
Min. 0.7VDD 0.9VDD 1.98 2.98 3.98 2.08 3.12 4.12
Typ. 2.10 3.15 4.20 2.20 3.30 4.40
Max. 0.3VDD 0.4VDD 2.22 3.32 4.42 2.32 3.50 4.70
Unit
IDD17
ISTB1
ISTB2
load, system HALT,
ISTB3
load, system HALT, off, (note bias, type, VLCD=VDD load, system HALT, off, (note bias, type, VLCD=3V load, system HALT, off, (note type, VLCD=VDD, bias (RBIAS=400kW) load, system HALT, off, (note type, VLCD=VDD, bias (RBIAS=600kW) load, system HALT, off, off, PCLK PCLK=fSYS/8 Configuration option: 2.1V Configuration option: 3.15V Configuration option: 4.2V Configuration option: 2.2V Configuration option: 3.3V Configuration option: 4.4V VOL=0.1VDD (OTP version) VOH=0.9VDD (OTP version)
ISTB4
ISTB5
ISTB6
ISTB7
VIL1 VIH1 VIL2 VIH2
IOH1
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HT56R64
Test Conditions Conditions VOL=0.1VDD
Symbol
Parameter Common Segment Current Common Segment Current Pull-high Resistance Ports Input Voltage Input Reference Voltage Range Differential Non-Linearity Integral Non-Linearity Additional Power Consumption Converter Used
Min. -180
Typ. -160 -360
Max. AVDD VREF AVDD+
Unit
IOL2
IOH2
VOH=0.9VDD
52QFP, 64LQFP 100QFP AVDD=5V AVDD=5V, VREF=AVDD, tAD=0.5ms AVDD=5V, VREF=AVDD, tAD=0.5ms
VREF IADC Note:
32768Hz slow start mode (RTCC.4=1) D.C. current measurement. waveform Type condition. internal clock Buzzer, RTC, Time base WDT. Both Timer/Event Counters off. Timer filter disabled test conditions.
Rev. 1.20
March 2009
HT56R64
A.C. Characteristics
Symbol Parameter Test Conditions Conditions 2.2V~5.5V fSYS1 System Clock (Crystal OSC, OSC) System Clock (RTC Crystal OSC) Frequency Timer Frequency (TMR0/TMR1) Period External Reset Pulse Width Voltage Reset Time Time LVDO Become Stable, LVDC Enabled System Start-up Timer Period System Start-up Timer Period XTAL oscillator System Start-up Timer Period External External Clock Interrupt Pulse Width Clock Period Conversion Time Start *tSYS=1/fSYS1 1/fSYS2 3.3V~5.5V 4.5V~5.5V fSYS2 fRTCOSC 2.2V~5.5V fTIMER 3.3V~5.5V 4.5V~5.5V fRC32K tRES tLVR tLVDO tSST1 tSST2 tSST3 tINT tADC tON2ST Note: Power-on Wake-up from Power Down Mode Wake-up from Power Down Mode 2.2V~5.5V, After Trim 2.2V~5.5V Min. 28.1 Typ. 32768 32768 31.25 1024 1024 Max. 4000 8000 12000 4000 8000 12000 34.4 Ta=25°C Unit tSYS* tSYS* tSYS*
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March 2009
HT56R64
System Architecture
factor high-performance features Holtek range microcontrollers attributed their internal system architecture. range devices take advantage usual features found within RISC microcontrollers providing increased speed operation enhanced performance. pipelining scheme implemented such that instruction fetching instruction execution overlapped, hence instructions effectively executed cycle, with exception branch call instructions. 8-bit wide used practically instruction operations, which carries arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. internal data path simplified moving data through Accumulator ALU. Certain internal registers implemented Data Memory directly indirectly addressed. simple addressing methods these registers along with additional architectural features ensure that minimum external components required provide functional control system with maximum reliability flexibility. This makes device suitable low-cost, high-volume production controller applications. Clocking Pipelining main system clock, derived from either Crystal/Resonator oscillator subdivided into four internally generated non-overlapping clocks, T1~T4. Program Counter incremented beginning clock during which time instruction fetched. remaining T2~T4 clocks carry decoding execution functions. this way, T1~T4 clock cycle forms instruction cycle. Although fetching execution instructions takes place consecutive instruction cycles, pipelining structure microcontroller ensures that instructions effectively executed instruction cycle. exception this instructions where contents Program Counter changed, such subroutine calls jumps, which case instruction will take more instruction cycle execute. When oscillator used, OSC2 free phase clock synchronizing pin. This phase clock frequency fSYS/4 with high/low duty cycle. instructions involving branches, such jump call instructions, machine cycles required complete instruction execution. extra cycle required program takes cycle first obtain actual jump call address then another cycle actually execute branch. requirement this extra cycle should taken into account programmers timing sensitive applications.
illa
System Clocking Pipelining
Instruction Fetching
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March 2009
HT56R64
Program Counter During program execution, Program Counter used keep track address next instruction executed. automatically incremented each time instruction executed except instructions, such that demand jump non-consecutive Program Memory address. must noted that only lower bits, known Program Counter Register, directly addressable. When executing instructions requiring jumps non-consecutive addresses such jump instruction, subroutine call, interrupt reset, etc., microcontroller manages program control loading required address into Program Counter. conditional skip instructions, once condition been met, next instruction, which already been fetched during present instruction execution, discarded dummy cycle takes place while correct instruction obtained. lower byte Program Counter, known Program Counter register PCL, available program control readable writable register. transferring data directly into this register, short program jump executed directly, however, only this byte available manipulation, jumps limited present page memory, that locations. When such program jumps executed should also noted that dummy cycle will inserted. lower byte Program Counter fully accessible under program control. Manipulating might cause program branching, extra cycle needed pre-fetch. Further information register found Special Function Register section.
Program Counter Bits
Mode
Initial Reset External Interrupt External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow SPI/I Interrupt Multi-Function Interrupt Skip Loading Jump, Call Branch Return from Subroutine
Program Counter PC11 PC10
Program Counter Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction code address bits @7~@0: bits S11~S0: Stack register bits
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HT56R64
Stack This special part memory which used save contents Program Counter only. stack levels neither part data part program space, neither readable writeable. activated level indexed Stack Pointer, neither readable writeable. subroutine call interrupt acknowledge signal, contents Program Counter pushed onto stack. subroutine interrupt routine, signaled return instruction, RETI, Program Counter restored previous value from stack. After device reset, Stack Pointer will point stack.
Increment Decrement INCA, INC, DECA, Branch decision, JMP, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
Program Memory location where user code program stored. this device Program Memory type, which means programmed only time. using appropriate programming tools, this memory device offer users flexibility conveniently debug develop their applications while also offering means field programming. program memory used store program instructions, which executed. also contains data, table, interrupt entries, organized into bits format which addressed program counter table pointer. CALL instructions provide only bits address allow branching within program memory. When doing CALL instruction. Structure Program Memory capacity bits. Program Memory addressed Program Counter also contains data, table information interrupt entries. Table data, which setup location within Program Memory, addressed separate table pointer register. Special Vectors Within Program Memory, certain locations reserved special usage such reset interrupts.
Location 000H
stack full enabled interrupt takes place, interrupt request flag will recorded acknowledge signal will inhibited. When Stack Pointer decremented, RETI, interrupt will serviced. This feature prevents stack overflow allowing programmer structure more easily. However, when stack full, CALL subroutine instruction still executed which will result stack overflow. Precautions should taken avoid such cases which might cause unpredictable program branching. Arithmetic Logic Unit arithmetic-logic unit critical area microcontroller that carries arithmetic logic operations instruction set. Connected main microcontroller data bus, receives related instruction codes performs required arithmetic logical operations after which result will placed specified register. these calculation operations result carry, borrow other status changes, status register will correspondingly updated reflect these changes. supports following functions:
Arithmetic operations: ADD, ADDM, ADC, ADCM,
This vector reserved device reset program initialisation. After device reset initiated, program will jump this location begin execution.
Location 004H
This vector used external interrupt external interrupt receives active edge, program will jump this location begin execution external interrupt enabled stack full.
Location 008H
SUB, SUBM, SBC, SBCM,
Logic operations: AND, XOR, ANDM, ORM,
This vector used external interrupt external interrupt receives active edge, program will jump this location begin execution external interrupt enabled stack full.
Location 00CH
XORM, CPL, CPLA
Rotation RRA, RRCA, RRC, RLA, RLCA,
This internal vector used Timer/Event Counter Timer/Event Counter overflow occurs, program will jump this location begin execution timer/event counter interrupt enabled stack full.
Rev. 1.20
March 2009
HT56R64
Location 010H
Look-up Table location within Program Memory defined look-up table where programmers store fixed data. look-up table, table pointer must first setup placing lower order address look data retrieved table pointer register, TBLP. This register defines lower 8-bit address look-up table. After setting table pointer, table data retrieved from current Program Memory page last Program Memory page using instructions, respectively. When these instructions executed, lower order table byte from Program Memory will transferred user defined Data Memory register specified instruction. higher order table data byte from Program Memory will transferred TBLH special register. unused bits this transferred higher order byte will read following diagram illustrates addressing/data flow look-up table:
This internal vector used Timer/Event Counter Timer/Event Counter overflow occurs, program will jump this location begin execution timer/event counter interrupt enabled stack full.
Location 014H
This internal vector used SPI/I2C interrupt. When either bus, dependent upon which selected, requires data transfer, program will jump this location begin execution SPI/I2C interrupt enabled stack full.
Location 018H
This internal vector used Multi-function Interrupt. When Time Base overflows, Real Time Clock overflows, converter completes conversion process, active edge appears External Peripheral interrupt pin, program will jump this location begin execution relevant interrupt enabled stack full.
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ifie
I/I2C lti_
Program Memory Structure
Table Location Bits Instruction TABRDC TABRDL PC11 PC10
Table Location Note: PC11~PC8: Current program counter bits @7~@0: Table Pointer TBLP bits
Rev. 1.20
March 2009
HT56R64
Table Program Example following example shows table pointer table data defined retrieved from microcontroller. This example uses table data located last page which stored there using statement. value this statement which refers start address last page within Program Memory device. table pointer setup here have initial value This will ensure that first data read from data table will Program Memory address locations after start last page. Note that value table pointer referenced first address present page instruction being used. high byte table data which this case equal zero will transferred TBLH register automatically when instruction executed. Because TBLH register read-only register cannot restored, care should taken ensure protection both main routine Interrupt Service Routine table read instructions. using table read instructions, Interrupt Service Routines change value TBLH subsequently cause errors used again main routine. rule recommended that simultaneous table read instructions should avoided. However, situations where simultaneous cannot avoided, interrupts should disabled prior execution main routine table-read instructions. Note that table related instructions require instruction cycles complete their operation.
Tempreg1 tempreg2 tabrdl a,06h
temporary register temporary register
initialise table pointer note that this address referenced last page present page
tblp,a
tempreg1
transfers value table referenced table pointer tempregl data prog. memory address transferred tempreg1 TBLH
tblp tabrdl tempreg2
reduce value table pointer transfers value table referenced table pointer tempreg2 data prog.memory address transferred tempreg2 TBLH this example data transferred tempreg1 data register tempreg2
700h
sets initial address last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
Rev. 1.20
March 2009
HT56R64
Data Memory
Data Memory volatile area 8-bit wide internal memory location where temporary information stored. Divided into three sections, first these area where special function registers located. These registers have fixed locations necessary correct operation device. Many these registers read from written directly under program control, however, some remain protected from user manipulation. second area Data Memory reserved general purpose use. locations within this area read write accessible under program control. third area reserved
General Purpose Data Memory microcontroller programs require area read/write memory where temporary data stored retrieved later. this area memory that known General Purpose Data Memory. This area Data Memory fully accessible user program both read write operations. using instructions individual bits reset under program control giving user large range flexibility manipulation Data Memory. Special Purpose Data Memory
This area Data Memory where registers, necessary correct operation microcontroller, stored. Most registers both read write type some protected read only, details which located under relevant Special Function Register section. Note that locations that unused, read instruction these addresses will return value
Bank Data Memory Structure Note: Most Data Memory bits directly manipulated using with exception dedicated bits. Data Memory also accessed through memory pointer registers MP1.
Memory. This special area Data Memory mapped directly display data written into this memory area will directly affect displayed data. addresses Memory area overlap those General Purpose Data Memory area, switching between areas achieved setting Bank Pointer correct value. Structure Data Memory subdivided into banks, known Bank Bank which implemented 8-bit wide RAM. Data Memory located Bank subdivided into sections, Special Purpose Data Memory General Purpose Data Memory. start address Data Memory devices address last Data Memory address Bank display memory which occupy location.
Special Purpose Data Memory
Rev. 1.20
March 2009
HT56R64
Memory
data displayed also stored area fully accessible Data Memory. writing this area RAM, display output directly controlled application program. Memory exists Bank have addresses which into General Purpose Data Memory, necessary first ensure that Bank Pointer value before accessing Memory. Memory only accessed indirectly using Memory Pointer indirect addressing register IAR1. When Bank Pointer Bank access Data Memory, addresses with value less than read, Special Purpose Memory Bank will accessed. Also, Bank Pointer Bank addresses higher than last address Bank read, then value will returned. Indirect Addressing Registers IAR0, IAR1 Indirect Addressing Registers, IAR0 IAR1, although having their locations normal register space, actually physically exist normal registers. method indirect addressing data manipulation uses these Indirect Addressing Registers Memory Pointers, contrast direct memory addressing, where actual memory address specified. Actions IAR0 IAR1 registers will result actual read write operation these registers rather memory location specified their corresponding Memory Pointer, MP1. Acting pair, IAR0 together access data Bank while IAR1 register pair access data from Bank Bank Indirect Addressing Registers physically implemented, reading Indirect Addressing Registers indirectly will return result writing registers indirectly will result operation. Memory Pointers MP0, devices, Memory Pointers, known provided. These Memory Pointers physically implemented Data Memory manipulated same normal registers providing convenient with which address track data. When operation relevant Indirect Addressing Registers carried out, actual address that microcontroller directed address specified related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, used access data from Bank while IAR1 used access data from Bank Bank
Special Function Registers
ensure successful operation microcontroller, certain internal registers implemented Data Memory area. These registers ensure correct operation internal functions such timers, interrupts, etc., well external functions such data control converter operation. location these registers within Data Memory begins address 00H. unused Data Memory locations between these special function registers point where General Purpose Memory begins reserved future expansion purposes, attempting read data from these locations will return value 00H.
following example shows clear section four locations already defined locations adres1 adres4. data .section adres1 adres2 Adres3 adres4 block code .section start: loop: a,04h block,a a,offset adres1 mp0,a IAR0 block loop setup size block Accumulator loaded with first address setup memory pointer with first address clear data address defined increment memory pointer check last memory location been cleared
continue: important point note here that example shown above, reference made specific addresses.
Rev. 1.20
March 2009
HT56R64
Bank Pointer Data Memory divided into Banks, known Bank Bank Selecting required Data Memory area achieved using Bank Pointer. data Bank accessed, then register must loaded with value 00H, while data Bank accessed, then register must loaded with value 01H. Data Memory initialised Bank after reset, except time-out reset Power Down Mode, which case, Data Memory bank remains unaffected. should noted that Special Function Data Memory affected bank selection, which means that Special Function Registers accessed from within either Bank Bank Directly addressing Data Memory will always result Bank being accessed irrespective value Bank Pointer. Accumulator Accumulator central operation microcontroller closely related with operations carried ALU. Accumulator place where intermediate results from stored. Without Accumulator would necessary write result each calculation logical operation such addition, subtraction, shift, etc., Data Memory resulting higher programming timing overheads. Data transfer operations usually involve temporary storage function Accumulator; example, when transferring data between user defined register another, necessary this passing data through Accumulator direct transfer between registers permitted. Program Counter Register provide additional program control functions, byte Program Counter made accessible programmers locating within Special Purpose area Data Memory. manipulating this register, direct jumps other program locations easily implemented. Loading value directly into this register will cause jump specified Program Memory location, however, register only 8-bit wide, only jumps within current Program Memory page permitted. When such operations used, note that dummy cycle will inserted. Look-up Table Registers TBLP, TBLH These special function registers used control operation look-up table which stored Program Memory. TBLP table pointer indicates location where table data located. value must setup before table read commands executed. value changed, example using instructions, allowing easy table data pointing reading. TBLH location where high order byte table data stored after table read data instruction been executed. Note that lower order table data byte transferred user defined location. Status Register STATUS This 8-bit register contains zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). These arithmetic/logical operation system management flags used record status operation microcontroller. With exception flags, bits status register altered instructions like most
Bank Pointer
ilia
Status Register
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HT56R64
other registers. data written into status register will change flag. addition, operations related status register give different results different instruction operations. flag affected only system power-up, time-out executing instruction. flag affected only executing instruction during system power-up. flags generally reflect status latest operations.
operation results carry during
registers TMR0 TMR1L/TMR1H locations where timer values located. These register also preloaded with fixed data allow different time intervals setup. associated control registers, TMR0C TMR1C, contains setup information these timers, which determines what mode timer used well containing timer on/off control function. Input/Output Ports Control Registers Within area Special Function Registers, registers their associated control registers play prominent role. ports have designated register correspondingly labeled These labeled registers mapped specific addresses within Data Memory shown Data Memory table, which used transfer appropriate output input data that port. With each port there associated control register labeled PAC, PDC, also mapped specific addresses with Data Memory. control register specifies which pins that port inputs which outputs. setup input, corresponding control register must high, output must low. During program initialization, important first setup control registers specify which pins outputs which inputs before reading data from writing data ports. flexible feature these registers ability directly program single bits using instructions. ability change pins from output input vice versa manipulating specific bits control registers during normal program operation useful feature these devices. Pulse Width Modulator Registers device contains four Pulse Width Modulator function with their related independent control register, known PWM0L, PWM0H, PWM1L, PWM1H, PWM2L, PWM2H, PWM3L PWM3H. 12-bit contents each register pair, defines duty cycle value modulation cycle Pulse Width Modulator. Converter Registers ADRL, ADRH, ADCR, ACSR device contains 8-channel 12-bit converter. correct operation requires data registers control registers. data registers, high byte data register known ADRH, byte data register known ADRL, register locations where digital value placed after completion analog digital conversion cycle. Functions such enable/disable, channel selection clock frequency determined using control registers, ADCR ACSR.
dition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction.
operation results carry
nibbles addition, borrow from high nibble into nibble subtraction; otherwise cleared.
result arithmetic logical operation
zero; otherwise cleared.
operation results carry into high-
est-order carry highest-order bit, vice versa; otherwise cleared.
cleared system power-up executing
instruction. executing instruction.
cleared system power-up executing
instruction. time-out. addition, entering interrupt sequence executing subroutine call, status register will pushed onto stack automatically. contents status registers important subroutine corrupt status register, precautions must taken correctly save Interrupt Control Register INTC0, INTC1, MFIC, INTEDGE These 8-bit registers, control operation device interrupt functions. setting various bits within these registers using standard manipulation instructions, enable/disable function each interrupt independently controlled. master interrupt within this register, bit, acts like global enable/disable used interrupt enable bits off. This cleared when interrupt routine entered disable further interrupt executing instruction. INTEDGE register used select active edges external interrupt pins INT0 INT1. Timer/Event Counter Registers TMR0, TMR1L/ TMR1H, TMR0C, TMR1C device contains internal 8-bit Timer/Event Counter 16-bit Timer/Event Counter. Rev. 1.20
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Serial Interface Registers device contains serial interfaces, interface. SIMCON0, SIMCON1, SIMAR/ SIMCON2 control registers Serial Interface function while SIMDR data register Serial Interface Data. Port Wake-up Register PAWU pins Port have wake-up function enable going edge these pins wake-up device when power down mode. pins Port that used have wake-up function selected using this resister. Pull-High Resistors PAPU, PBPU, PDPU pins Ports setup inputs, connected internal pull-high resistor. pins which require pull-high resistor connected selected using these registers. Register CLKMOD device operates using dual clock system whose mode controlled using this register. register controls functions such clock source, idle mode enable division ratio slow clock. Registers LCDCTRL, LCDOUT1, LCDOUT2 device contains fully integrated Driver function which setup various configurations allowing control wide range external panels. Most these options controlled using LCDCTRL register. some segment driving pins also setup used CMOS oututs, registers, LCDOUT1 LCDOUT2, used select required function. Miscellaneous Register MISC miscellaneous register used control functions. four lower bits used Watchdog Timer control, while highest four bits used select open drain outputs pins PA0~PA3. non-latching, which means inputs must ready rising edge instruction where denotes port address. output operation, data latched remains unchanged until output latch rewritten. Pull-high Resistors Many product applications require pull-high resistors their switch inputs usually requiring external resistor. eliminate need these external resistors, pins, when configured input have capability being connected internal pull-high resistor. These pull-high resistors selected using registers PAPU, PBPU PDPU implemented using weak PMOS transistors. Port Wake-up HALT instruction forces microcontroller into Power Down condition which preserves power, feature that important battery other low-power applications. Various methods exist wake-up microcontroller, which change logic condition Port pins from high low. After HALT instruction forces microcontroller into entering Power Down condition, processor will remain low-power state until logic condition selected wake-up Port changes from high low. This function especially suitable applications that woken external switches. Each Port selected individually have this wake-up feature using PAWU register. Port Open Drain Function pins device have CMOS structures, however Port pins PA0~PA3 also setup open drain structures. This implemented using ODE0~ODE3 bits MISC register. Port Control Registers Each port control register known PAC, PBC, PDC, control input/output configuration. With this control register, each CMOS output input with without pull-high resistor structures reconfigured dynamically under software control. Each ports directly mapped associated port control register. function input, corresponding control register must written This will then allow logic state input directly read instructions. When corresponding control register written will setup CMOS output. currently setup output, instructions still used read output register. However, should noted that program will fact only read status output data latch actual logic status output pin.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility their ports. With input output designation every fully under user program control, pull-high selections ports wake-up selections certain pins, user provided with structure meet needs wide range application possibilities. device provides bidirectional input/output lines labeled with port names These ports mapped Data Memory with specific addresses shown Special Purpose Data Memory table. these ports used input output operations. input operation, these ports Rev. 1.20
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PA0~PA3 Open Drain Control MISC Pin-shared Functions flexibility microcontroller range greatly enhanced pins that have more than function. Limited numbers pins force serious design constraints designers supplying pins with multi-functions, many these difficulties overcome. some pins, chosen function multi-function pins configuration options while others function application program control.
External Interrupt Inputs
output enable output. port control register setup input, then will function normal logic input with usual pull-high selection, even registers have been selected.
Inputs
external interrupt pins INT0, INT1 pin-shared with pins PD4, PD5. applications requiring external interrupt input, pin-shared external interrupt used normal pin, however this, external interrupt enable bits INTC0 register must disabled.
External Timer Clock Input
device eight converter inputs. these analog inputs pin-shared with pins Port these pins used inputs normal pins then corresponding bits Converter Control Register, ADCR, must properly set. There configuration options associated with function. used pins, then full pull-high resistor register remain, however used inputs then pull-high resistor selections associated with these pins will automatically disconnected. Structures accompanying diagrams illustrate internal structures. exact logical construction differ from these drawings, they supplied guide only assist with functional understanding pins. Programming Considerations Within user program, first things consider port initialisation. After reset, data port control registers will high. This means that pins will default input state, level which depends other connected circuitry whether pull-high selections have been chosen. port control registers, PAC, PDC, then programmed setup some pins outputs, these output pins will have initial high output value unless associated port data registers, first programmed. Selecting which pins inputs which outputs achieved byte-wide loading correct values into appropriate port control register programming individual bits port control register using instructions. Note that when using these control instructions,
external timer pins TMR0, TMR1 pin-shared with PD6, PD7. configure operate timer input, corresponding control bits timer control register must correctly must also setup input. Note that original function will remain even setup used external timer input.
Output
device contains function whose single output pin-shared with PA3. output function this chosen configuration option remains fixed after device programmed. Note that corresponding port control register, PAC.3, must setup output enable output. port control register setup input, then will function normal logic input with usual pull-high selection, even configuration option been selected.
Outputs
device contains four outputs shared with PD0~PD3. output functions chosen registers. Note that corresponding port control register, PDC, must setup
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read-modify-write operation takes place. microcontroller must first read data entire port, modify required values then rewrite this data back output ports.
Port additional capability providing wake-up functions. When device Power Down Mode, various methods available wake device these high transition Port pins. Single multiple pins Port setup have this function.
Read/Write Timing
Input/Output Ports
Pull-High Resistor Register PAPU, PBPU, PDPU
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Input/Output Ports
Liquid Crystal Display (LCD) Driver
large volume applications, which incorporate their design, custom display rather than more expensive character based display reduces costs significantly. However, corresponding signals required, which vary both amplitude time, drive such custom display require many special considerations proper operation occur. Holtek Driver function, with internal signal generating circuitry various options, will automatically generate these time amplitude varying signals provide means direct driving easy interfacing range custom LCDs. Memory area Data Memory especially reserved data. This data area known Memory. data written here will automatically read internal driver circuits, which will turn automatically generate necessary driving signals. Therefore data written into Memory will immediately reflected into actual display connected microcontroller. start address Memory 40H; address Memory 60H. Data Memory addresses overlap those General Purpose Data Memory, Data Memory stored memory data bank, which different from that General Purpose Data Memory. Data Memory stored Bank Data Memory Bank chosen using Bank Pointer, which special function register Data Memory, with name, When lowest Bank Pointer binary value only General Purpose Data Memory will accessed, read write actions Memory will take place. access Memory therefore requires first that Bank selected setting lowest Bank Pointer binary value After this, Memory then accessed using indirect addressing through Memory Pointer MP1. With Bank selected, then using read write memory area, 40H~60H, will result operations Memory. Directly addressing Memory applicable will result data access Bank General Purpose Data Memory. diagrams below based format pixel drive capability panels. 4-COM format will automatically setup when duty control selected while 3-COM format will automatically setup duty control selected.
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Memory Registers single Control Register Data Memory, known LCDCTRL, used control various setup features Driver. Various bits this register control functions such duty type, bias type, bias resistor selection well overall enable disable. LCDEN LCDCTRL register will only effective when device Normal, Slow Idle Mode. device Sleep Mode then will always disabled. Bits RSEL0 RSEL1 select internal bias resistors supply panel with correct bias voltages. choice best match panel used application selected also minimise bias current. TYPE used select whether Type Type control signals used.
Control Register LCDCTRL
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Output Control Register LCDOUT1
Output Control Register LCDOUT2
registers, LCDOUT1 LCDOUT2 used determine output function pins SEG0~ SEG23 used segment drivers CMOS outputs. used CMOS outputs then Data Memory used determine logic level CMOS output pins. Note that only bits used determine output function SEG0~SEG7 SEG8~SEG15 pins, individual pins from these groups pins cannot chosen have either segment CMOS output function. output function pins SEG16~SEG23 chosen individually either segment driver CMOS input. Reset Function internal reset function that function inverted LCDEN LCDCTRL register Sleep function. reset signal active high. LCDENB signal inverse LCDEN LCDCTRL register. RELCD= (Sleep IDLEN=0 LCDENB. LEDSEL=0 LCDEN=1 must enabled activate LCDCTRL register function. Clock clock source internal clock signal, fSUB, divided using internal divider circuit. fSUB internal clock supplied either internal 32K_INT oscillator external oscillator, choice which determined configuration option. proper operation, this arrangement provided generate ideal clock source frequency 4kHz. fSUB Clock Source Internal 32K_INT Osc. External Osc. Clock Frequency 4KHz 4KHz
Driver Output number outputs supplied driver, well biasing duty selections, dependent upon control bits selected. accompanying table lists various selections. Bias Type, whether type selected using configuration option. Duty Driver Number Selections C-type bias used then internal charge pump will enabled. This charge pump voltage multiplier options selected using configuration option. Note that C-type bias available 52-pin package type. nature Liquid Crystal Displays require that only voltages applied their pixels application voltages pixels cause permanent damage. this reason relative contrast display controlled actual voltage applied each pixel, which equal value voltage minus voltage applied pin. This differential voltage must greater than saturation voltage pixel less than threshold voltage pixel off. requirement limit voltage zero control many pixels possible with minimum number connections, requires that both time amplitude signal generated applied application LCD. These time amplitude varying signals automatically generated driver circuits type Bias Bias Type Waveform Type
Clock Source
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microcontroller. What known duty determines number common lines used, which also known backplanes COMs. duty, which chosen control have value 1/2, which equates number respectively, therefore defines number time divisions within each signal frame. types signal generation also provided, known Type Type required type selected TYPE LCDCTRL register. Type offers lower frequency signals, however lower frequencies introduce flickering influence display clarity. accompanying timing diagrams depict signals generated microcontroller various values duty bias. Voltage Source Biasing time amplitude varying signals generated Driver function require generation several voltage levels their operation. number voltage levels used signal depends upon value BIAS LCDCTRL register. device have either type type biasing selected configuration option. Selecting type biasing will enable internal charge pump whose multiplying ration selected using additional configuration option. type biasing external voltage source must supplied VLCD1 generate internal biasing voltages. This could microcontroller power supply some other voltage source. type bias selection, three voltage levels VSS, utilised. voltage equal externally supplied voltage source applied VLCD1. generated internally microcontroller will have value equal VLCD1/2. type bias selection, four voltage levels VSS, utilised. voltage equal VLCD1, equal while equal addition selecting bias, several values bias resistor chosen using bits LCDCTRL register. Different values internal bias resistors selected using RSEL0 RESEL1 bits
LCDCTRL register. This along with voltage VLCD1 will determine bias current. connection VMAX depends upon voltage that applied VLCD1. voltage greater than voltage applied VLCD1 then VMAX should connected VDD, otherwise VMAX should connected VLCD1. Note that external capacitors resistors required connected type biasing used. Condition VLCD1 Otherwise VMAX connection Connect VMAX Connect VMAX VLCD1
Type Bias Current VMAX Connection type biasing external voltage source must also supplied VLCD1 generate internal biasing voltages. type biasing scheme uses internal charge pump circuit, which case bias selection generate voltages higher than what supplied VLCD1. This feature useful applications where microcontroller supply voltage less than supply voltage required LCD. internal charge pump voltage multiplying selections. lower multiplying selection external power supply should connected VLCD1 filter capacitor connected VLCD2. higher multiplying selection external power supply should connected VLCD2 filter capacitor connected VLCD1. additional charge pump capacitor must also connected between pins generate necessary voltage levels. type bias selection, three voltage levels VSS, utilised. voltage generated internally value VLCD1 depending upon which charge pump configuration option been selected. will have value equal type bias configuration used. type bias selection, four voltage levels VSS, utilised. voltage genV
Type Bias Voltage Levels
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Type Bias Voltage Levels
erated internally value depending upon which charge pump configuration option been selected. will have value equal will have value equal 1/3. connection VMAX depends upon bias voltage that applied VLCD, details shown table. Note that type biasing available 52-pin package device types. these package types, pins provided. recommended that 0.1mF capacitor connected between ground 52-pin package types. extremely important ensure that these charge pump generated internal voltages exceed maximum voltage 5.5V. Note that C-type bias type available 52-pin package type. Biasing Type Bias VMAX Connection
Bias
VDD>VLCD1 Otherwise
Connect VMAX Connect VMAX VLCD1
Type Biasing VMAX Connection Programming Considerations Certain precautions must taken when programming LCD. these ensure that memory properly initialised after microcontroller powered Like General Purpose Data Memory, contents memory unknown condition after power-on. contents memory will mapped into actual LCD, important initialise this memory area into known condition soon after applying power obtain proper display pattern. Consideration must also given capacitive load actual used application. load presented microcontroller pixels generally modeled mainly capacitive nature, important that this excessive, point that particularly true case lines which connected many pixels. accompanying diagram depicts equivalent circuit LCD.
Connect VMAX Otherwise Connect VMAX
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additional consideration that must taken into account what happens when microcontroller enters HALT condition. control LCDCTRL register permits powered reduce power consumption. selected, driving signals will cease, producing blank display pattern reducing power consumption associated with LCD. After Power-on, note that LCDEN LCDCTRL register will cleared zero, function will disabled. following timing diagrams depict signals generated microcontroller various values duty bias.
Panel Equivalent Circuit With such frequency chosen, microcontroller internal driver circuits will ensure that appropriate driving signals generated obtain suitable frame frequency.
Driver Output Type Duty, Bias Note Bias, VA=VLCD1, both type.
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Driver Output Type Duty, Bias Note: Bias, VA=VLCD1, both type.
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Driver Output Type Duty, Bias Note: type bias, VA=VLCD1, type bias, VB=VLCD1
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Driver Output Type Duty, Bias Note: type bias, VA=VLCD1, type bias, VB=VLCD1
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Driver Output Type Duty, Bias Note: bias, VA=VLCD, both type.
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Timer/Event Counters
provision timers form important part microcontroller, giving designer means carrying time related functions. devices contain 8-bit 16-bit count-up timer. each timer three different operating modes, they configured operate general timer, external event counter pulse width measurement device. provision prescaler clock circuitry 8-bit Timer/Event Counter also gives added range this timer. There types registers related Timer/Event Counters. first registers that contain actual value Timer/Event Counter into which initial value preloaded. Reading from these registers retrieves contents Timer/Event Counter. second type associated register Timer Control Register which defines timer options determines Timer/Event Counter used. Timer/Event Counters have their clock configured come from internal clock source. addition, their clock source also configured come from external timer pin. Configuring Timer/Event Counter Input Clock Source internal clock originate from various sources. system clock source used when Timer/Event Counter timer mode pulse width measurement mode. Timer/Event Counter this internal clock source fSYS which also divided prescaler, division ratio which conditioned Timer Control Register, TMR0C, bits T0PSC0~ T0PSC2. Timer/Event Counter this internal clock source chosen from combination internal clocks using configuration option TMR1C register. external clock source used when timer event counting mode, clock source being provided external timer TMR0 TMR1, depending upon which timer used. Depending upon condition bit, each high low, high transition external timer will increment counter one. Timer Registers TMR0, TMR1L, TMR1H timer registers special function registers located Special Purpose Data Memory place where actual timer value stored. 8-bit Timer/Event Counter this register known TMR0. 16-bit Timer/Event Counter timer registers known TMR1L TMR1H. value timer registers increases each time internal clock pulse received external transition occurs external timer pin. timer will count from initial value loaded preload register full count 8-bit timer FFFFH 16-bit timer which point timer overflows internal interrupt signal generated. timer value will then reset with initial preload register value continue counting. achieve maximum full range count 8-bit timer FFFFH 16-bit timer, preload registers must first cleared zeros. should noted that after power-on, preload register will unknown condition. Note that Timer/Event Counter switched data written preload registers, this data will immediately written into actual timer registers. However, Timer/Event Counter enabled counting, data written into preload data registers during this period will remain preload registers will only written into timer registers next time overflow occurs. 16-bit Timer/Event Counter which both byte high byte timer registers, accessing these registers carried specific way. must noted when using instructions preload data into byte timer register, namely TMR1L, data will only placed byte buffer directly into byte timer register. actual transfer data into
Timer Mode Timing Chart
Event Counter Mode Timing Chart
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byte timer register only carried when write associated high byte timer register, namely TMR1H, executed. other hand, using instructions preload data into high byte timer register will result data being directly written high byte timer register. same time data byte buffer will transferred into associated byte timer register. this reason, byte timer register should written first when preloading data into 16-bit timer registers. must also noted that read contents byte timer register, read high byte timer register must executed first latch contents byte timer register into associated byte buffer. After this been done, byte timer register read normal way. Note that reading byte timer register will result reading previously latched contents byte buffer actual contents byte timer register. Timer Control Registers TMR0C, TMR1C flexible features Holtek microcontroller Timer/Event Counters enable them operate three different modes, options which determined contents their respective control register. Timer Control Register together with corresponding timer registers that control full operation Timer/Event Counters. Before timers used, essential that appropriate Timer Control Register fully programmed with right data ensure correct operation, process that normally carried during program initialisation. choose which three modes timer operate either timer mode, event counting mode pulse width measurement mode, bits Timer Control Register, which known pair T0M1/T0M0 T1M1/T1M0 respectively, depending upon which timer used, must required logic levels. timer-on bit, which Timer Control Register known T0ON T1ON, depending upon which timer used, provides basic on/off control respective timer. Setting high allows counter run, clearing stops counter. timers that have prescalers, bits Timer Control Register determine division ratio input clock prescaler. prescaler settings have effect external clock source used. timer event count pulse width measurement mode, active transition edge level type selected logic
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Timer/Event Counter Structure
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Timer/Event Counter Structure
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Timer/Event Counter Control Register TMR0C
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Timer/Event Counter Control Register TMR1C
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level Timer Control Register which known depending upon which timer used. additional TMR1C register used determine clock source Timer/Event Counter Configuring Timer Mode this mode, Timer/Event Counter utilised measure fixed time intervals, providing internal interrupt signal each time Timer/Event Counter overflows. operate this mode, Operating Mode Select pair, T0M1/T0M0 T1M1/T1M0, Timer Control Register must correct value shown. Control Register Operating Mode Select Bits Timer Mode Bit7 Bit6 Control Register Operating Mode Select Bits Event Counter Mode Bit7 Bit6
this mode internal clock, fSYS used internal clock 8-bit Timer/Event Counter fSUB fSYS/4 used internal clock 16-bit Timer/Event Counter However, clock source, fSYS, 8-bit timer further divided prescaler, value which determined Prescaler Rate Select bits T0PSC2~T0PSC0, which bits Timer Control Register. After other bits Timer Control Register have been setup, enable T0ON T1ON, which Timer Control Register, high enable Timer/Event Counter run. Each time internal clock cycle occurs, Timer/Event Counter increments one. When full overflows, interrupt signal generated Timer/Event Counter will reload value already loaded into preload register continue counting. interrupt disabled ensuring that Timer/Event Counter Interrupt Enable Interrupt Control Register, INTC0, reset zero. Configuring Event Counter Mode this mode, number externally changing logic events, occurring external timer pin, recorded Timer/Event Counter. operate this mode, Operating Mode Select pair, T0M1/T0M0 T1M1/T1M0, Timer Control Register must correct value shown.
this mode, external timer pin, TMR0 TMR1, used Timer/Event Counter clock source, however divided internal prescaler. After other bits Timer Control Register have been setup, enable T0ON T1ON, which Timer Control Register, high enable Timer/Event Counter run. Active Edge Select T1E, which Timer Control Register, low, Timer/Event Counter will increment each time external timer receives high transition. Active Edge Select high, counter will increment each time external timer receives high transition. When full overflows, interrupt signal generated Timer/Event Counter will reload value already loaded into preload register continue counting. interrupt disabled ensuring that Timer/Event Counter Interrupt Enable Interrupt Control Register, INTC0, reset zero. external timer shared with pin, ensure that configured operate event counter input pin, things have happen. first ensure that Operating Mode Select bits Timer Control Register place Timer/Event Counter Event Counting Mode, second ensure that port control register configures input. should noted that event counting mode, even microcontroller Power Down Mode, Timer/Event Counter will continue record externally changing logic events timer input pin. result when timer overflows will generate timer interrupt corresponding wake-up source.
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Pulse Width Measure Mode Timing Chart
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Configuring Pulse Width Measurement Mode this mode, Timer/Event Counter utilised measure width external pulses applied external timer pin. operate this mode, Operating Mode Select pair, T0M1/T0M0 T1M1/T1M0, Timer Control Register must correct value shown. Control Register Operating Mode Select Bits Pulse Width Measurement Mode Bit7 Bit6 length pulse received external timer pin. enable been reset, further transitions external timer will ignored. until enable again high program timer begin further pulse width measurements. this way, single shot pulse measurements easily Made. should noted that this mode Timer/Event Counter controlled logical transitions external timer logic level. When Timer/Event Counter full overflows, interrupt signal generated Timer/Event Counter will reload value already loaded into preload register continue counting. interrupt disabled ensuring that Timer/Event Counter Interrupt Enable Interrupt Control Register, INTC, reset zero. external timer shared with pin, ensure that configured operate pulse width measurement pin, things have happen. first ensure that Operating Mode Select bits Timer Control Register place Timer/Event Counter Pulse Width Measurement Mode, second ensure that port control register configures input. Programmable Frequency Divider Programmable Frequency Divider provides means producing variable frequency output suitable applications requiring precise frequency generator. output pin-shared with PA3. function selected configuration option, however, selected, operate normal pin. clock source circuit originate from either timer timer overflow signal selected configuration option. output frequency controlled loading required values into timer registers prescaler registers give required division ratio. timer will begin count-up from this preload register value until full, which point overflow signal generated, causing output change state. timer will then automatically reloaded with preload register value continue counting-up.
this mode internal clock, fSYS used internal clock 8-bit Timer/Event Counter fSUB fSYS/4 used internal clock 16-bit Timer/Event Counter However, clock source, fSYS, 8-bit timer further divided prescaler, value which determined Prescaler Rate Select bits T0PSC2~T0PSC0, which bits Timer Control Register. After other bits Timer Control Register have been setup, enable T0ON T1ON, which Timer Control Register, high enable Timer/Event Counter, however will actually start counting until active edge received external timer pin. Active Edge Select T1E, which Timer Control Register, low, once high transition been received external timer pin, TMR0 TMR1, Timer/Event Counter will start counting until external timer returns original high level. this point enable will automatically reset zero Timer/Event Counter will stop counting. Active Edge Select high, Timer/Event Counter will begin counting once high transition been received external timer stop counting when external timer returns original level. before, enable will automatically reset zero Timer/Event Counter will stop counting. important note that Pulse Width Measurement Mode, enable automatically reset zero when external control signal external timer returns original level, whereas other modes enable only reset zero under program control. residual value Timer/Event Counter, which read program, therefore represents
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output function, essential that corresponding Port control register setup output. setup input output will function, however, still used normal input pin. output will only activated This output data used on/off control output. Note that output will output data cleared Using this method frequency generation, crystal oscillator used system clock, very precise values frequency generated. Prescaler Bits T0PSC0~T0PSC2 TMR0C register used define pre-scaling stages internal clock sources Timer/Event Counter Timer/Event Counter overflow signal used generate signals Timer Interrupt. Interfacing Timer/Event Counter, when configured event counter pulse width measurement mode, require external correct operation. this shared must configured correctly ensure setup Timer/Event Counter input normal pin. This implemented ensuring that mode select bits Timer/Event Counter control register, select either event counter pulse width measurement mode. Additionally Port Control Register must high ensure that setup input. pull-high resistor this will remain valid even used Timer/Event Counter input. Timer/Event Counter Pins Internal Filter external Timer/Event Counter pins connected internal filter reduce possibility unwanted event counting events inaccurate pulse width measurements adverse noise spikes external Timer/Event Counter input signal. this internal filter circuit will consume limited amount power, configuration option provided switch filter function, option which beneficial power sensitive applications, which integrity input signal high. Care must taken when using filter on/off configuration option will applied only both external Timer/Event Counter pins also external interrupt input pins. Individual Timer/Event Counter external interrupt pins cannot selected have filter on/off function. Programming Considerations When configured timer mode, internal system clock used timer clock source therefore synchronised with overall operation microcontroller. this mode when appropriate timer Rev. 1.20 register full, microcontroller will generate internal interrupt signal directing program flow respective internal interrupt vector. pulse width measurement mode, internal system clock also used timer clock source timer will only when correct logic condition appears external timer input pin. this external event synch microcontroller will only this external event when next timer clock pulse arrives. result, there small differences measured values requiring programmers take this into account during programming. same applies timer configured event counting mode, which again external event synchronised with internal system timer clock. When Timer/Event Counter read, data written preload register, clock inhibited avoid errors, however this result counting error, this should taken into account programmer. Care must taken ensure that timers properly initialised before using them first time. associated timer enable bits interrupt control register must properly otherwise internal interrupt associated with timer will remain inactive. edge select, timer mode clock source control bits timer control register must also correctly ensure timer properly configured required application. also important ensure that initial value first loaded into timer registers before timer switched this because after power-on initial values timer registers unknown. After timer been initialised timer turned controlling enable timer control register. Note that setting timer enable high turn timer should only executed after timer mode bits have been properly setup. Setting timer enable high together with mode modification, lead improper timer operation executed single timer control register byte write instruction. When Timer/Event counter overflows, corresponding interrupt request flag interrupt control register will set. timer interrupt enabled this will turn generate interrupt signal. However irrespective whether interrupts enabled not, Timer/Event counter overflow will also generate wake-up signal device Power-down condition. This situation occur Timer/Event Counter Event Counting Mode external signal continues change state. such case, Timer/Event Counter will continue count these external events overflow occurs device will woken from Power-down condition. prevent such wake-up from occurring, timer interrupt request flag should first high before issuing HALT instruction enter Power Down Mode.
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Timer Program Example This program example shows Timer/Event Counter registers setup, along with interrupts enabled managed. Note Timer/Event Counter turned setting Timer Control Register. Timer/Event Counter turned similar clearing same bit. This example program sets Timer/Event Counter timer mode, which uses internal system clock clock source. external interrupt vector reti Timer/Event Counter interrupt vector tmrint jump here when Timer/Event Counter overflows main program ;internal Timer/Event Counter interrupt routine tmrint: Timer/Event Counter main program placed here reti begin: ;setup Timer registers a,09bh setup Timer preload value tmr0,a; a,081h setup Timer control register tmr0c,a timer mode prescaler setup interrupt register a,009h enable master interrupt timer interrupt int0c,a tmr0c.4 start Timer/Event Counter note mode bits must previously setup
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Pulse Width Modulator
device contains four Pulse Width Modulation, PWM, outputs. Useful such applications such motor speed control, function provides output with fixed frequency with duty cycle that varied setting particular values into corresponding register. Channel Mode Output Register Names PWM0L PWM0H PWM1L PWM1H PWM2L PWM2H PWM3L PWM3H modulation cycle modulation cycle denoted table. Each these sixteen sub-cycles contains clock cycles. this mode, modulation frequency increase sixteen achieved. 12-bit register value, which represents overall duty cycle waveform, divided into groups. first group which consists bit4~bit11 denoted here value. second group which consists bit0~bit3 known value. mode, duty cycle value each modulation sub-cycles shown following table. Parameter Modulation cycle (i=0~15) (0~15) i<AC (Duty Cycle) DC+1
Mode Modulation Cycle Values Overview Four register pairs, located Data Memory assigned Pulse Width Modulator known registers. each register pair that 12-bit value, which represents overall duty cycle modulation cycle output waveform, should placed. registers also contain enable/disable control outputs. increase modulation frequency, each modulation cycle modulated into sixteen individual modulation sub-sections, known mode. Note that only necessary write required modulation value into corresponding register subdivision waveform into sub-modulation cycles implemented automatically within microcontroller hardware. clock source system clock fSYS. This method dividing original modulation cycle into further sub-cycles enables generation higher frequencies, which allow wider range applications served. long periods generated pulses less than time constants load, output will suitable such long time constant loads will average pulses output. difference between what known cycle frequency modulation frequency should understood. clock system clock, fSYS, value 12-bits wide, overall cycle frequency fSYS/4096. However, when mode operation, modulation frequency will fSYS/256. Mode Modulation Each full cycle, 12-bits wide, 4096 clock periods. However, mode, each cycle subdivided into sixteen individual sub-cycles known accompanying diagram illustrates waveforms associated with mode operation. important note single cycle subdivided into individual modulation cycles, numbered 0~15 value related value. Output Control Modulation Frequency fSYS/256 Cycle Frequency fSYS/4096 Cycle Duty (PWM register value)/4096
four PWM0~PWM3 outputs shared with pins PD0~PD3. operate output pin, relevant register must high. zero must also written corresponding port control register, ensure that PWM0 output setup output. After these initial steps have been carried out, course after required 12-bit value been written into register pair register, writing corresponding data register will enable data appear pin. Writing will disable output function force output low. this way, Port data output register bits, also used on/off control function. Note that enable register high enable function, been written corresponding control register configure input, then still function normal input line, with pull-high resistor selections.
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Mode
Register Pairs
Programming Example following sample program shows output setup controlled. a,64h pwm0h,a pwm0l pdc.0 pwm0en pd.0 pd.0 setup PWM0 value 1600 decimal which 640H setup PWM0H register value setup PWM0L register value setup output PWM0 enable Enable PWM0 output
PWM0 output disabled will remain
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Analog Digital Converter
need interface real world analog signals common requirement many electronic systems. However, properly process these signals microcontroller, they must first converted into digital signals converters. integrating conversion electronic circuitry into microcontroller, need external components reduced significantly with corresponding follow-on benefits lower costs reduced component space requirements. Overview device contains 8-channel analog digital converter which directly interface external analog signals, such that from sensors other control signals convert these signals directly into either 12-bit digital value. Input Channels Conversion Bits Input Pins PB0~PB7
Register ADRL ADRH
Data Registers Converter Control Registers ADCR, ACSR control function operation converter, control registers known ADCR ACSR provided. These 8-bit registers define functions such selection which analog channel connected internal converter, which pins used analog inputs which used normal I/Os, clock source well controlling start function monitoring converter conversion status. ACS2~ACS0 bits ADCR register define channel number. device contains only actual analog digital converter circuit, each individual analog inputs must routed converter. function ACS2~ACS0 bits ADCR register determine which analog channel actually connected internal converter. ADCR control register also contains PCR2~PCR0 bits which determine which pins Port used analog inputs converter which pins used normal pins. 3-bit address PCR2~PCR0 value then eight pins, namely AN0~AN7 will analog inputs. Note that PCR2~PCR0 bits zero, then Port pins will setup normal I/Os internal converter circuitry will powered reduce power consumption.
accompanying block diagram shows overall internal structure converter, together with associated registers. Converter Data Registers ADRL, ADRH device, which internal 12-bit converter, requires data registers, high byte register, known ADRH, byte register, known ADRL. After conversion process takes place, these registers directly read microcontroller obtain digitised conversion value. Only high byte register, ADRH, utilises full 8-bit contents. byte register utilises only 8-bit contents contains only lowest bits 12-bit converted value. following table, D0~D11 conversion data result bits.
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Converter Control Register ADCR
START ADCR register used start reset converter. When microcontroller sets this from high then again, analog digital conversion cycle will initiated. When START brought from high again, EOCB ADCR register will analog digital converter will reset. START that used control overall on/off operation internal analog digital converter. EOCB ADCR register used indicate when analog digital conversion process complete. This will automatically microcontroller after conversion cycle ended. addition, corresponding interrupt request flag will interrupt control register, interrupts enabled, appropriate internal interrupt signal will generated. This internal interrupt signal will direct program flow associated internal interrupt address processing. internal interrupt disabled, microcontroller used poll EOCB ADCR register check whether been cleared alternative method detecting conversion cycle. clock source converter, which originates from system clock fSYS, first divided division ratio, value which determined ADCS2, ADCS1 ADCS0 bits ACSR register.
Controlling on/off function converter circuitry implemented using ADONB ACSR register value bits ADCR register. Both ADONB must cleared value bits must have non-zero value converter enabled. ADONB
Although clock source determined system clock fSYS, bits ADCS2, ADCS1 ADCS0, there some limitations maximum clock source speed that selected. minimum value permissible clock period, tAD, 0.5ms, care must taken system clock speeds excess 4MHz. system clock speeds excess 4MHz, ADCS2, ADCS1 ADCS0 bits should Doing will give clock periods that less than minimum clock period which result inaccurate conversion values. Refer following table examples, where values marked with asterisk show where, depending upon device, special care must taken, values less than specified minimum Clock Period.
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Clock Period (tAD) fSYS ADCS2, ADCS1, ADCS0=000 (fSYS/2) 500ns* 250ns* 167ns* ADCS2, ADCS1, ADCS0=001 (fSYS/8) 667ns* Clock Period Examples
ADCS2, ADCS1, ADCS0=010 (fSYS/32) 32ms 16ms 2.67ms
ADCS2, ADCS1, ADCS0=011 Undefined Undefined Undefined Undefined Undefined
1MHz 2MHz 4MHz 8MHz 12MHz
Converter Control Register ACSR Input Pins analog input pins pin-shared with pins Port Bits PCR2~PCR0 ADCR register, determine whether input pins setup normal Port input/output pins whether they setup analog inputs. this way, pins changed under program control change their function from normal operation analog inputs vice versa. Pull-high resistors, which setup through register programming, apply input pins only when they used normal pins, setup inputs pull-high resistors will automatically disconnected. Note that necessary first setup input port control register enable input when PCR2~PCR0 bits enable input, status port control register will overridden. converter power supply pins AVDD AVSS VREF reference pin. analog input values must allowed exceed value VREF. Initialising Converter internal converter must initialised special way. Each time Port channel selection bits modified program, converter must re-initialised. converter initialised after channel selection bits changed, EOCB flag have undefined value, which produce false conversion signal. initialise converter after channel selection bits have changed, then, within time frame instruction cycles, START ADCR register must first high then immediately cleared zero. This will ensure that EOCB flag correctly high condition. Summary Conversion Steps following summarises individual steps that should executed order implement conversion process.
Step
Select required conversion clock correctly programming bits ADCS2, ADCS1 ADCS0 ACSR register.
Step
Enable clearing ADONB ACSR register zero.
Step
Select which channel connected internal converter correctly programming ACS2~ACS0 bits which also contained ADCR register.
Step
Select which pins Port used inputs configure them input pins correctly programming PCR2~PCR0 bits ADCR register. Note that this step combined with Step into single ADCR register programming operation. March 2009
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Conversion Timing
Step
interrupts used, interrupt control registers must correctly configured ensure converter interrupt function active. master interrupt control bit, EMI, INTC0 interrupt control register must multi-function interrupt enable bit, EMFI, INTC1 register converter interrupt bit, EADI, INTC1 register must also
Step
during which time program continue with other functions. time taken conversion 16tAD where equal clock period. Programming Considerations When programming, special attention must given channel selection bits ADCR register. these bits cleared zero external pins will selected input pins allowing pins used normal pins. When this happens power supplied internal circuitry will reduced resulting reduction supply current. This ability reduce power turning internal function clearing channel selection bits important consideration battery powered applications. ADONB ACSR register also used power down function. Another important programming consideration that when channel selection bits change value, converter must re-initialised. This achieved pulsing START ADCR register immediately after channel selection bits have changed state. exception this where channel selection bits cleared, which case converter required re-initialised. Programming Example following programming examples illustrate setup implement conversion. first example, method polling EOCB ADCR register used detect when conversion cycle complete, whereas second example, interrupt used determine when conversion complete.
analog digital conversion process initialised setting START ADCR register from then again. Note that this should have been originally
Step
check when analog digital conversion process complete, EOCB ADCR register polled. conversion process complete when this goes low. When this occurs data registers ADRL ADRH read obtain conversion value. alternative method interrupts enabled stack full, program wait interrupt occur. Note: When checking conversion process, method polling EOCB ADCR register used, interrupt enable step above omitted.
accompanying diagram shows graphically various stages involved analog digital conversion process associated timing. setting operation converter function fully under control application program there configuration options associated with converter. After conversion process been initiated application program, microcontroller internal hardware will begin carry conversion, Rev. 1.20
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Example: using EOCB polling method detect conversion EADI disable interrupt a,00000001B ACSR,a select fSYS/8 clock turn ADONB a,00100000B setup ADCR register configure Port PB0~PB3 inputs ADCR,a select connected converter Port channel bits have changed following START signal (0-1-0) must issued instruction cycles Start_conversion: START START reset START start Polling_EOC: EOCB poll ADCR register EOCB detect conversion polling_EOC continue polling a,ADRL read byte conversion result value adrl_buffer,a save result user defined register a,ADRH read high byte conversion result value adrh_buffer,a save result user defined register start_conversion start next conversion Example: using interrupt method detect conversion EADI disable interrupt a,00000001B ACSR,a select fSYS/8 clock turn ADONB a,00100000B ADCR,a setup ADCR register configure Port PB0~PB3 inputs select connected Port channel bits have changed following START signal(0-1-0) must issued Start_conversion: START START START EADI EMFI interrupt service routine ADC_: acc_stack,a a,STATUS status_stack,a a,ADRL adrl_buffer,a a,ADRH adrh_buffer,a EXIT_ISR: a,status_stack STATUS,a a,acc_stack reti Rev. 1.20
reset start clear interrupt request flag enable interrupt enable multi-function interrupt enable global interrupt
save user defined memory save STATUS user defined memory read save read save byte conversion result value result user defined register high byte conversion result value result user defined register
restore STATUS from user defined memory restore from user defined memory clear interrupt flag
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Transfer Function device contain 12-bit converter, full-scale converted digitised value equal FFFH. Since full-scale analog input value equal voltage, this gives single analog input value VDD/4096. diagram show ideal transfer function between analog input value digitised output value converter. Note that reduce quantisation error, offset added Converter input. Except digitised zero value, subsequent digitised values will change point below where they would change without offset, last full scale digitised value will change point below level.
Interface Operation
Serial Interface
device contains both serial interface functions, which allows methods easy communication with external peripheral hardware. function share same external pins internal registers their function must first chosen selecting correct configuration option. Interface interface often used communicate with external peripheral devices such sensors, Flash EEPROM memory devices etc. Originally developed Motorola, four line interface synchronous serial data interface that relatively simple communication protocol simplifying programming requirements when communicating with external hardware devices.
interface full duplex synchronous serial data link. Communication between devices connected interface carried slave/master mode with data transfer initiations being implemented master. Multiple slave devices connected serial with each device controlled using slave select line. four line interface with names SDI, SDO, SCS. Pins Serial Data Input Serial Data Output lines, Serial Clock line Slave Select line. interface pins pin-shared with segment pins with function pins, interface must first enabled selecting correct configuration option. After configuration option been selected then also selected using SIMEN SIMCON0 register. function this device offers following features:
Full duplex synchronous data transfer Both Master Slave modes first first data transmission modes Transmission complete flag Supports UART interface bridge IDLE mode supported
Several other configuration options also exist setup various interface options follows:
enabled Rising falling active clock edge WCOL enabled disabled CSEN enabled disabled
Ideal Transfer Function
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status interface pins determined number factors, whether device master slave mode upon condition certain control bits such CSEN SIMEN. Master (SIMEN=1) Master/Salve (SIMEN=0) CSEN=1 L(CPOL=1) H(CPOL=0) CSEN=0 L(CPOL=1) H(CPOL=0) CSEN=0 Slave (=1) line=0 (CSEN=1) line=1 (CSEN=1)
floating, output high, output low, Input, level, input floating pull-high) Interface Status
Registers
SIMDR register used store data being transmitted received. There control registers associated with interface, SIMCON0 SIMCON2 data register known SIMDR. SIMCON1 register used function. Register SIMCON0 used control enable/disable function, power down control data transmission clock frequency. Register SIMCON2 used other control functions such LSB/MSB selection, write collision flag etc. following gives further explanation each bit:
lines will floating condition operating current will reduced <0.1mA When high interface enabled. Note that when SIMEN changes from high contents control registers will unknown condition should therefore initialised application program.
SIMEN SIMEN overall on/off control interface. When SIMEN cleared zero disable interface, SDI, SCO,
SIMIDLE SIMIDLE used select interface continues running when device IDLE mode. Setting high allows clock keep running enables interface maintain operation when device Idle mode. Clearing zero disables operations when Idle mode.
Block Diagram
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Control Register SIMCON0
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Control Register SIMCON2
I/I2C
Module Structure
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SIM0~SIM2 These three bits control Master/Slave selection also setup interface clock speed when Master Mode. clock function system clock whether type Crystal type also chosen sourced from Timer/Event Counter divided two. Slave Mode selected then clock will supplied external Master device. following gives further explanation each bit: Transmit/Receive Complete flag cleared application program used generate interrupt. When high data been transmitted received. data being transmitted been received. WCOL WCOL used detect data collision occurred. this high means that data been attempted written SMDR register during data transfer operation. This writing operation will ignored data being transferred. cleared application program. Note that using SCEN disabled enabled configuration option.
CSEN CSEN used on/off control pin. this then will disabled placed into floating condition. high will enabled used select pin. used select data transferred, either first. Setting high will select first first. Note that SIMCON2 register same SIMAR register used interface.
Communication
After interface enabled setting SIMEN high, then Master Mode, when data written SIMDR register, transmission/reception will begin simultaneously. When data transfer complete, flag will automatically. Slave Mode, when clock signal from master been received, data SIMDR register will transmitted data will shifted into SIMDR register. master should output signal before clock signal provided slave data transfers should enabled/disabled before/after signal received.
Interface Timing
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Transfer Control Flowchart
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Interface bidirectional 2-line communication interface originally developed Philips. possibility transmitting receiving data only lines offers many application possibilities microcontroller based applications.
Interface Operation Registers
interface pins pin-shared with segment pins with function pins, interface must first enabled selecting correct configuration option. There lines associated with bus, first known Serial Data line, second known line Serial Clock line. many devices connected together same bus, their outputs both open drain types. this reason necessary that external pull-high resistors connected these outputs. Note that chip select line exists, each device identified unique address which will transmitted received bus. When devices communicate with each other bidirectional bus, known master device slave device. Both master slave transmit receive data, however, master device that overall control bus. this device, which only operates slave mode, there methods transferring data bus, slave transmit mode slave receive mode.
There three control registers associated with bus, SIMCON0, SIMCON1 SIMAR data register, SIMDR. SIMDR register used store data being transmitted received bus. Before microcontroller writes data bus, actual data transmitted must placed SIMDR register. After data received from bus, microcontroller read from SIMDR register. transmission data reception data from must made SIMDR register. SIMAR register location where slave address microcontroller stored. Bits SIMAR register define microcontroller slave address. defined. When master device, which connected bus, sends address, which matches slave address SIMAR register, microcontroller slave device will selected. Note that SIMAR register same register SIMCON2 which used interface. SIMCON0 register used overall on/off control describe interface remains active Idle Mode.
Slave Address Register SIMAR
Control Register SIMCON0
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Control Register SIMCON1
following gives further explanation each bit:
SIMEN SIMEN determines enabled disabled. data transferred received then this must high. SIMIDLE SIMIDLE used select interface continues running when device IDLE mode. Setting high allows interface maintain operation when device Idle mode. Clearing zero disables operations when Idle mode. SIMCON1 register used control monitor status bus. following gives further explanation each bit: flag data transfer flag. This flag will zero when data being transferred. Upon completion 8-bit data transfer flag will high interrupt will generated. HASS HASS flag address match flag. This flag used determine slave device address same master transmit address. addresses match then this will high, there match then flag will low.
flag transmit/receive mode bit. This flag should high transmit mode receive mode. TXAK TXAK flag transmit acknowledge flag. After receipt 8-bits data, this will transmitted clock. continue receiving more data, this reset zero before further data received. Slave Read/Write bit. This determines whether master device wishes transmit receive data from bus. When transmitted address slave address match, that when HAAS high, device will check determine whether should transmit mode receive mode. high, master requesting read data from bus, device should transmit mode. When zero, master will write data bus, therefore device should receive mode read this data. RXAK RXAK flag receive acknowledge flag. When RXAK been reset zero means that correct acknowledge signal been received clock, after bits data have been transmitted. When transmit mode, transmitter checks RXAK determine receiver wishes receive next byte. transmitter will therefore continue sending data until RXAK When this occurs, transmitter will release line allow master send STOP signal release bus.
flag busy flag. This flag will high when busy which will occur when START signal detected. flag will reset zero when free which will occur when STOP signal detected.
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Communication Communication requires four separate steps, START signal, slave device address transmission, data transmission finally STOP signal. When START signal placed bus, devices will receive this signal notified imminent arrival data bus. first seven bits data will slave address with first being MSB. address microcontroller matches that transmitted address, HAAS SIMCON1 register will interrupt will generated. After entering interrupt service routine, microcontroller slave device must first check condition HAAS determine whether interrupt source originates from address match from completion 8-bit data transfer. During data transfer, note that after 7-bit slave address been transmitted, following bit, which bit, read/write whose value will placed bit. This will checked microcontroller determine whether into transmit receive mode. Before transfer data from bus, microcontroller must initialise bus, following steps achieve this: Step Write slave address microcontroller address register SIMAR. Step SIMEN SIMCON0 register enable bus. Step interrupt control register enable interrupt.
Start Signal
START signal only generated master device connected microcontroller, which only slave device. This START signal will detected devices connected bus. When detected, this indicates that busy therefore will set. START condition occurs when high transition line takes place when line remains high.
Slave Address
transmission START signal master will detected devices bus. determine which slave device master wishes communicate with, address slave device will sent immediately following START signal. slave devices, after receiving this 7-bit address data, will compare with their 7-bit slave address. address sent master matches internal address microcontroller slave device, then internal interrupt signal will generated. next following address, which bit, defines read/write status will saved SIMCON1 register. device will then transmit acknowledge bit, which level, bit. microcontroller slave device will also status flag HAAS when addresses match. interrupt come from sources, when program enters interrupt subroutine, HAAS should examined whether interrupt source come from matching slave address from completion data byte transfer. When slave address matched, device must placed either transmit mode then write data SIMDR register, receive mode where must implement dummy read from SIMDR register release line.
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Communication Timing Diagram
SIMCON1 register defines whether microcontroller slave device wishes read data from write data bus. microcontroller should examine this determine transmitter receiver. then this indicates that master wishes read data from bus, therefore microcontroller slave device must setup send data transmitter. then this indicates that master wishes send data bus, therefore microcontroller slave device must setup read data from receiver.
Acknowledge
first last. After receipt 8-bits data, receiver must transmit acknowledge signal, level before receive next data byte. transmitter does receive acknowledge signal from receiver, then will release line master will send STOP signal release control bus. corresponding data will stored SIMDR register. setup transmitter, microcontroller slave device must first write data transmitted into SIMDR register. setup receiver, microcontroller slave device must read transmitted data from SIMDR register.
After master transmitted calling address, slave device bus, whose internal address matches calling address, must generate acknowledge signal. This acknowledge signal will inform master that slave device accepted calling address. acknowledge signal received master then STOP signal must transmitted master communication. When HAAS high, addresses have matched microcontroller slave device must check determine transmitter receiver. high, microcontroller slave device should setup transmitter SIMCON1 register should then microcontroller slave device should setup receiver SIMCON1 register should
Data Byte
Data Timing Diagram
Receive Acknowledge
When receiver wishes continue receive next data byte, must generate acknowledge bit, known TXAK, clock. microcontroller slave device, which setup transmitter will check RXAK SIMCON1 register determine send another data byte, then will release line await receipt STOP signal from master.
transmitted data 8-bits wide transmitted after slave device acknowledged receipt slave address. order serial transmission Rev. 1.20 March 2009
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Flow Chart
Peripheral Clock Output
Peripheral Clock Output allows device supply external hardware with clock signal synchronised microcontroller clock. peripheral clock output pin, PINT, shared with segment line SEG14, required function chosen configuration option. clock source Peripheral Clock Output originate from either Timer/Event Counter divided divided ratio internal fsys clock. clock source selected using PCKEN SIMCON0 register. required division ratio system clock selected using PCKPSC0 PSCPSC1 bits same register. system enters Power down mode this will also influence operation Peripheral Clock Output shown block diagram.
Initialisation Flow Chart
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I/I2C
Module Structure
Peripheral Clock Output Control SIMCON0
Buzzer
Operating similar Programmable Frequency Divider, Buzzer function provides means producing variable frequency output, suitable applications such Piezo-buzzer driving other external circuits that require precise frequency generator. pins form complimentary pair, pin-shared with pins, PA1. configuration option used select from three buzzer options. first option both pins used normal I/Os, second option both pins configured buzzer pins, third option selects only used buzzer with retaining normal function. Note that inverse which together generate differential output which supply more power connected interfaces such buzzers.
buzzer driven internal clock source, which then passes through divider, division ratio which selected configuration options provide range buzzer frequencies from fS/22 fS/29. clock source that generates which turn controls buzzer frequency, originate from three different sources, oscillator, 32K_INT oscillator System oscillator/4, choice which determined clock source configuration option. Note that buzzer frequency controlled configuration options, which select both source clock internal clock internal division ratio. There internal registers associated with buzzer frequency. configuration options have selected both pins function complementary pair buzzer outputs, then correct buzzer operation
Buzzer Function Rev. 1.20 March 2009
HT56R64
essential that both pins must setup outputs setting bits PAC0 PAC1 port control register zero. data data register must also high enable buzzer outputs, low, both pins will remain low. this PA0/PA1 Function Control Register PAC0
stands care stands Data
single register used on/off control both buzzer outputs. Note that data register control over buzzer PA1.
Register PAC1
Data Register
Data Register
Output Function PA0=BZ PA1=BZ PA0=BZ PA1=input line PA1=input line PA0=input line PA1=D PA0=input line PA0=input line
configuration options have selected that only function buzzer pin, then used normal pin. function buzzer pin, must setup output setting PAC0 port control register zero. data data register must also high enable buzzer output, will remain low. this used on/off control buzzer PA0. PAC0 port control register high, then still used input even though configuration option configured buzzer output.
Note that matter what configuration option chosen buzzer, port control register setup function input, then this will override configuration option selection force always behave input pin. This arrangement enables used both buzzer input pin, regardless configuration option chosen; actual function changed dynamically application program programming appropriate port control register bit.
Buzzer Output Control Note: above drawing shows situation where both pins selected configuration option buzzer outputs. Port Control Register both pins must have already been setup output. data setup effect buzzer outputs.
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Interrupts
Interrupts important part microcontroller system. When external event internal function such Timer/Event Counter converter requires microcontroller attention, their corresponding interrupt will enforce temporary suspension main program allowing microcontroller direct attention their respective needs. device contains several external interrupt internal interrupts functions. external interrupts controlled action external INT0, INT1 PINT pins, while internal interrupts controlled Timer/Event Counter overflows, Time Base interrupt, interrupt, SPI/I2C interrupt converter interrupt. Interrupt Registers Overall interrupt control, which means interrupt enabling request flag setting, controlled INTC0, INTC1 MFIC registers, which located Data Memory. controlling appropriate enable bits these registers each individual interrupt enabled disabled. Also when interrupt occurs, corresponding request flag will microcontroller. global enable flag cleared zero will disable interrupts. Interrupt Operation Timer/Event Counter overflow, Time Base, overflow, SPI/I2C data transfer complete, conversion external interrupt line being triggered will generate interrupt request setting their corresponding request flag, their appropriate interrupt enable set. When this happens, Program Counter, which stores address next instruction executed, will transferred onto stack. Program Counter will then loaded with address which will value corresponding interrupt vector. microcontroller will then fetch next instruction from this interrupt vector. instruction this vector will usually statement which will jump another section program which known interrupt service routine. Here located code control appropriate interrupt. interrupt service routine must terminated with RETI statement, which retrieves original Program Counter address from stack allows microcontroller continue with normal execution point where interrupt occurred. various interrupt enable bits, together with their associated request flags, shown accompanying diagram with their order priority. Once interrupt subroutine serviced, other interrupts will blocked, will cleared automatically. This will prevent further interrupt nesting from occurring. However, other interrupt requests occur during this interval, although interrupt will Rev. 1.20 immediately serviced, request flag will still recorded. interrupt requires immediate servicing while program already another interrupt service routine, should after entering routine, allow interrupt nesting. stack full, interrupt request will acknowledged, even related interrupt enabled, until Stack Pointer decremented. immediate service desired, stack must prevented from becoming full. Interrupt Priority Interrupts, occurring interval between rising edges consecutive pulses, will serviced latter pulses, corresponding interrupts enabled. case simultaneous requests, following table shows priority that applied. Interrupt Source External Interrupt External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow SPI/I2C Interrupt Multi-function Interrupt Priority Vector
converter interrupt, Real Time clock interrupt, Time Base interrupt External Peripheral interrupt share same interrupt vector which 18H. Each these interrupts have their individual interrupt flag also share same interrupt flag. flag will cleared hardware once Multi-function interrupt serviced, however individual interrupts that have triggered Multi-function interrupt need cleared application program. External Interrupt external interrupt occur, global interrupt enable bit, EMI, external interrupt enable bits, EEI0 EEI1, must first set. Additionally correct interrupt edge type must selected using INTEDGE register enable external interrupt function choose trigger edge type. actual external interrupt will take place when external interrupt request flag, EIF0 EIF1, set, situation that will occur when transition, whose type chosen edge select bit, appears INT0 INT1 pin. external interrupt pins pin-shared with pins only configured external interrupt pins their corresponding external interrupt enable INTC0 register been set. must also setup input setting corresponding PDC.4 PDC.5 bits port control register. When interrupt enabled, stack full correct transition type appears March 2009
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Interrupt Control Register INTC0
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Interrupt Control Register INTC1
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Interrupt Control Register MFIC
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Interrupt Structure
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external interrupt pin, subroutine call external interrupt vector location 08H, will take place. When interrupt serviced, external interrupt request flags, EIF0 EIF1, will automatically reset will automatically cleared disable other interrupts. Note that pull-high resistor selections this will remain valid even used external interrupt input. INTEDGE register used select type active edge that will trigger external interrupt. choice either rising falling edge types chosen along with option allow both edge types trigger external interrupt. Note that INTEDGE register also used disable external interrupt function.
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external peripheral interrupt occur, global interrupt enable bit, EMI, external peripheral interrupt enable bit, EPI, Multi-function interrupt enable bit, EMFI, must first set. actual external peripheral interrupt will take place when external interrupt request flag, PEF, set, situation that will occur when negative transition, appears PINT pin. external peripheral interrupt pin-shared with segment SEG15, configured peripheral interrupt configuration option. When interrupt enabled, stack full negative transition type appears external peripheral interrupt pin, subroutine call Multi-function interrupt vector location18H, will take place. When external peripheral interrupt serviced, will cleared disable other interrupts, however only interrupt request flag will reset. flag will automatically reset, cleared application program. Timer/Event Counter Interrupt Timer/Event Counter interrupt occur, global interrupt enable bit, EMI, corresponding timer interrupt enable bit, ET0I ET1I, must first set. actual Timer/Event Counter interrupt will take place when Timer/Event Counter request flag, T1F, set, situation that will occur when Timer/Event Counter overflows. When interrupt enabled, stack full Timer/Event Counter overflow occurs, subroutine call timer interrupt vector location 10C, will take place. When interrupt serviced, timer interrupt request flag, T1F, will automatically reset will automatically cleared disable other interrupts. Interrupt Interrupt contained within Multi-function Interrupt. Interrupt generated, global interrupt enable bit, EMI, Interrupt enable bit, EADI, Multi-function interrupt enable bit, EMFI, must first
external interrupt pins connected internal filter reduce possibility unwanted external interrupts adverse noise spikes external interrupt input signal. this internal filter circuit will consume limited amount power, configuration option provided switch filter function, option which beneficial power sensitive applications, which integrity input signal high. Care must taken when using filter on/off configu
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